Search results for "overtesting"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
117	Hui Liu, Huawei Li 0001, Yu Hu 0001, Xiaowei Li 0001	A Scan-Based Delay Test Method for Reduction of Overtesting.	DELTA	2008	DBLP DOI BibTeX RDF	overtesting, SeBoS, delay test, IR drop
91	Ilia Polian, Hideo Fujiwara	Functional Constraints vs. Test Compression in Scan-Based Delay Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Overtesting prevention, Scan-based delay test, Test compression, Functional constraints
91	Ilia Polian, Hideo Fujiwara	Functional constraints vs. test compression in scan-based delay testing.	DATE	2006	DBLP DOI BibTeX RDF	overtesting prevention, scan-based delay test, test compression, functional constraints
63	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudofunctional testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
63	Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz	Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
42	Irith Pomeranz, Sudhakar M. Reddy	Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
28	Kazuteru Namba, Hideo Ito	Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Two-rail logic circuit, overtesting, testability, monotone function, path delay fault testing
28	Irith Pomeranz, Sudhakar M. Reddy	On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance
21	Irith Pomeranz, Sudhakar M. Reddy	Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.	VTS	2008	DBLP DOI BibTeX RDF	functional broadside tests, test generation, transition faults, reachable states, full-scan circuits
21	Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu	On Common-Mode Skewed-Load and Broadside Tests.	VLSI Design	2008	DBLP DOI BibTeX RDF
21	Zahi S. Abuhamdeh, Bob Hannagan, Jeff Remmers, Alfred L. Crouch	A Production IR-Drop Screen on a Chip.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	power-related failures, screen on a chip, power rails, production screen, IR drop
21	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.	DFT	2006	DBLP DOI BibTeX RDF
21	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient techniques for transition testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test chain, test data volume reduction, transition faults, Test application time reduction, yield loss
21	Xiao Liu 0010, Michael S. Hsiao	A Novel Transition Fault ATPG That Reduces Yield Loss.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Hardware I Computing Methodologies
21	Dirk Niggemeyer, Elizabeth M. Rudnick	Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
21	Xiao Liu 0010, Michael S. Hsiao	Constrained ATPG for Broadside Transition Testing.	DFT	2003	DBLP DOI BibTeX RDF