Search results for "pcie"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
164	Venkata Krishnan	Towards an integrated IO and clustering solution using PCI express.	CLUSTER	2007	DBLP DOI BibTeX RDF
117	Matthew J. Koop, Wei Huang 0003, Karthik Gopalakrishnan, Dhabaleswar K. Panda 0001	Performance Analysis and Evaluation of PCIe 2.0 and Quad-Data Rate InfiniBand.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	qdr, pci, infiniband
36	Ray Bittner	Bus mastering PCI express in an FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	bus mastering, pcie, performance, fpga, design, pci express
23	John Park	Thinking outside of the chip.	ISPD	2010	DBLP DOI BibTeX RDF	collaboration, co-design, package, ic, chip, pcb
23	Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer	Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	accelerator space-filling curve, openmp, matrix multiplication, cache-oblivious, lu decomposition, manycore
23	Ying-Wen Bai, Chun-Yang Tsai	Design and implementation of a low-power workstation.	CCECE	2009	DBLP DOI BibTeX RDF
23	Changjian Gao, Shih-Lien Lu	Novel FPGA based Haar classifier face detection algorithm acceleration.	FPL	2008	DBLP DOI BibTeX RDF
23	Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan	ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.	FCCM	2008	DBLP DOI BibTeX RDF
23	Maxim Leonov, Vyacheslav V. Kitaev	Feasibility Study of Implementing Multi-Channel Correlation for DSP Applications on Reconfigurable CPU+FPGA Platform.	PDCAT	2008	DBLP DOI BibTeX RDF
23	Mun Seong Park, Seok Young Kim, Seon Wook Kim	Low Overhead PIM-to-PIM Communication on PCIe-based Multi-PIM Platforms for Executing Large-Scale AI Models.	ICEIC	2024	DBLP DOI BibTeX RDF
23	Wentao Hou, Jie Zhang, Zeke Wang, Ming Liu	Understanding Routable PCIe Performance for Composable Infrastructures.	NSDI	2024	DBLP BibTeX RDF
23	Heehoon Kim, Junyeol Ryu, Jaejin Lee	TCCL: Discovering Better Communication Paths for PCIe GPU Clusters.	ASPLOS (3)	2024	DBLP DOI BibTeX RDF
23	Daniel Suárez, Víctor Fernández 0001, Héctor Posadas, Pablo Sánchez	Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards.	IEEE Embed. Syst. Lett.	2023	DBLP DOI BibTeX RDF
23	Xiaojian Liao, Youyou Lu, Zhe Yang 0012, Jiwu Shu	Efficient Crash Consistency for NVMe over PCIe and RDMA.	ACM Trans. Storage	2023	DBLP DOI BibTeX RDF
23	Anup Das 0001	Preserving Privacy of Neuromorphic Hardware From PCIe Congestion Side-Channel Attack.	COMPSAC	2023	DBLP DOI BibTeX RDF
23	Jianxin Liu, Fuge Wang, Qingkun Zhuo, Xue Yang	PCIE-Based Shared Memory Technology between BMC and CPU.	SPCNC	2023	DBLP DOI BibTeX RDF
23	David Castells-Rufas, Xavier Martorell, Aleix Roca, Alexander Kropotov, Xavier Teruel, Teresa Cervero, John D. Davis	Ethernet Emulation over PCIe for RISC-V Software Development Vehicles.	DCIS	2023	DBLP DOI BibTeX RDF
23	Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong	A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
23	Seung-Ho Lim, Kwangho Cha	Shared Memory Model over a Switchless PCIe NTB Interconnect Network.	J. Inf. Process. Syst.	2022	DBLP DOI BibTeX RDF
23	Tessil Thomas, Bharath Venkatasubramanian, Dinesh Sthapit, Christopher Gray, Atresh Gummadavelly, Janick Bergeron, Pankaj Mehta, Prabu Thangamuthu	Left-shifter: A pre-silicon framework for usage model based performance verification of the PCIe interface in server processor system on chips.	ISPASS	2022	DBLP DOI BibTeX RDF
23	Mert Side, Fan Yao, Zhenkai Zhang	LockedDown: Exploiting Contention on Host-GPU PCIe Bus for Fun and Profit.	EuroS&P	2022	DBLP DOI BibTeX RDF
23	Yibo Huang 0005, Yukai Huang, Ming Yan, Jiayu Hu, Cunming Liang, Yang Xu, Wenxiong Zou, Yiming Zhang 0018, Rui Zhang, Chunpu Huang, Jie Wu 0003	An ultra-low latency and compatible PCIe interconnect for rack-scale communication.	CoNEXT	2022	DBLP DOI BibTeX RDF
23	Mohamed Amine Khelif, Jordane Lorandel, Olivier Romain	Experimental interfacing with the IPhone 6s through its PCIe communication bus.	ISIE	2022	DBLP DOI BibTeX RDF
23	Hodong Kim, Junbeom Hur	PCIe Side-channel Attack on I/O Device via RDMA-enabled Network Card.	ICTC	2022	DBLP DOI BibTeX RDF
23	Toshiya Matsuda, Kota Nishiyama, Kana Masumoto, Masahiro Nakagawa, Takashi Miyamura	Ultra-Low Latency Short Packet Transmission Experiments with Optical Bus Platform Based on PCIe.	OFC	2022	DBLP BibTeX RDF
23	Usman Ali, Salman Abdul Khaliq, Omer Khan	Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware.	ISQED	2022	DBLP DOI BibTeX RDF
23	Myoungsoo Jung	Hello bytes, bye blocks: PCIe storage meets compute express link for memory expansion (CXL-SSD).	HotStorage	2022	DBLP DOI BibTeX RDF
23	Jieun Choi, Yosang Jeong, Ji Hoon Kang 0002, Gibeom Gu, Hoon Ryu	Empirical Study on the GPU-accelerated HPL Performance: Effects of PCIe Communication.	CLUSTER	2022	DBLP DOI BibTeX RDF
23	Guangming Tan, Chaoyang Shui, Yinshan Wang, Xianzhi Yu, Yujin Yan	Optimizing the LINPACK Algorithm for Large-Scale PCIe-Based CPU-GPU Heterogeneous Systems.	IEEE Trans. Parallel Distributed Syst.	2021	DBLP DOI BibTeX RDF
23	Piyush Manavar, Manoj Nambiar 0001, Nupur Sumeet, Rekha Singhal, Sharod Choudhary, Amey Pandit	Experience with PCIe streaming on FPGA for high throughput ML inferencing.	CoRR	2021	DBLP BibTeX RDF
23	Tse-Yuan Wang, Chun-Feng Wu, Che-Wei Tsao, Yuan-Hao Chang 0001, Tei-Wei Kuo	Scheduling-Aware Prefetching: Enabling the PCIe SSD to Extend the Global Memory of GPU Device.	NVMSA	2021	DBLP DOI BibTeX RDF
23	Chan-Ho Park, Won-Ok Kwon, Myeong-Hoon Oh, Cheol-Hoon Lee	PCIe Bridge Hardware for Gen-Z Memory System.	ICEIC	2021	DBLP DOI BibTeX RDF
23	Shanquan Tian, Ilias Giechaskiel, Wenjie Xiong 0001, Jakub Szefer	Cloud FPGA Cartography using PCIe Contention.	FCCM	2021	DBLP DOI BibTeX RDF
23	Zhonghao Zhang, Zhengxiang Li	ARM and FPGA Heterogeneous Accelerated Processing System Based on HLS and PCIe.	ICICT	2021	DBLP DOI BibTeX RDF
23	Mingtian Tan, Junpeng Wan, Zhe Zhou 0001, Zhou Li 0001	Invisible Probe: Timing Attacks with PCIe Congestion Side-channel.	SP	2021	DBLP DOI BibTeX RDF
23	Salman Abdul Khaliq, Usman Ali, Omer Khan	Timing-based side-channel attack and mitigation on PCIe connected distributed embedded systems.	HPEC	2021	DBLP DOI BibTeX RDF
23	Yiltan Hassan Temuçin, Amir Hossein Sojoodi, Pedram Alizadeh, Ahmad Afsahi	Efficient Multi-Path NVLink/PCIe-Aware UCX based Collective Communication for Deep Learning.	HOTI	2021	DBLP DOI BibTeX RDF
23	Jonas Markussen, Lars Bjørlykke Kristiansen, Pål Halvorsen, Halvor Kielland-Gyrud, Håkon Kvale Stensland, Carsten Griwodz	SmartIO: Zero-overhead Device Sharing through PCIe Networking.	ACM Trans. Comput. Syst.	2020	DBLP DOI BibTeX RDF
23	Ang Li 0006, Shuaiwen Leon Song, Jieyang Chen, Jiajia Li 0001, Xu Liu 0001, Nathan R. Tallent, Kevin J. Barker	Evaluating Modern GPU Interconnect: PCIe, NVLink, NV-SLI, NVSwitch and GPUDirect.	IEEE Trans. Parallel Distributed Syst.	2020	DBLP DOI BibTeX RDF
23	Mohamed Amine Khelif, Jordane Lorandel, Olivier Romain, Matthieu Regnery, Denis Baheux, Guillaume Barbu	Toward a hardware man-in-the-middle attack on PCIe bus.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
23	Nikhil Khatri, Shirshendu Chakrabarti	NVMe and PCIe SSD Monitoring in Hyperscale Data Centers.	CoRR	2020	DBLP BibTeX RDF
23	Jonas Markussen, Lars Bjørlykke Kristiansen, Rune Johan Borgli, Håkon Kvale Stensland, Friedrich Seifert, Michael Riegler 0001, Carsten Griwodz, Pål Halvorsen	Flexible device compositions and dynamic resource sharing in PCIe interconnected clusters using Device Lending.	Clust. Comput.	2020	DBLP DOI BibTeX RDF
23	Yohei Kuga, Ryo Nakamura, Takeshi Matsuya, Yuji Sekiya	NetTLP: A Development Platform for PCIe devices in Software Interacting with Hardware.	NSDI	2020	DBLP BibTeX RDF
23	Gyuyoung Park, Myoungsoo Jung	Automatic-SSD: Full Hardware Automation over New Memory for High Performance and Energy Efficient PCIe Storage Cards.	ICCAD	2020	DBLP DOI BibTeX RDF
23	Chen Li 0015, Jun Yang 0002, Yifan Sun 0002, Lingling Jin, Lingjie Xu, Zheng Cao, Pengfei Fan, David R. Kaeli, Sheng Ma, Yang Guo 0003	Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
23	Cheol Shim, Rupali Kiran Shinde, Min Choi	Compatibility enhancement and performance measurement for socket interface with PCIe interconnections.	Hum. centric Comput. Inf. Sci.	2019	DBLP DOI BibTeX RDF
23	Ang Li 0006, Shuaiwen Leon Song, Jieyang Chen, Jiajia Li 0001, Xu Liu 0001, Nathan R. Tallent, Kevin J. Barker	Evaluating Modern GPU Interconnect: PCIe, NVLink, NV-SLI, NVSwitch and GPUDirect.	CoRR	2019	DBLP BibTeX RDF
23	Cheol Shim, Kwangho Cha, Min Choi	Design and implementation of initial OpenSHMEM on PCIe NTB based cloud computing.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
23	Yingxiao Zhao, Xin Liu, Jiong Yang	A resource and timing optimized PCIe DMA architecture using FPGA internal data buffer.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
23	Mohamed Amine Khelif, Jordane Lorandel, Olivier Romain, Matthieu Regnery, Denis Baheux, Guillaume Barbu	Toward a Hardware Man-in-the-Middle Attack on PCIe Bus for Smart Data Replay.	DSD	2019	DBLP DOI BibTeX RDF
23	Vijendra V., Meghana Kulkarni, Rajesh Murgan	ECG Pattern Recognition and Beat Classification using Internet of Things and Hardware Acceleration on ZynQ (SOC) Platform with High Performance Computational PCIe Protocol.	BIODEVICES	2019	DBLP DOI BibTeX RDF
23	Seung-Ho Lim, Ki-Woong Park, Kwangho Cha	Developing an OpenSHMEM Model Over a Switchless PCIe Non-Transparent Bridge Interface.	IPDPS Workshops	2019	DBLP DOI BibTeX RDF
23	Ralf Kundel, Tim Burkert, Carsten Griwodz, Boris Koldehofe	Chaining of hardware accelerated Virtual Network Functions in PCIe Environments.	Middleware Demos/Posters	2019	DBLP DOI BibTeX RDF
23	Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam 0004, Donald W. Plass, Paul Muench	The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
23	Bruno da Silva 0001, An Braeken, Federico Domínguez, Abdellah Touhafi	Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator.	Int. J. Reconfigurable Comput.	2018	DBLP DOI BibTeX RDF
23	Burak Batmaz, Atakan Dogan	1 Gbit/s UDP/IP Offload Engine IP Core with PCIe Interface.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
23	Hongxu Jiang, Shenglan Li, Huiyong Li, Tingshan Liu, Jinyuan Lu	A High-Performance and Hardware-Efficient PCIe Transmission for a Multi-Channel Video Using Command Caching and Dynamic Splicing on FPGA.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
23	Dimitrios Mbakoyiannis, Othon Tomoutzoglou, George Kornaros	Energy-Performance Considerations for Data Offloading to FPGA-Based Accelerators Over PCIe.	ACM Trans. Archit. Code Optim.	2018	DBLP DOI BibTeX RDF
23	Kun Cheng, Weiyue Liu, Qi Shen, Shengkai Liao	Design and Implementation of High-throughput PCIe with DMA Architecture between FPGA and PowerPC.	CoRR	2018	DBLP BibTeX RDF
23	Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter A. Milder	A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
23	Rolf Neugebauer, Gianni Antichi, José Fernando Zazo, Yury Audzevich, Sergio López-Buedo, Andrew W. Moore 0002	Understanding PCIe performance for end host networking.	SIGCOMM	2018	DBLP DOI BibTeX RDF
23	William Cheng-Chun Tu, Tzi-cker Chiueh	Seamless Fail-over for PCIe Switched Networks.	SYSTOR	2018	DBLP DOI BibTeX RDF
23	Jonas Markussen, Lars Bjørlykke Kristiansen, Håkon Kvale Stensland, Friedrich Seifert, Carsten Griwodz, Pål Halvorsen	Flexible Device Sharing in PCIe Clusters using Device Lending.	ICPP Workshops	2018	DBLP DOI BibTeX RDF
23	Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton	A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
23	Tingshan Liu, Hongxu Jiang, Huiyong Li, Bo Li 0006, Miyi Duan	Efficient PCIe transmission for Multi-Channel video using dynamic splicing and conditional prefetching.	Multim. Tools Appl.	2017	DBLP DOI BibTeX RDF
23	Yang Ou, Nong Xiao, Fang Liu 0002, Zhiguang Chen, Wei Chen 0009, Lizhou Wu	Gemini: A Novel Hardware and Software Implementation of High-performance PCIe SSD.	Int. J. Parallel Program.	2017	DBLP DOI BibTeX RDF
23	Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku	Thorough analysis of PCIe Gen3 communication.	ReConFig	2017	DBLP DOI BibTeX RDF
23	Eyal Rozenberg, Peter A. Boncz	Faster across the PCIe bus: a GPU library for lightweight decompression: including support for patched compression schemes.	DaMoN	2017	DBLP DOI BibTeX RDF
23	Seonbong Kim, Joon-Sung Yang	Improving NVMe SSD I/O determinism with PCIe virtual channel: work-in-progress.	CASES	2017	DBLP DOI BibTeX RDF
23	Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam 0004, Juergen Pille, Donald W. Plass	3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.	ISSCC	2017	DBLP DOI BibTeX RDF
23	Mahesh Chaudhari, Kedar Kulkarni, Shreeya Badhe, Vandana Inamdar	Evaluating Effect of Write Combining on PCIe Throughput to Improve HPC Interconnect Performance.	CLUSTER	2017	DBLP DOI BibTeX RDF
23	Andre Oliver Richter	Mitigating and Resolving Performance Isolation Issues of PCIe Passthrough and SR-IOV in Multi-Core Virtualization.		2017	RDF
23	Andre Oliver Richter, Christian Herber, Thomas Wild, Andreas Herkersdorf	Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions.	DSD	2016	DBLP DOI BibTeX RDF
23	Liuhang Zhang, Rui Hou 0001, Sally A. McKee, Jianbo Dong, Lixin Zhang 0002	P-Socket: optimizing a communication library for a PCIe-based intra-rack interconnect.	Conf. Computing Frontiers	2016	DBLP DOI BibTeX RDF
23	Mohd Amiruddin Zainol, José Luis Núñez-Yáñez	CPCIe: A compression-enabled PCIe core for energy and performance optimization.	NORCAS	2016	DBLP DOI BibTeX RDF
23	Shin Morishima, Hiroki Matsutani	Distributed In-GPU Data Cache for Document-Oriented Data Store via PCIe over 10 Gbit Ethernet.	Euro-Par Workshops	2016	DBLP DOI BibTeX RDF
23	Maxime Martinasso, Grzegorz Kwasniewski, Sadaf R. Alam, Thomas C. Schulthess, Torsten Hoefler	A PCIe congestion-aware performance model for densely populated accelerator servers.	SC	2016	DBLP DOI BibTeX RDF
23	Mayank Daga	On the Acceleration of Graph500: Characterizing PCIe Overheads with Multi-GPUs.	VECPAR	2016	DBLP DOI BibTeX RDF
23	Janki Bhimani, Miriam Leeser, Ningfang Mi	Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus.	HPEC	2016	DBLP DOI BibTeX RDF
23	Francisco D. Igual, Luis M. Jara, José Ignacio Gómez Pérez, Luis Piñuel, Manuel Prieto-Matías	A power measurement environment for PCIe accelerators.	Comput. Sci. Res. Dev.	2015	DBLP DOI BibTeX RDF
23	Yann Thoma, Alberto Dassatti, Daniel Molla, Enrico Petraglio	FPGA-GPU communicating through PCIe.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
23	Jose Fernando Zazo, Sergio López-Buedo, Yury Audzevich, Andrew W. Moore 0002	A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances.	ReConFig	2015	DBLP DOI BibTeX RDF
23	Dawei Zang, Zheng Cao, Xiaoli Liu 0002, Lin Wang 0015, Zhan Wang, Ninghui Sun	PROP: Using PCIe-Based RDMA to Accelerate Rack-Scale Communications in Data Centers.	ICPADS	2015	DBLP DOI BibTeX RDF
23	Yuetsu Kodama, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato	PEACH2: An FPGA-based PCIe network device for Tightly Coupled Accelerators.	SIGARCH Comput. Archit. News	2014	DBLP DOI BibTeX RDF
23	Takashi Yoshikawa, Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Shinji Abe	Bridge chip composing a PCIe switch over ethernet to make a seamless disaggregated computer in data-center scale.	Hot Chips Symposium	2014	DBLP DOI BibTeX RDF
23	Jian Gong, Jiahua Chen, Haoyang Wu, Fan Ye 0003, Songwu Lu, Jason Cong, Tao Wang 0004	EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
23	Daniel Münch, Michael Paulitsch, Andreas Herkersdorf	Temporal Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using PCIe SR-IOV.	ARCS Workshops	2014	DBLP BibTeX RDF
23	Thomas B. Preußer, Rainer G. Spallek	Ready PCIe data streaming solutions for FPGAs.	FPL	2014	DBLP DOI BibTeX RDF
23	Jian Gong, Tao Wang 0004, Jiahua Chen, Haoyang Wu, Fan Ye 0003, Songwu Lu, Jason Cong	An efficient and flexible host-FPGA PCIe communication library.	FPL	2014	DBLP DOI BibTeX RDF
23	Simon Pickartz, Pablo Reble, Carsten Clauss, Stefan Lankes	SWIFT: A Transparent and Flexible Communication Layer for PCIe-Coupled Accelerators and (Co-)Processors.	IPDPS Workshops	2014	DBLP DOI BibTeX RDF
23	Hendrik Noll, Sebastian Siegert, Johannes Hiltscher, Wolfgang Rehm	UTOPIA: Generic User-Level Access to the Physical Memory Address Space for IP Core Debugging and Validation on FPGA Based PCIe Extension Cards.	FCCM	2014	DBLP DOI BibTeX RDF
23	Oliver Sander, Steffen Baehr, Enno Lübbers, Timo Sandmann, Viet Vu Duy, Jürgen Becker 0001	A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization.	FPT	2014	DBLP DOI BibTeX RDF
23	Eleni Bougioukou, Athina Ntalla, Aspa Palli, Maria Varsamou, Theodore Antonakopoulos 0001	Prototyping and performance evaluation of a dynamically adaptable block device driver for PCIe-based SSDs.	RSP	2014	DBLP DOI BibTeX RDF
23	Carlos Reaño, Federico Silla, Antonio J. Peña, Gilad Shainer, Scot Schultz, Adrián Castelló 0001, Enrique S. Quintana-Ortí, José Duato	Boosting the performance of remote GPU virtualization using InfiniBand connect-IB and PCIe 3.0.	CLUSTER	2014	DBLP DOI BibTeX RDF
23	Koen Lostrie, Paul De Meulenaere, Marijn Temmerman, Nick Van Remortel, W. P. Beaumont	Benchmarking of PCIe-Performance in MicroTCA-Equipment.	3PGCIC	2013	DBLP DOI BibTeX RDF
23	Amber Huffman	Delivering the full potential of PCIe storage.	Hot Chips Symposium	2013	DBLP DOI BibTeX RDF
23	Frank Martin, Peter Bennett 0002	Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples.	DATE	2013	DBLP DOI BibTeX RDF
23	Yann Thoma, Alberto Dassatti, Daniel Molla	FPGA2: An open source framework for FPGA-GPU PCIe communication.	ReConFig	2013	DBLP DOI BibTeX RDF
23	Sambit Kumar Shukla, Laxmi N. Bhuyan	A hybrid shared memory heterogeneous execution platform for PCIe-based GPGPUs.	HiPC	2013	DBLP DOI BibTeX RDF
23	Sambit Kumar Shukla, Yang Yang 0111, Laxmi N. Bhuyan, Philip Brisk	Shared memory heterogeneous computation on PCIe-supported platforms.	FPL	2013	DBLP DOI BibTeX RDF