Search results for "ported"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
84	Hao Zhang 0009, Dongrui Fan	Simplified Multi-Ported Cache in High Performance Processor.	IEEE NAS	2007	DBLP DOI BibTeX RDF
65	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
65	Kathryn Bassin, Padmanabhan Santhanam	Managing the Maintenance of Ported, Outsourced, and Legacy Software via Orthogonal Defect Classification.	ICSM	2001	DBLP DOI BibTeX RDF	ODC, testing, maintenance, outsourced, ported, software evaluation, defect analysis, legacy
59	Kenneth M. Wilson, Kunle Olukotun	High Bandwidth On-Chip Cache Design.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth
55	Aneesh Aggarwal, Manoj Franklin	Energy Efficient Asymmetrically Ported Register Files.	ICCD	2003	DBLP DOI BibTeX RDF
55	Khoan Truong	A Simple Built-In Self Test For Dual Ported SRAMs.	MTDT	2000	DBLP DOI BibTeX RDF
49	Todd M. Austin, Gurindar S. Sohi	High-Bandwidth Address Translation for Multiple-Issue Processors.	ISCA	1996	DBLP DOI BibTeX RDF
45	Bernard Marechal, P. H. Rausch Bello, Diego Moreira de Araujo Carvalho, Rafael Mayo 0001	Applications ported to the EELA e-Infrastructure.	CCGRID	2007	DBLP DOI BibTeX RDF
39	Mark Hennessy, James F. Power	Ensuring behavioural equivalence in test-driven porting.	CASCON	2006	DBLP DOI BibTeX RDF
39	Kenneth M. Wilson, Kunle Olukotun, Mendel Rosenblum	Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors.	ISCA	1996	DBLP DOI BibTeX RDF
39	Marc Tremblay, Bill Joy 0001, Ken Shin	A three dimensional register file for superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
35	Ge Zhang, Xu Yang, Yiwei Zhang	Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File.	NAS	2009	DBLP DOI BibTeX RDF
35	Mazen A. R. Saghir, Rawan Naous	A Configurable Multi-ported Register File Architecture for Soft Processor Cores.	ARC	2007	DBLP DOI BibTeX RDF
35	Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch	Application of Multi-ported CAM for Parallel Coding.	APCCAS	2006	DBLP DOI BibTeX RDF
35	Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm	ESTIMA: an architectural-level power estimator for multi-ported pipelined register files.	ISLPED	2003	DBLP DOI BibTeX RDF	power estimation, register files, area estimation
35	Yuh-Shyan Chen, Che-Yi Chen, Yu-Chee Tseng	Multi-node Broadcasting in All-Ported 3-D Wormhole-Routed Torus Using Aggregation-then-Distribution Strategy.	ISHPC	2000	DBLP DOI BibTeX RDF
29	Sandeep Sirsi, Aneesh Aggarwal	Exploring the Limits of Port Reduction in Centralized Register Files.	VLSI Design	2009	DBLP DOI BibTeX RDF
29	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal	Very wide register: an asymmetric register file organization for low power embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
29	Yixin Shi, Gyungho Lee	Dynamic Partition of Memory Reference Instructions - A Register Guided Approach.	Euro-Par	2005	DBLP DOI BibTeX RDF
29	Anupam Bhide, E. N. Elnozahy, Stephen P. Morgan, A. Siegel	A comparison of two approaches to build reliable distributed file servers.	ICDCS	1991	DBLP DOI BibTeX RDF
29	Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram	Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power TLB, multi-ported memory structures, energy optimization, low-power cache
25	Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	Designing low-diameter interconnection networks with multi-ported host-switch graphs.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
25	Hanan Marinberg, Esteban Garzón, Tzachi Noy, Marco Lanuzza, Adam Teman	Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach.	IEEE Access	2023	DBLP DOI BibTeX RDF
25	Chia-Chen Yen, Mi-Yen Yeh, Ming-Syan Chen	Integrated Multi-Ported Memory Distribution for Temporal-Multiplexing Workloads on FPGAs.	ICFPT	2023	DBLP DOI BibTeX RDF
25	Mohammad Zubair, Aaron Walden, Gabriel Nastac, Eric J. Nielsen, Christoph Bauinger, Xiao Zhu 0002	Optimization of Ported CFD Kernels on Intel Data Center GPU Max 1550 using oneAPI ESIMD.	SC Workshops	2023	DBLP DOI BibTeX RDF
25	Hao Luan, Yu Yao, Chang Huang	A Many-ported and Shared Memory Architecture for High-Performance ADAS SoCs.	CoRR	2022	DBLP DOI BibTeX RDF
25	Hao Luan, Yu Yao, Chang Huang	A Many-Ported and Shared Memory Architecture for High-Performance ADAS SoCs.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF
25	Mufan Xiang, Yongjian Li, Sijun Tan, Yongxin Zhao, Yiwei Chi	Parameterized Design and Formal Verification of Multi-ported Memory.	ICECCS	2022	DBLP DOI BibTeX RDF
25	S. Navid Shahrouzi, Arkan Alkamil, Darshika G. Perera	Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs.	IEEE Access	2020	DBLP DOI BibTeX RDF
25	Jesper Larsson Träff	k-ported vs. k-lane Broadcast, Scatter, and Alltoall Algorithms.	CoRR	2020	DBLP BibTeX RDF
25	Hao Luan, Alan Gatherer	Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture.	CoRR	2020	DBLP BibTeX RDF
25	Hao Luan, Alan Gatherer	Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture.	NOCS	2020	DBLP DOI BibTeX RDF
25	Bo-Ya Chen, Bo-En Chen, Bo-Cheng Lai	Efficient Write Scheme for Algorithm-Based Multi-Ported Memory.	VLSI-DAT	2019	DBLP DOI BibTeX RDF
25	Janusz Jaworski, Waldemar Karwowski, Marian Rusek	Microservice-Based Cloud Application Ported to Unikernels: Performance Comparison of Different Technologies.	ISAT (1)	2019	DBLP DOI BibTeX RDF
25	S. Navid Shahrouzi, Darshika G. Perera	Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs.	SoCC	2018	DBLP DOI BibTeX RDF
25	S. Navid Shahrouzi, Darshika G. Perera	An efficient embedded multi-ported memory architecture for next-generation FPGAs.	ASAP	2017	DBLP DOI BibTeX RDF
25	Sungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg	A case for standard-cell based RAMs in highly-ported superscalar processor structures.	ISQED	2017	DBLP DOI BibTeX RDF
25	Ameer M. S. Abdelhadi, Guy G. F. Lemieux	A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs.	FCCM	2016	DBLP DOI BibTeX RDF
25	Dilip Bhavsar, Michael Lohmiller, Pankaj Pant	Lateral coupling faults in multi-ported register files and methods for their testing.	VTS	2016	DBLP DOI BibTeX RDF
25	Akshata Anil Muddebihal, Carla Purdy	Design and implementation of area efficient multi-ported memories with write conflict resolution.	MWSCAS	2015	DBLP DOI BibTeX RDF
25	Joost Hoozemans, Jens Johansen, Jeroen van Straten, Anthony Brandon, Stephan Wong	Multiple contexts in a multi-ported VLIW register file implementation.	ReConFig	2015	DBLP DOI BibTeX RDF
25	Jiun-Liang Lin, Bo-Cheng Charles Lai	BRAM efficient multi-ported memory on FPGA.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
25	Charles Eric LaForest, Zimo Li, Tristan O'rourke, Ming G. Liu, J. Gregory Steffan	Composing Multi-Ported Memories on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2014	DBLP DOI BibTeX RDF
25	Ameer Abdelhadi, Guy G. F. Lemieux	Modular multi-ported SRAM-based memories.	FPGA	2014	DBLP DOI BibTeX RDF
25	Igor Loi, Luca Benini	A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms.	DATE	2014	DBLP DOI BibTeX RDF
25	Eckhard Bick	ML-Optimization of Ported Constraint Grammars.	LREC	2014	DBLP BibTeX RDF
25	Stephen Richardson, Ofer Shacham, Dejan Markovic, Mark Horowitz	An area-efficient minimum-time FFT schedule using single-ported memory.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
25	Baishakhi Ray, Miryung Kim, Suzette Person, Neha Rungta	Detecting and characterizing semantic inconsistencies in ported code.	ASE	2013	DBLP DOI BibTeX RDF
25	Jaime Ibar, Gonzalo Ruiz, Ruben Valles, Alfonso Tarancón	OptiWeb: An Optimization Application for Steel Cutting Industries Ported to the Grid in the Framework of PireGrid Project.	Comput. Informatics	2012	DBLP BibTeX RDF
25	Tim Güneysu	Using Data Contention in Dual-ported Memories for Security Applications.	J. Signal Process. Syst.	2012	DBLP DOI BibTeX RDF
25	Charles Eric LaForest, Ming G. Liu, Emma Rae Rapati, J. Gregory Steffan	Multi-ported memories for FPGAs via XOR.	FPGA	2012	DBLP DOI BibTeX RDF
25	Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux	Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew.	FPT	2012	DBLP DOI BibTeX RDF
25	Vincent Boulos, Vincent Fristot, Dominique Houzet, Luc Salvo, Pierre Lhuissier	Investigating performance variations of an optimized GPU-ported granulometry algorithm.	DASIP	2012	DBLP BibTeX RDF
25	Holger Lange, Thorsten Wink, Andreas Koch 0001	MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers.	DATE	2011	DBLP DOI BibTeX RDF
25	Tan-Hsiung Ho, Wei-Jen Chen, Shyh-Jong Chung	A 2-D Amplifying Array Using Multi-Ported Aperture-Coupled Patch Antennas.	IEICE Trans. Commun.	2009	DBLP DOI BibTeX RDF
25	Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch	Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory.	IEICE Trans. Inf. Syst.	2007	DBLP DOI BibTeX RDF
25	Yuuichirou Ikeda, Masaya Sumita, Makoto Nagata	Multi-Ported Register File for Reducing the Impact of PVT Variation.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
25	Yuh-Shyan Chen, Chao-Yu Chiang, Che-Yi Chen	Multi-node broadcasting in all-ported 3-D wormhole-routed torus using an aggregation-then-distribution strategy.	J. Syst. Archit.	2004	DBLP DOI BibTeX RDF
25	Tatsuya Abe 0001	A Concurrent System of Multi-ported Processes with Causal Dependency.	APLAS	2004	DBLP DOI BibTeX RDF
25	Christos Bouras, Apostolos Gkamas, Anastasios Karaliotas, Dimitris Primpas, Kostas Stamos	Issues for the Performance Monitoring of an Open Source H.323 Implementation Ported to IPv6-Enabled Networks with QoS Characteristics.	International Conference on Internet Computing	2003	DBLP BibTeX RDF
25	Susan Schreibman	The Text Ported.	Lit. Linguistic Comput.	2002	DBLP DOI BibTeX RDF
25	Atila Alvandpour, Ram Krishnamurthy 0001, Krishnamurthy Soumyanath, Shekhar Borkar	A low-leakage dynamic multi-ported register file in 0.13mm CMOS.	ISLPED	2001	DBLP DOI BibTeX RDF
25	Hyuk-Jun Lee, Albert A. Liddicoat, Michael J. Flynn	Exploiting Parallelism and Data Locality of Systolic Array Applications using Multi-Ported FPGA.	PDPTA	2000	DBLP BibTeX RDF
25	Roberto Pomponi, M. Busuoli, P. D'Atanasio, E. Rubino, M. Bandinelli, F. Bessi, Matteo Beccaria, G. Cella, Alberto Ciampa, Giuseppe Curci, Andrea Vicerè	Validation and Performance Analysis of a Parallel Ported Code for Simulating the Effects of Lightning Strokes on Telecommunication Buildings.	HPCN	1997	DBLP DOI BibTeX RDF
25	Silvia M. Müller, Uzi Vishkin	Conflict-Free Access to Multiple Single-Ported Register Files.	IPPS	1997	DBLP DOI BibTeX RDF
25	K. V. M. Deva Raju, S. V. Subba Rao, K. V. Srinivasan, K. Visvanathan	Multichannel real-time data acquisition system using dual ported FIFO buffers.	Microprocess. Microsystems	1994	DBLP DOI BibTeX RDF
25	Andrew Wolfe, Rodney Boleyn	Two-ported cache alternatives for superscalar processors.	MICRO	1993	DBLP DOI BibTeX RDF
25	N. Jagadish, J. Mohan Kumar, Lalit M. Patnaik	An efficient scheme for interprocessor communication using dual-ported RAMs.	IEEE Micro	1989	DBLP DOI BibTeX RDF
25	Seth Chaiken	The Tutte polynomial of a ported matroid.	J. Comb. Theory, Ser. B	1989	DBLP DOI BibTeX RDF
20	Feng Xia 0001, Longhua Ma, Zhe Peng	Programming scilab in ARM linux.	ACM SIGSOFT Softw. Eng. Notes	2008	DBLP DOI BibTeX RDF	embedded systems, programming, linux, open source software, ARM, scilab
20	Károly Sándor, Miklós Kozlovszky, Viktor Kamarás, Levente Ficsór, S. Viktor Varga, Béla Molnár	Porting a 3D image registration application to multi-core environment.	SpringSim	2008	DBLP DOI BibTeX RDF	3D image registration, application porting, digital microscopy, virtual microscopy, parallel programming
20	Dimitris Skouteris, Alessandro Costantini, Antonio Laganà, Gergely Sipos, Ákos Balaskó, Péter Kacsuk	Implementation of the ABC Quantum Mechanical Reactive Scattering Program on the EGEE Grid Platform.	ICCSA (1)	2008	DBLP DOI BibTeX RDF
20	Ningning Zhu, Tzi-cker Chiueh	Portable and Efficient Continuous Data Protection for Network File Servers.	DSN	2007	DBLP DOI BibTeX RDF
20	Daniel Sánchez 0003, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam	Implementing Signatures for Transactional Memory.	MICRO	2007	DBLP DOI BibTeX RDF
20	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip.	ASP-DAC	2007	DBLP DOI BibTeX RDF
20	Arun Kumar 0004, Naresh Jayam, Ashok Srinivasan, Ganapathy Senthilkumar, Pallav K. Baruah, Shakti Kapoor, Murali Krishna, Raghunath Sharma	Feasibility study of MPI implementation on the heterogeneous multi-core cell BETM architecture.	SPAA	2007	DBLP DOI BibTeX RDF	cell BE™ processor, heterogeneous multi-core processors, MPI
20	Dionisios N. Pnevmatikatos, Aggelos Arelakis	Variable-Length Hashing for Exact Pattern Matching.	FPL	2006	DBLP DOI BibTeX RDF
20	Yi Wang 0016, Jussipekka Leiwo, Thambipillai Srikanthan	Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications].	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Complexity-Effective Reorder Buffer Designs for Superscalar Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
20	G. Surendra, Subhasis Banerjee, S. K. Nandy 0001	On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort.	WMPI	2004	DBLP DOI BibTeX RDF	cache traffic, intrusion detection, pattern matching, network processor, instruction reuse
20	Christos Bouras, Apostolos Gkamas, Dimitris Primpas, Kostas Stamos	Performance Evaluation of an IPv6-capable H323 Application.	AINA (1)	2004	DBLP DOI BibTeX RDF
20	Gurashish Singh Brar, Susmit Biswas, Sudipta Kundu, Arijit Mukhopadhyay, Pratik Worah, Anupam Basu	OaSis: An Application Specific Operating System for an Embedded Environment.	VLSI Design	2004	DBLP DOI BibTeX RDF
20	T. N. Vijaykumar, Irith Pomeranz, Karl Cheng	Transient-Fault Recovery Using Simultaneous Multithreading.	ISCA	2002	DBLP DOI BibTeX RDF
20	Xianglong Huang, Steve Carr 0001, Philip H. Sweany	Loop Transformations for Architectures with Partitioned Register Banks.	LCTES/OM	2001	DBLP DOI BibTeX RDF
20	Daranee Hormdee, Jim D. Garside	AMULET3i Cache Architecture.	ASYNC	2001	DBLP DOI BibTeX RDF
20	David Gregg, M. Anton Ertl, Andreas Krall	Implementing an Efficient Java Interpreter.	HPCN	2001	DBLP DOI BibTeX RDF
20	Adrian Stoica, Didier Keymeulen, Raoul Tawel, Carlos Salazar-Lazaro, Wei-Te Li	Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
20	Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin	On High-Bandwidth Data Cache Design for Multi-Issue Processors.	MICRO	1997	DBLP DOI BibTeX RDF	Locality-Based Interleaving, Multiporting, High-Bandwidth Data Supply, Multi-Bank Caches
20	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor.	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
20	Kenneth M. Wilson, Kunle Olukotun	Designing High Bandwidth On-Chip Caches.	ISCA	1997	DBLP DOI BibTeX RDF
20	Jan Hoogerbrugge, Henk Corporaal	Register file port requirements of transport triggered architectures.	MICRO	1994	DBLP DOI BibTeX RDF
20	James D. Mooney	A course in software portability.	SIGCSE	1992	DBLP DOI BibTeX RDF
20	G. B. Bonkowski, W. Morven Gentleman, M. A. Malcolm	Porting the Zed compiler.	SIGPLAN Symposium on Compiler Construction	1979	DBLP DOI BibTeX RDF
20	David R. Cheriton, Michael A. Malcolm, Lawrence S. Melen, Gary R. Sager	Thoth, a Portable Real-Time Operating System (Extended Abstract). (long version: CACM)	SOSP	1977	DBLP DOI BibTeX RDF	Thoth
10	Albrecht Schmidt 0001	Engineering interactive ubiquitous computing systems.	EICS	2011	DBLP DOI BibTeX RDF
10	Heidi Pan, Benjamin Hindman, Krste Asanovic	Composing parallel software efficiently with lithe.	PLDI	2010	DBLP DOI BibTeX RDF	cooperative scheduling, oversubscription, user-level scheduling, parallelism, resource management, composability, hierarchical scheduling
10	Brian Demsky, Patrick Lam 0001	Views: object-inspired concurrency control.	ICSE (1)	2010	DBLP DOI BibTeX RDF	concurrency, language design, static verification
10	Daniel Lupei, Bogdan Simion, Don Pinto, Matthew Misler, Mihai Burcea, William Krick, Cristiana Amza	Transactional memory support for scalable and transparent parallelization of multiplayer games.	EuroSys	2010	DBLP DOI BibTeX RDF	scalability, load balancing, synchronization, software transactional memory, massively multiplayer games
10	Daniel Lupei, Bogdan Simion, Don Pinto, Matthew Misler, Mihai Burcea, William Krick, Cristiana Amza	Towards scalable and transparent parallelization of multiplayer games using transactional memory support.	PPoPP	2010	DBLP DOI BibTeX RDF	scalability, synchronization, software transactional memory, massively multiplayer games
10	Jingfei Kong, Martin Dimitrov, Yi Yang 0018, Janaka Liyanage, Lin Cao, Jacob Staples, Mike Mantor, Huiyang Zhou	Accelerating MATLAB Image Processing Toolbox functions on GPUs.	GPGPU	2010	DBLP DOI BibTeX RDF	image processing, GPGPU, CUDA, MATLAB, OpenCL