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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18662 occurrences of 5027 keywords
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Results
Found 21661 publication records. Showing 21661 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
49 | Randolph D. Nelson, Donald F. Towsley, Asser N. Tantawi |
Performance Analysis of Parallel Processing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Banff, Alberta, Canada, May 11-14, 1987, pp. 93-94, 1987, ACM, 0-89791-225-X. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
46 | Edward H. Bensley, Thomas J. Brando, J. C. Fohlin, Myra Jean Prelle, Ann Wollrath |
MITRE's future generation computer architectures program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA/ECOOP Workshop on Object-based Concurrent Programming ![In: Proceedings of the 1988 ACM SIGPLAN Workshop on Object-based Concurrent Programming, OOPSLA/ECOOP Workshop on Object-based Concurrent Programming 1988, San Diego, CA, USA, September 26-27, 1988, pp. 99-101, 1988, ACM, 978-0-89791-304-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
46 | Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal |
Tiled Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 1-33, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
46 | James Laudon, Robert T. Golla, Greg Grohoski |
Throughput-Oriented Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 205-230, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Mattan Erez, William J. Dally |
Stream Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 231-270, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
46 | H. Peter Hofstee |
Heterogeneous Multi-core Processors: The Cell Broadband Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 271-295, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Chuck Moore, Pat Conway |
General-Purpose Multi-core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 173-203, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang |
Challenges in code generation for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 48-64, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
46 | Peter Marwedel |
Code generation for embedded processors: an introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 14-31, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
46 | Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens |
Chess: retargetable code generation for embedded DSP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 85-102, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
43 | Pawel Gepner, David L. Fraser, Michal Filip Kowalik |
Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 7th International Conference, PPAM 2007, Gdansk, Poland, September 9-12, 2007, Revised Selected Papers, pp. 20-28, 2007, Springer, 978-3-540-68105-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors |
43 | Ruby B. Lee |
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 3-14, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
microSIMD, multimedia, microprocessors, computer arithmetic, permutations, processors, digital signal processors, Instruction Set Architecture, fine-grain parallelism, subword parallelism, media processors |
43 | Michael Yang, Ahmed N. Tantawy |
A design methodology for protocol processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTDCS ![In: 5th IEEE Workshop on Future Trends of Distributed Computing Systems (FTDCS 1995), August 28-30, 1995, Chenju, Korea, Proceedings, pp. 376-383, 1995, IEEE Computer Society, 0-8186-7125-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
protocol processors, FCS, Fibre Channel Standard, homogeneous multi-processors, single VLSI chip, VHDL macro libraries, VLSI protocol processors, CVDS, Communication VLSI Design System, protocols, asynchronous transfer mode, ATM, multiprocessing systems, communication protocols |
42 | David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky |
Conjoining soft-core FPGA processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 694-701, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning |
40 | Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park |
Scheduling of conditional branches using SSA form for superscalar/VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 344-351, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA |
39 | Anurag Gupta, Ian F. Akyildiz, Richard Fujimoto |
Performance Analysis of Time Warp With Multiple Homogeneous Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(10), pp. 1013-1027, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
interacting processors, Time Warp protocol, discrete-state, continuous-time Markov chain model, exponential task times, timestamp increments, event message, negligible rollback, unbounded message buffers, homogeneous processors, processed events, rollback probability, uncommitted processed events, Time Warp testbed, performance evaluation, protocols, discrete event simulation, Markov processes, performance measures, multiprocessing systems, shared-memory multiprocessor, parallel simulation, speedup, communication delay, virtual time, state saving, probability mass function, probability distribution function |
39 | Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang |
VLSI design of densely-connected array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 492-497, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets |
38 | Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha |
Optimizing Memory Transactions for Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 145-172, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Li-Shiuan Peh, Stephen W. Keckler, Sriram R. Vangal |
On-Chip Networks for Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 35-71, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Doug Burger, Stephen W. Keckler, Simha Sethumadhavan |
Composable Multicore Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 73-109, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Gurindar S. Sohi, T. N. Vijaykumar |
Speculatively Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multicore Processors and Systems ![In: Multicore Processors and Systems, pp. 111-143, 2009, Springer, 978-1-4419-0262-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Peter Marwedel, Gert Goossens (eds.) |
Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994] ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![Kluwer The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
38 | Henk Corporaal, Jan Hoogerbrugge |
Code generation for transport triggered architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 240-259, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Ulrich Bieker |
Retargetable compilation of self-test programs using constraint logic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 221-239, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus |
Local microcode generation in system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 171-187, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Steven Novack, Alexandru Nicolau, Nikil D. Dutt |
A Unified code generation approach using mutation scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 203-218, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Wolfgang Schenk |
Retargetable code generation for parallel, pipelined processor structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 119-135, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Farhad Mavaddat |
On transforming code generation to a parsing problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 153-170, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Marco Cornero, Filip Thoen, Gert Goossens, Francesco Curatelli |
Software Synthesis for real-time information processing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 260-279, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Paul Vanoostende, Etienne Vanzieleghem, Emmanuel Rousseau, Christian Massy, François Gérard |
Retargetable code generation: key issues for successful introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 32-47, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala |
Flexware: A flexible firmware development environment for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 67-84, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Andreas Fauth |
Beyond tool-specific machine descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 138-152, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Bernhard Wess |
Code generation based on trellis diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 188-202, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
38 | Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji |
An ILP-based approach to code generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Code Generation for Embedded Processors ![In: Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31 - September 2, 1994], pp. 103-118, 1994, Kluwer. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
37 | Pedro Marcuello, Antonio González 0001 |
Clustered speculative multithreaded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999, pp. 365-372, 1999, ACM, 1-58113-164-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
control-flow speculation, data value speculation, simultaneous multithreaded processors, dynamically scheduled processors, data dependance speculation, clustered processors |
37 | Bernard Goossens, Duc Thang Vu |
Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 36-42, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Superpipelined Processors, Architecture, Instruction Level Parallelism, Superscalar Processors, Multithreaded Processors |
37 | Wade Walker, Harvey G. Cragon |
Interrupt Processing in Concurrent Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 28(6), pp. 36-46, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Interrupt processing, imprecise interrupts, concurrent processors, checkpointing, taxonomy, superscalar processors, pipelined processors, out- of-order execution, out-of-order issue, precise interrupts |
36 | Nuno Roma, Leonel Sousa |
In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 170, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
specialized processors, high-order 2-D image moments, computational intensive task, systolic processing, programmable digital processors, configurable hardware logic, real-time system, image analysis, object modelling, floating-point arithmetic, digital signal processing chips, object matching |
36 | Stefan M. Petters |
Bounding the execution time of real-time tasks on modern processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 498-502, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
task execution time, modern processors, embedded hard real time systems, up-to-date processors, fast core frequency, systematic information, real-time systems, computer architecture, complex systems, control flow graph, main memory, flow graphs, optimising compilers, real time tasks, acceleration techniques |
36 | Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu |
Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 207-213, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
edge-weighted directed acyclic graph, bounded number of processors scheduling, arbitrary processor network, scheduling, scheduling, parallel programming, processor scheduling, data flow graphs, task graphs, parallel processors, dataflow graph |
35 | Rainer Leupers, Steven Bashford |
Graph-based code selection techniques for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(4), pp. 794-814, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
code selection, irregular data paths, embedded processors, data-flow graphs, SIMD instructions |
35 | Grzegorz Malewicz, Alexander Russell, Alexander A. Shvartsman |
Distributed cooperation in the absence of communication (brief announcement). ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Nineteenth Annual ACM Symposium on Principles of Distributed Computing, July 16-19, 2000, Portland, Oregon, USA., pp. 339, 2000, ACM, 1-58113-183-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Stephen W. Melvin, Yale N. Patt |
Handling of packet dependencies: a critical issue for highly parallel network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 202-209, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
memory synchronization, packet dependencies, parallel processing, network processors, processor architecture, thread level speculation, multithreaded processors, packet processing |
33 | Fuji Ren |
Dialogue Machine Translation System Using Multiple Translation Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA Workshops ![In: 11th International Workshop on Database and Expert Systems Applications (DEXA'00), 6-8 September 2000, Greenwich, London, UK, pp. 143-154, 2000, IEEE Computer Society, 0-7695-0680-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dialogue machine translation system, multiple translation processors, natural dialogues, irregular expressions, natural conversation, ill-formed sentences, dialogue machine translation, MTP, translation processors, original language analysis, target language generation processing, Robust Parser based Translation Processor, Example Based Translation Processor, Family Modal based Translation Processor, Super Function based Translation Processor, information analysis model, syntactic constraint analysis model, semantic constraint analysis model, robust dialogue translation, language translation |
33 | Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith 0001 |
Trace Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 138-148, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
trace processors, multiscalar processors, next trace prediction, selective reissuing, context-based value prediction, trace cache |
32 | Amirali Baniasadi |
Balancing clustering-induced stalls to improve performance in clustered processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 21-27, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
clustering stalls, clustered processors |
32 | Tzi-cker Chiueh, Prashant Pradhan |
Cache Memory Design for Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 409-418, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Routing Table Lookup, Caching, Network Processors |
32 | John-David Wellman, Edward S. Davidson |
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 110-115, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle |
32 | Santanu Dutta, Wayne H. Wolf, Andrew Wolfe |
VLSI issues in memory-system design for video signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 498-503, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design |
31 | Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas |
Architecture and Evaluation of an Asynchronous Array of Simple Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 243-259, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous |
31 | Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson |
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 50-55, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FMAX distribution, parameter fluctuations, throughput distribution, multi-core, parameter variations |
31 | Dariusz R. Kowalski, Alexander A. Shvartsman |
Writing-all deterministically and optimally using a non-trivial number of asynchronous processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 27-30, 2004, Barcelona, Spain, pp. 311-320, 2004, ACM, 1-58113-840-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
write-all, distributed algorithms, shared memory, asynchrony, work |
31 | Theo Ungerer, Borut Robic, Jurij Silc |
A survey of processors with explicit multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 35(1), pp. 29-63, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interleaved multithreading, simultaneous multithreading, Blocked multithreading |
31 | Byeong Kil Lee, Lizy Kurian John |
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 226-233, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Peter R. Cappello |
Multicore processors as Array Processors: Research Opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 169-172, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Pawel Gepner, David L. Fraser, Michal Filip Kowalik |
Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (1) ![In: Computational Science - ICCS 2008, 8th International Conference, Kraków, Poland, June 23-25, 2008, Proceedings, Part I, pp. 417-426, 2008, Springer, 978-3-540-69383-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
quad-core processors, parallel processing, benchmarks, HPC, multi-core processors |
30 | Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero |
Kilo-Instruction Processors: Overcoming the Memory Wall. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(3), pp. 48-57, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors |
30 | M. Watheq El-Kharashi, Fayez El Guibaly, Kin F. Li |
Adapting Tomasulo's algorithm for bytecode folding based Java processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 29(5), pp. 1-8, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
instruction shelving, java bytecode folding, java stack folding, reservation stations, stack processors, tomasulo's algorithm, java, Java, java virtual machine, dynamic scheduling, java processors, register renaming |
30 | A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans |
TriMedia CPU64 Application Domain and Benchmark Suite. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 580-585, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
TriMedia, multi-media benchmark, design space exploration, embedded processors, VLIW processors, media processing |
30 | Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye |
A technique to determine power-efficient, high-performance superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 324-333, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation |
30 | Isaac Gelado, John H. Kelm, Shane Ryoo, Steven S. Lumetta, Nacho Navarro, Wen-mei W. Hwu |
CUBA: an architecture for efficient CPU/co-processor data communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 299-308, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
co-processors |
30 | Surendra Byna, Yong Chen 0001, Xian-He Sun |
Taxonomy of Data Prefetching for Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 24(3), pp. 405-417, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
taxonomy of prefetching strategies, memory hierarchy, multicore processors, data prefetching |
30 | Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Mendel Rosenblum |
Streamware: programming general-purpose multicore processors using streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 297-307, 2008, ACM, 978-1-59593-958-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
general-purpose multicore processors, programming, streams, runtime system |
30 | Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai |
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 41, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Compilers for low energy, loop buffers, VLIW processors |
30 | Xiaotong Zhuang, Santosh Pande |
Effective thread management on network processors with compiler analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario, Canada, June 14-16, 2006, pp. 72-82, 2006, ACM, 1-59593-362-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
real-time scheduling, compiler optimizations, network processors, CPU scheduling |
30 | Naga K. Govindaraju, Nikunj Raghuvanshi, Dinesh Manocha |
Fast and Approximate Stream Mining of Quantiles and Frequencies Using Graphics Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, Baltimore, Maryland, USA, June 14-16, 2005, pp. 611-622, 2005, ACM, 1-59593-060-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data streams, sorting, sliding windows, memory bandwidth, graphics processors, frequencies, quantiles |
30 | Soraya Ghiasi, Tom W. Keller, Freeman L. Rawson III |
Scheduling for heterogeneous processors in server systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 199-210, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, performance, power, heterogeneous processors |
30 | Oleg Bessonov, Dominique Fougère, Bernard Roux |
Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 7th International Conference, PaCT 2003, Novosibirsk, Russia, September 15-19, 2003, Proceedings, pp. 345-353, 2003, Springer, 3-540-40673-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors |
30 | Madhavi Gopal Valluri, R. Govindarajan |
Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 78-83, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods |
29 | Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang |
A self-timed redundant-binary number to binary number converter for digital arithmetic processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 386-391, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems |
29 | Bhaskar Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis |
The VLSI design and implementation of the array processors of a multilayer vision system architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 125-128, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multilayer vision system architecture, KYDON vision system, multilayered image understanding system, computer vision, parallel processing, VLSI, digital simulation, VLSI design, array processors, timing simulation |
29 | Kunal Agrawal, Charles E. Leiserson, Yuxiong He, Wen-Jing Hsu |
Adaptive work-stealing with parallelism feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 26(3), pp. 7:1-7:32, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
instantaneous parallelism, parallelism feedback, trim analysis, parallel computation, randomized algorithm, job scheduling, multiprogramming, processor allocation, multiprocessing, work-stealing, Adaptive scheduling, work, thread scheduling, adversary, span, space sharing, two-level scheduling |
29 | Bharadwaj Veeravalli, Wong Han Min |
Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(3), pp. 273-288, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
finish times, communication delays, divisible loads, processing times, release times, Linear networks |
29 | Grzegorz Malewicz, Alexander Russell, Alexander A. Shvartsman |
Distributed Cooperation During the Absence of Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 14th International Conference, DISC 2000, Toledo, Spain, October 4-6, 2000, Proceedings, pp. 119-133, 2000, Springer, 3-540-41143-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Ronny Krashinsky, Christopher Batten, Krste Asanovic |
Implementing the scale vector-thread processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 41:1-41:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hybrid C++/Verilog simulation, iterative VLSI design flow, procedural datapath pre-placement, vector-thread processors, multithreaded processors, Vector processors |
29 | Mayan Moudgill, Stamatis Vassiliadis |
Precise Interrupts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 16(1), pp. 58-67, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
interrupt handlers, out-of-order issue processors, instruction level parallel processors, pipelining, exceptions, superscalar processors, traps, precise interrupts |
29 | Tsutomu Hoshino, Toshio Kawai, Tomonori Shirakawa, Jun'ichi Higashino, Akira Yamaoka, Hachidai Ito, Takashi Sato, Kazuo Sawada |
PACS: A Parallel Microprocessor Array for Scientific Calculations ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 1(3), pp. 195-221, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
highly parallel processors, multimicroprocessors, nearest neighbor communication, scientific calculation, distributed systems, parallel algorithms, synchronization, multiprocessors, performance measurement, supercomputer, parallel language, processor architecture, MIMD, array processors, multiprocessing, parallel processors |
29 | Kenneth E. Batcher |
Bit-Serial Parallel Processing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(5), pp. 377-384, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
radar processing, Airborne processors, bit-serial processors, custom VLSI chips, multidimensional access, image processing, parallel processors |
29 | Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi |
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 421-427, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Bogdan S. Chlebus, Dariusz R. Kowalski |
Randomization Helps to Perform Tasks on Processors Prone to Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 13th International Symposium, Bratislava, Slovak Republic, September 27-29, 1999, Proceedings, pp. 284-296, 1999, Springer, 3-540-66531-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Jack L. Rosenfeld |
A case study in programming for parallel-processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 12(12), pp. 645-655, 1969. The full citation details ...](Pics/full.jpeg) |
1969 |
DBLP DOI BibTeX RDF |
Gauss-Seidel, Jacobi, storage interference, simulation, parallel programming, parallelism, multiprocessor, convergence, tasking, multiprogramming, relaxation, parallel-processor, electrical network |
28 | Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero |
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 32(3), pp. 3-10, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Byeong Kil Lee, Lizy Kurian John |
Implications of Programmable General Purpose Processors for Compression/Encryption Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 233-242, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Farinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey |
Processors for Mobile Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 603-608, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Lin Chen 0001 |
Optimal overlap representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 8-14, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimal overlap representations, minimal interval, circular arc overlap representations, minimal interval overlap representation, EREW PRAM processors, common CRCW PRAM, BSR processors, parallel algorithms, computational complexity, computational geometry, optimal algorithms |
28 | David Goodwin, Darin Petkov |
Automatic generation of application specific processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 137-147, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
automatic instruction-set generation, ASIPs, configurable processors, extensible processors |
28 | Jorge E. Carrillo, Paul Chow |
The effect of reconfigurable units in superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 141-150, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
OneChip, superscalar processors, reconfigurable processors |
28 | Sang Jeong Lee, Yuan Wang, Pen-Chung Yew |
Decoupled Value Prediction on Trace Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 231-240, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Wide-issue superscalar processors, Trace processors, Speculative execution, Value prediction |
28 | Joseph A. Fisher |
Customized Instruction-Sets for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 253-257, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
custom processors, mass customization of toolchains, instruction-level parallelism, VLIW, embedded processors |
28 | Pedro Marcuello, Antonio González 0001, Jordi Tubella |
Speculative Multithreaded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 12th international conference on Supercomputing, ICS 1998, Melbourne, Australia, July 13-17, 1998, pp. 77-84, 1998, ACM, 0-89791-998-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
multithreaded processors, data speculation, dynamically scheduled processors, data dependence speculation, control speculation |
28 | Sandeep N. Bhatt, Geppino Pucci, Abhiram G. Ranade, Arnold L. Rosenberg |
Scattering and Gathering Messages in Networks of Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(8), pp. 938-949, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
message scattering, messages gathering, networks of processors, trees of processors, noncolliding paths, queueing mechanisms, scheduling, distributed processing, multiprocessor interconnection networks, spanning trees, buffering |
28 | Ashok K. Agrawala, Edward G. Coffman Jr., M. R. Garey, Satish K. Tripathi |
A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniform Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(4), pp. 351-356, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
uniform processor systems, Consider a set of processors P1, ..., Pm differing only in speed and a set of jobs with exponentially distributed execution times, The rate parameter for the ith processor is given by ?i, 1 =i = m, where we assume the processors are ordered so that ?1 = ?2 = ... = ?m. The problem is to sequence the jobs nonpreemptively so as to minimize expected total flow time (sum of finishing times). We defin, Mean flow time minimization, stochastic optimization, stochastic scheduling, routing problems |
28 | Chris R. Jesshope |
Some Results Concerning Data Routing in Array Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(7), pp. 659-662, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
data rotation, ICL distributed array processor (DAP), k-dimensional cyclic networks, Array processors, parallel processors, data routing |
27 | Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero |
A first glance at Kilo-instruction based multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 212-221, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors |
27 | Emile Haddad |
Optimal load distribution for asynchronously scheduled homogeneous multiprocessor and distributed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 183-184, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimal load distribution, asynchronously scheduled homogeneous multiprocessor systems, interacting tasks, identical processors, job completion time minimization, execution initiation times, earliest availability, load parameters, optimal load allocation, uneven module distribution, distributed systems, resource allocation, distributed processing, multiprocessing systems, processor scheduling, minimisation, system parameters, processor assignment |
27 | Ning Weng, Tilman Wolf |
Analytic modeling of network processors for parallel workload mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(3), pp. 18:1-18:29, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
embedded systems, network processors, multiprocessor scheduling, Application profiling |
27 | Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha |
Throughput optimal task allocation under thermal constraints for multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 776-781, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimal throughput, task allocation, thermal management, multi-core processors, thread migration |
27 | Garo Bournoutian, Alex Orailoglu |
Miss reduction in embedded processors through dynamic, power-friendly cache design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 304-309, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dynamic associativity, multi-core, embedded processors, data cache |
27 | Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao |
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 197-200, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
subgraph covering, VLIW, ASIPs, extensible processors |
27 | Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju |
A Throughput-Driven Task Creation and Mapping for Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 227-241, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Intel IXP, Task Creation and Mapping, Throughput, Network Processors, Dataflow Programming |
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