Search results for "single-ended"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram	Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory.	DATE	2007	DBLP DOI BibTeX RDF
58	Carine Neus, Wim Foubert, Leo Van Biesen	Loop Identification and Capacity Estimation of Digital Subscriber Lines with Single Ended Line Testing.	AccessNets	2008	DBLP DOI BibTeX RDF	Digital Subscriber Line (DSL), Single Ended Line Testing (SELT), transfer function estimation, loop qualification, channel capacity
58	Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi	Pseudoduplication - An ACOB Technique for Single-Ended Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	pseudoduplication, ACOB, analog circuit observer block, single-ended switched capacitor filter, data duplication code, simulation, fault detection, layout, design for test, switched capacitor filters
57	Tiago H. Falk, Wai-Yip Chan	Single-Ended Speech Quality Measurement Using Machine Learning Methods.	IEEE Trans. Speech Audio Process.	2006	DBLP DOI BibTeX RDF
51	Abhijit Sil, Eswar Prasad Kolli, Soumik Ghosh, Magdy A. Bayoumi	High speed single-ended pseudo differential current sense amplifier for SRAM cell.	ISCAS	2008	DBLP DOI BibTeX RDF
49	Deepak C. Sekar	Clock trees: differential or single ended?.	ISQED	2005	DBLP DOI BibTeX RDF
42	Fabio Lacerda, Stefano Pietri, Alfredo Olmos	A differential switched-capacitor amplifier with programmable gain and output offset voltage.	SBCCI	2006	DBLP DOI BibTeX RDF	differential to single ended, switched capacitor stage, analog integrated circuits
40	Haikun Zhu, Rui Shi 0003, Chung-Kuan Cheng, Hongyu Chen	Approaching Speed-of-light Distortionless Communication for On-chip Interconnect.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.10 micron, speed-of-light distortionless communication, surfliner on-chip distortionless transmission line scheme, shunt resistors, shunt conductance, single-ended microstrip line, 10 Gbit/s, on-chip interconnect
40	T. Haulin	Built-in parametric test for controlled impedance I/Os.	VTS	1997	DBLP DOI BibTeX RDF	controlled impedance I/Os, built-in parametric test, full DC parametrics, full speed AC tests, lower cost ATE, differential signal I/Os, single-ended signal I/Os, short circuit proof drivers, B9 test method, bidirectional I/O, differential receivers, differential transmitters, diagnostic tests, narrow pulse test, contact test, high speed test logic, built-in self test, functional test, boundary scan, static tests
40	Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De	Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Shu-Hui Tu, J. Neil Ross, Chun-Ming Chang	Analytical synthesis of current-mode even-Nth-order single-ended-input OTA and equal-capacitor elliptic filter structure with the minimum components.	ISCAS	2006	DBLP DOI BibTeX RDF
39	Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici	Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density.	IJCNN	2006	DBLP DOI BibTeX RDF
39	Shu-Hui Tu, J. Neil Ross	Low sensitivity single-ended-input OTA and grounded capacitor elliptic filter structure with the minimum components.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
39	Angelo Nagari, Germano Nicollini	A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs.	DATE	2004	DBLP DOI BibTeX RDF
36	Xingyuan Tong, Jinwu Wu, Dong Chen	Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
36	Yuping Toh, John A. McNeill	Single-ended to differential converter for multiple-stage single-ended ring oscillators.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
36	Gianluigi Boarin, Vittorio Colonna, Gabriele Gandolfi, Fabrizio Stefani, Andrea Baschirotto	90dB-DR 3.3V CMOS single-ended-to-fully differential and fully differential-to-single-ended amplifiers for audio applications.	Int. J. Circuit Theory Appl.	2003	DBLP DOI BibTeX RDF
31	S. Chrisben Gladson, P. Siva Prasad, V. Thenmozhi, M. Bhaskar 0001	A 4-6 GHz Single-Ended to Differential-Ended Low-Noise Amplifier for IEEE 802.11ax Wireless Applications with Inherent Complementary Distortion Cancellation.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
31	Yun-gi Kwak, Dae-ho Heo, Byoung-Hee Lee, Feel-soon Kang	Failure-rate Comparison of Single-ended and Double-ended Forward Converter by means of Fault-tree Analysis.	ISIE	2020	DBLP DOI BibTeX RDF
31	Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki	Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
31	Dustin Dunwell, Brian Frank	24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18µm CMOS.	CCECE	2006	DBLP DOI BibTeX RDF
30	Shan Chen, Xingyuan Tong, Naiqiong Cai, Yintang Yang	A 12-bit 1MS/s Non-calibrating SAR A/D Converter Based on 90nm CMOS Process.	MVHI	2010	DBLP DOI BibTeX RDF	single-ended, non-calibrating, finger capacitors, small area, SAR, analog-to-digital converter
30	Niraj K. Jha	Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers
30	Tajeshwar Singh, Trond Ytterdal	A single-ended to differential capacitive sensor interface circuit designed in CMOS technology.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
28	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
28	Bastien Giraud, Amara Amara	A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
28	Richard F. Hobson	A New Single-Ended SRAM Cell With Write-Assist.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
28	Gülin Tulunay, Sina Balkir	Design automation of single-ended LNAs using symbolic analysis.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
28	Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang 0001, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De	Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
28	Caroline Papaix, Jean Michel Daga	A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories.	MTDT	2002	DBLP DOI BibTeX RDF
28	Mehdi M. Mechaik	An Evaluation of Single-Ended and Differential Impedance in PCBs.	ISQED	2001	DBLP DOI BibTeX RDF
22	Wei-Xiang You, Cheng-Yin Wang, Yih Wang, Tsung-Yung Jonathan Chang, Szuya Sandy Liao	Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
22	Yana Zheng, Weimin Wang 0008, Yongle Wu, Weijuan Chen	A Single-Layer Planar Wideband Filtering Single-Ended-to-Balanced Crossover With Excellent Common-Mode Suppression.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
22	Calvin Yoji Lee, Un-Ku Moon	A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS.	ISSCC	2022	DBLP DOI BibTeX RDF
22	Xiong Chen, Tao Yang, Pei-Ling Chi	Novel Single-Ended-to-Balanced Filter With Reconfigurable Working Modes, Frequency, Bandwidth, and Single/Dual-Band Operations.	IEEE Access	2021	DBLP DOI BibTeX RDF
22	Son Thai Le, Karsten Schuh	465 Gbps Single Side Band Direct Detection Transmission over 40 km of SSMF using a Single-ended Photodiode.	OFC	2021	DBLP BibTeX RDF
22	M. Sezer Erkilinc, Zhixin Liu, Thomas Gerard, Robert I. Killey, Polina Bayvel, Domaniç Lavery	Bidirectional Symmetric 25G Coherent ONU Using a Single Laser, Single-Ended PIN and a 2-bit ADC.	ECOC	2018	DBLP DOI BibTeX RDF
22	Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park	A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
22	Linga Reddy Cenkeramaddi, Tajeshwar Singh, Trond Ytterdal	Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	CMUT-CMOS, analog front-end for CMUTs, charge sampling, sampling, CSA
22	Haigang Feng, Qiong Wu 0013, Xiaokang Guan, Rouying Zhan, Albert Z. Wang, Liwu Yang	A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35µm SiGe BiCMOS.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
22	Amlan Ghosh, Bevin G. Perumana, Ashudeb Dutta, Padmanava Sen, Yogesh Kumar, Vipul Garg, T. K. Bhattacharyya, Nirmal B. Chakrabarti	Design and Implementation of 935 MHz FM Transceiver for Radio Telemetry and 2.45 GHz Direct AQPSK Transmitter in CMOS.	VLSI Design	2004	DBLP DOI BibTeX RDF
21	Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim	Yield-driven near-threshold SRAM design.	ICCAD	2007	DBLP DOI BibTeX RDF
21	Leila Shepherd, Pantelis Georgiou, Chris Toumazou	A novel voltage-clamped CMOS ISFET sensor interface.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Uroschanit Yodprasit, Christian C. Enz	On an implementation of differential and quadrature Colpitts injection-locked frequency dividers.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Guochi Huang, Tae-Sung Kim, Byung-Sung Kim, Mingyan Yu, Yizheng Ye	Post linearization of CMOS LNA using double cascade FETs.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni	Balanced 3-phase analog signal processing for radio communications.	ISCAS	2006	DBLP DOI BibTeX RDF
21	K. Kiyoyama, Yoshinobu Tanaka, Michihisa Onoda	A low current consumption delta-sigma modulator for body-implanted chip.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
21	Susan Luschas, Hae-Seung Lee	Output impedance requirements for DACs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
19	Ivan Chee Hong Lai, Yuki Kambayashi, Minoru Fujishima	50GHz Double-Balanced Up-Conversion Mixer Using CMOS 90nm Process.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Chia-Jung Chang, Ke-Horng Chen	Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter Compensation.	IWSOC	2005	DBLP DOI BibTeX RDF
19	Kartik Mohanram, Scott Rixner	Context-Independent Codes for Off-Chip Interconnects.	PACS	2004	DBLP DOI BibTeX RDF
18	Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim	A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
18	Tao Wang, Jieyang Li, Di Hua, Liangbo Lei, Peng Cao, Peng Xu, Jiawei Xu 0001, Zhiliang Hong	A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DLL-Based Three-Segment Hybrid DTC in 28 nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
18	Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Jisu Yook, Jihoon Lee, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sungsik Park, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim, Sung-Ung Kwak	A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
18	Jiawei He, Yaru Sheng, Bin Li 0028, Ye Li, Bohao Zhou	A Novel Segmented-COV-Based Single-Ended Line Protection Algorithm for the Multiterminal MMC-HVDC System With No Boundary Reactor.	IEEE Trans. Ind. Informatics	2024	DBLP DOI BibTeX RDF
18	Xiaofei Wang, Jing Jin 0005, Xiaoming Liu 0008, Hui Wang 0023, Huzhi Tang, Chao Yang, Yuekang Guo, Tingting Mo, Jianjun Zhou	A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
18	Myungguk Lee, Jaeik Cho, Junung Choi, Won Joon Choi, Jiyun Lee, Iksu Jang, Changjae Moon, Gain Kim, Byungsub Kim	Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
18	Taeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae-Kang Jung, Jaeduk Han	A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
18	Haotian Lan, Yuhua Liang	A 93.4-dB SNDR single-ended SAR ADC with a hybrid R-C DAC.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
18	Liping Zhong, Hongzhi Wu, Yangyi Zhang, Xuxu Cheng, Weitao Wu, Catherine Wang, Xiongshi Luo, Taiyang Fan, Dongfan Xu, Quan Pan 0002	7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Xiongshi Luo, Xuewei You, Zhenghao Li, Hamed Mosalam, Dongfan Xu, Taiyang Fan, Hongchang Qiao, Wentao Zhou, Hongzhi Wu, Liping Zhong, Patrick Yin Chiang, Quan Pan 0002	7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Weitao Wu, Hongzhi Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Dongfan Xu, Catherine Wang, Zhenghao Li, Quan Pan 0002	13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Kihwan Seong, Wooseuk Oh, Hyunwoo Lee, Gyeom-Je Bae, Youngseob Suh, Hyemun Lee, Juyoung Kim, Eunsu Kim, Yeongeon Kang, Gunhu Mo, Youjin Lee, Mingyeong Kim, Seongno Lee, Donguk Park, Byoung-Joo Yoo, Hyo-Gyuem Rhew, Jongshin Shin	13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Junyeol An, Seung Hun Choi, Si-Woo Kim, Jae-Youl Lee, Hyung-Min Lee, Yoon-Kyung Choi	26.3 Noise Immunity in Capacitive Sensing: Single-Ended AFE Design with Common-Current Subtraction for Mutual- and Self-Capacitance Sensing in 390pF Load.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Sanchari Das, Bibhu Datta Sahoo 0002	Closed Form Expression of Input Matching of a Wideband Single-Ended to Differential LNA.	VLSID	2024	DBLP DOI BibTeX RDF
18	Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim	A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Sumit Pratap Singh, Timo Rahkonen, Marko E. Leinonen, Aarno Pärssinen	Design Aspects of Single-Ended and Differential SiGe Low-Noise Amplifiers Operating Above fmax/2in Sub-THz/THz Frequencies.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	David Joseph Munzer, Naga Sasikanth Mannem, Jeongseok Lee, Hua Wang 0006	Broadband mm-Wave Current/Voltage Sensing-Based VSWR-Resilient True Power/Impedance Sensor Supporting Single-Ended Antenna Interfaces.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Qian Liu, Li Du, Yuan Du	A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim	A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Yong-Un Jeong, Joo-Hyung Chae, Suhwan Kim	A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim	A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Miguel Jiménez-Aparicio, Felipe Wilches-Bernal, Matthew J. Reno	Local, Single-Ended, Traveling-Wave Fault Location on Distribution Systems Using Frequency and Time-Domain Data.	IEEE Access	2023	DBLP DOI BibTeX RDF
18	Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose	A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process.	IET Circuits Devices Syst.	2023	DBLP DOI BibTeX RDF
18	Yong-Un Jeong, Sungphil Choi, Suhwan Kim, Joo-Hyung Chae	Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
18	Erfan Abbasian, Sobhan Sofimowloodi	Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
18	Kevin Pelzers, Mariska van der Struijk, Pieter Harpe	A 0.0022 mm² 10 bit 20 MS/s SAR ADC With Passive Single-Ended-to-Differential-Converter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
18	Youming Zhang, Xusheng Tang, Zhennan Wei, Yunqi Cao, Xiaoyu Wang, Fengyi Huang	On the Design of Broadband Truly Balanced Inductor-Less Differential-to-Single-Ended Converter in CMOS Friendly to Wire-Bond Package.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Li Yang 0011, Roberto Gómez-García	High-Order Quasi-Elliptic-Type Single-Ended and Balanced Wideband Bandpass Filters Using Microstrip-to-Microstrip Vertical Transitions.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Hyochang Kim, Hyeongmin Seo, Hyuntae Kim, Changsik Yoo, Jaeduk Han	A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Xi-Bei Zhao, Feng Wei 0003, Xinxin Liu	Balanced-to-Single-Ended Filtering Power Divider Using Multilayer Mixed-Mode Magic-T.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Shan Shen, Hao Xu, Yongliang Zhou, Wenjian Yu	A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim	A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Wei-Shen Liu, Le Xu, Feng Wei 0003, Tao Feng, Xi-Bei Zhao, Yu-Chen Xue, Jia Xin Wang, Zhao Li	Miniaturized Single-Ended-to-Balanced Filtering Power Divider With High Selectivity Based on Tri-Mode Resonator.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Alireza Jahangiri, Ali Abdolalizadeh, Ahmad Ghaderi Shamim	A new single ended primary inductor converter with high voltage gain, low voltage stress and continuous input current.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
18	Zhong Zhang 0002, Ming Cheng, Yihu Yu, Qi Yu 0002, Kejun Wu, Ning Ning 0002	A 0.053 mm2 10-bit 10-ks/s 40-nW SAR ADC with pseudo single ended switching procedure for bio-related applications.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
18	Bhawna Rawat, Poornima Mittal	A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
18	Yiqi Xing, Yu Liu, Dayou Lu, Xinchen Zou, Xuming He	A Physics-Informed Data-Driven Fault Location Method for Transmission Lines Using Single-Ended Measurements with Field Data Validation.	CoRR	2023	DBLP DOI BibTeX RDF
18	Rui Ma, Haichang Sun, Liang Qin 0001	An Emergency Coordinated Control Strategy to Improve the Transient Stability of a Single-Ended Distribution Network with Flexible Interconnection Channel Blocking.	Sensors	2023	DBLP DOI BibTeX RDF
18	Willem Mazzotti Mazzotti Pallard, Alberto Lazzarotto, José Acuña, Björn Palm	Calibration and Uncertainty Quantification for Single-Ended Raman-Based Distributed Temperature Sensing: Case Study in a 800 m Deep Coaxial Borehole Heat Exchanger.	Sensors	2023	DBLP DOI BibTeX RDF
18	Guangyang Zhou, Shaahin Filizadeh, Zesan Liu, Hongmin Meng, Xueying Zhuge, Shu Huang, Zhenan Xu	Single-Ended Fault Detection Scheme Using ANN for MTDC Systems.	PCCNT	2023	DBLP DOI BibTeX RDF
18	Hung-Wen Lin, Chung-Yen Lin, Tzu-Yu Teng, Chi-Ting Ke	A SSN reduction technique for single-ended I/O, parallel link system.	ICCE-Taiwan	2023	DBLP DOI BibTeX RDF
18	V. H. Arzate Palma, F. Sandoval-Ibarra	Slew-rate Comparison of single-ended amplifiers-the Folded Cascode and the Recycling Folded Cascode.	CCE	2023	DBLP DOI BibTeX RDF
18	Cristina Maurette-Blasini, Rainer Weber, Sandrine Wagner, Dirk Schwantuschke, Sébastien Chartier, Rüdiger Quay	Single-Ended Resistive Down-Converter MMICs in InGaAs mHEMT and GaN-HEMT Technologies for D-Band (110-170 GHz) Applications.	BCICTS	2023	DBLP DOI BibTeX RDF
18	Scott D. Huss, Chris Moscone, Mark Summers, James Vandersand, Kelvin McCollough, Randall Smith	Short to Medium-Reach Wireline Transceivers Using Single-Ended Signaling, Clock Forwarding, and Spatial Encoding for Die-to-Die Applications.	CICC	2023	DBLP DOI BibTeX RDF
18	Ying Wei, Yi Chieh Huang, Haiming Tang, Nithya Sankaran, Ish Chadha, Dai Dai, Olakanmi Oluwole, Vishnu Balan, Edward Lee	NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin Single-ended Signaling.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong	A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim	A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.	ISSCC	2023	DBLP DOI BibTeX RDF