Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
62 | Ho Fai Ko, Nicola Nicolici |
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(4), pp. 393-403, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Skewed-load, Scan division, At-speed test, Low-power test |
58 | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
On Common-Mode Skewed-Load and Broadside Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 151-156, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Jacob Savir, Srinivas Patil |
Scan-based transition test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8), pp. 1232-1241, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Zhen Chen, Boxue Yin, Dong Xiang |
Conflict driven scan chain configuration for high transition fault coverage and low test power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 666-671, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Irith Pomeranz, Sudhakar M. Reddy |
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 398-403, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Irith Pomeranz, Sudhakar M. Reddy |
Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 419-427, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Ho Fai Ko, Nicola Nicolici |
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 454-459, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
High-level DFT, Delay-fault testing |
28 | Seongmoon Wang, Wenlong Wei |
Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, pp. 125-130, 2008, IEEE Computer Society, 978-0-7695-3150-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Transition delay fault, broadside, skewed-load, enhanced scan |
28 | Jacob Savir |
Delay Test Generation: A Hardware Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(3), pp. 245-254, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
transition test, skewed-load delay test, shift dependency, cellular automata, linear feedback shift register, delay test, pseudo-random test |
28 | Jacob Savir |
Generator choices for delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 214-221, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test |
27 | Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar |
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1296-1301, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Jacob Savir, Srinivas Patil |
Broad-side delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8), pp. 1057-1064, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz, Xijiang Lin |
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(2), pp. 423-433, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12), pp. 5238-5246, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Multicycle Broadside and Skewed-Load Tests for Test Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1), pp. 262-266, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Padding of Multicycle Broadside and Skewed-Load Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(11), pp. 2587-2595, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Skewed-Load Tests for Transition and Stuck-at Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10), pp. 1969-1973, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Boundary-Functional Broadside and Skewed-Load Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(1), pp. 7:1-7:20, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Combined input test data volume reduction for mixed broadside and skewed-load test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 10(3), pp. 138-145, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(3), pp. 593-597, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4), pp. 638-642, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Low-power skewed-load tests based on functional broadside tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 19(2), pp. 18:1-18:18, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Roland Dobai, Marcel Baláz |
Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Informatics ![In: Comput. Informatics 32(2), pp. 251-272, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
22 | Irith Pomeranz |
On Test Compaction of Broadside and Skewed-Load Test Cubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(9), pp. 1705-1714, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Broadside and Skewed-Load Tests Under Primary Input Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(4), pp. 776-780, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Static test compaction for mixed broadside and skewed-load transition fault test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 7(1), pp. 21-28, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Roland Dobai, Marcel Baláz |
SAT-based generation of compressed skewed-load tests for transition delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(2), pp. 196-205, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
On the Computation of Common Test Data for Broadside and Skewed-Load Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 61(4), pp. 578-583, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Roland Dobai, Marcel Baláz |
Genetic method for compressed skewed-load delay test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012, pp. 242-247, 2012, IEEE, 978-1-4673-1187-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, pp. 37-42, 2012, IEEE Computer Society, 978-1-4673-3043-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue |
Hybrid Test Application in Partial Skewed-Load Scan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12), pp. 2571-2578, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Roland Dobai, Marcel Baláz |
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pp. 191-196, 2011, IEEE Computer Society, 978-1-4577-1048-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 84-89, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz |
Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 17th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2011, Pasadena, CA, USA, December 12-14, 2011, pp. 45-52, 2011, IEEE Computer Society, 978-1-4577-2005-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Irith Pomeranz, Sudhakar M. Reddy |
Functional and partially-functional skewed-load tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 505-510, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Sying-Jyan Wang, Kuo-Lin Peng, Katherine Shu-Min Li |
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 169-174, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Ho Fai Ko, Nicola Nicolici |
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, pp. 237-242, 2006, IEEE, 978-0-7803-9707-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Srinivas Patil, Jacob Savir |
Skewed-Load Transition Test: Part 2, Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 714-722, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
22 | Jacob Savir |
Skewed-Load Transition Test: Part 1, Calculus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 705-713, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Jun Gao, Peter Steenkiste |
Design and evaluation of a distributed scalable content discovery system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 22(1), pp. 54-66, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Michele Colajanni, Philip S. Yu, Daniel M. Dias |
Analysis of Task Assignment Policies in Scalable Distributed Web-Server Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(6), pp. 585-600, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Internet, Distributed systems, WWW, load balancing, performance analysis, scheduling algorithms, Web servers |
12 | Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy |
Scan BIST Targeting Transition Faults Using a Markov Source. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 497-502, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|