Search results for "slew-rate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
123	Yuantao Peng, Xun Liu	Low-power repeater insertion with both delay and slew rate constraints.	DAC	2006	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion, slew rate
97	Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock	A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	opamp, feedback, CMOS, compensation, operational amplifier, slew rate
88	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A simple metric for slew rate of RC circuits based on two circuit moments.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
83	Andre Vilas Boas, Eduardo Ribeiro, Alfredo Olmos, Ricardo Maltione	Self-adaptable slew rate control output buffer for embedded microcontroller port applications.	SBCCI	2008	DBLP DOI BibTeX RDF	I/O pad, slew rate control, self-adaptable, microcontroller, output buffer
78	Bjorn Dahlberg	Increasing Test Accuracy by Varying Driver Slew Rate.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
76	Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF
66	Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu	High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.	ISCAS	2006	DBLP DOI BibTeX RDF
66	Hoi Lee, Philip K. T. Mok	A CMOS current-mirror amplifier with compact slew rate enhancement circuit for large capacitive load applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
63	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Chin Ngai Sze	Fast Algorithms for Slew-Constrained Minimum Cost Buffering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
62	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Simple metrics for slew rate of RC circuits based on two circuit moments.	DAC	2003	DBLP DOI BibTeX RDF
55	Jing Zhang	A Low-Power and High Slew-rate CMOS Voltage Follower.	MVHI	2010	DBLP DOI BibTeX RDF	CSTN-LCD, voltage-follower, high slew-rate, low-power
52	H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler	A rail to rail, slew-boosted pre-charge buffer.	ISCAS	2006	DBLP DOI BibTeX RDF
52	Young-Ho Kwak, Inhwa Jung, Chulwoo Kim	A slew-rate controlled output driver with one-cycle tuning time.	ASP-DAC	2008	DBLP DOI BibTeX RDF
52	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	High slew rate two stage A/AB and AB/AB op-amps with phase lead compensation at output node and local common mode feedback.	ISCAS	2008	DBLP DOI BibTeX RDF
52	Amorn Jiraseree-amornkun, Apisak Worapishet, Eric A. M. Klumperink, Bram Nauta, Wanlop Surakampontorn	Slew rate induced distortion in switched-resistor integrators.	ISCAS	2006	DBLP DOI BibTeX RDF
50	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Cliff C. N. Sze	Fast algorithms for slew constrained minimum cost buffering.	DAC	2006	DBLP DOI BibTeX RDF	slew constraint, physical design, buffer insertion
48	Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee	A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond.	ISSCC	2023	DBLP DOI BibTeX RDF
45	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
45	Pradip Mandal, V. Visvanathan	Design of high performance two stage CMOS cascode op-amps with stable biasing.	VLSI Design	1996	DBLP DOI BibTeX RDF	two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability
38	Tongyu Song, Shouli Yan	A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Joongho Choi, Jinup Lim, Cheng-Chew Lim	A low-voltage operational amplifier with high slew-rate for sigma-delta modulators.	ISCAS	2006	DBLP DOI BibTeX RDF
38	Sushmita Baswa, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	A novel family of low-voltage very low power super class AB OTAs with significantly enhanced slew rate and bandwidth.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
38	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio Jesús Torralba Silgado, Carlos Nieva	A new class AB differential input stage for implementation of low-voltage high slew rate op amps and linear transconductors.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
38	Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis	A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection.	DATE	1999	DBLP DOI BibTeX RDF
38	Gustavo E. Téllez, Majid Sarrafzadeh	Minimal buffer insertion in clock trees with skew and slew rate constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
31	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
29	Dae Hyun Kwon, Minkyu Kim 0003, Sung-Geun Kim, Woo-Young Choi	A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
29	Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang	32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation.	ICICDT	2014	DBLP DOI BibTeX RDF
28	Michael Lustig, Seung-Jean Kim, John M. Pauly	A Fast Method for Designing Time-Optimal Gradient Waveforms for Arbitrary k-Space Trajectories.	IEEE Trans. Medical Imaging	2008	DBLP DOI BibTeX RDF
28	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.	VLSI Design	2008	DBLP DOI BibTeX RDF
28	Zushu Yan, Qiang Bian, Yuanfu Zhao	Freqency Compensation for Multistage Amplifiers using Active-Feedback Current Buffers.	CCECE	2006	DBLP DOI BibTeX RDF
28	Salvatore Pennisi	High-performance CMOS current feedback operational amplifier.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
28	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driver output model for on-chip RLC transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
28	Shanta Thoutam, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	Power efficient fully differential low-voltage two stage class AB/AB op-amp architectures.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
28	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driving point model for on-chip RLC interconnects.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
26	Janet Meiling Wang, Jun Li 0066, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla	Modeling the Driver Load in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout	A multi-port current source model for multiple-input switching effects in CMOS library cells.	DAC	2006	DBLP DOI BibTeX RDF	MCSM, cell library characterization, multiple input switching, timing analysis, current source model, cell model
26	Nathan Kalyanasundharam, Nital Patwa	Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor.	ICCD	1999	DBLP DOI BibTeX RDF	multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance
24	Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka	An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
24	Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang	A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.	Integr.	2023	DBLP DOI BibTeX RDF
24	Sougata Ghosh	Low-Voltage Super Class-AB Bulk-Driven Single-Stage Subthreshold OTA with Very High DC Gain, Slew Rate, and High Driving Capability.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
24	Xiaoyan Gui, Renjie Tang, Kai Li, Kanan Wang, Dan Li 0011, Quan Pan 0002, Li Geng	A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique.	IET Circuits Devices Syst.	2023	DBLP DOI BibTeX RDF
24	Bhawna Aggarwal, Vaishali Sharma	A New Improved Current Splitter OTA with Higher Transconductance and Slew Rate.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
24	Francesco Gagliardi 0002, Alessandro Catania, Massimo Piotto, Paolo Bruschi, Michele Dei	A Novel High-Performance Parallel-Type Slew-Rate Enhancer for LCD-Driving Applications.	PRIME	2023	DBLP DOI BibTeX RDF
24	V. H. Arzate Palma, F. Sandoval-Ibarra	Slew-rate Comparison of single-ended amplifiers-the Folded Cascode and the Recycling Folded Cascode.	CCE	2023	DBLP DOI BibTeX RDF
24	Seunghwa Shin, Gyeong-Gu Kang, Gyu-Wan Lim, Hyun-Sik Kim	A Mobile OLED Source-Driver IC featuring Ultra-Compact 3-Stage-Cascaded 10-Bit DAC and 42V/μs-Slew-Rate True-DC-Interpolative Super-OTA Buffer.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
24	Yarallah Koolivand, Yasser Rezayean, Milad Zamani, Meysam Akbari, Omid Shoaei, Kea-Tiong Tang, Farshad Moradi	A 69MHz-Bandwidth 40V/μs-Slew-rate 3nV/√Hz-Noises 4.5μV-Offset Chopper Operational Amplifier.	CICC	2023	DBLP DOI BibTeX RDF
24	Wangchen Fan, Zhongyuan Fang, Yongjia Lil, Minggang Chen, Weifeng Sun	A Transient-Enhanced Capacitor-Less LDO With 30-MHz Bandwidth and High Slew Rate.	APCCAS	2023	DBLP DOI BibTeX RDF
24	Mihika Mahendra, Shweta Kumari, Maneesha Gupta	Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application.	Integr.	2022	DBLP DOI BibTeX RDF
24	Cristian Raducan, Marius Neag	Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
24	Emad Ebrahimi, Amin Roozbakhsh, Mohammadreza Rasekhi	A new slew rate enhancement technique for operational transconductance amplifiers.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
24	Caffey Jindal, Rishikesh Pandey	High Slew-Rate and Very-Low Output Resistance Class-AB Flipped Voltage Follower Cell for Low-Voltage Low-Power Analog Circuits.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
24	Mehdi Moradian Boanloo, Mohammad Yavari	A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
24	Ionut-Constantin Guran, Adriana Florescu, Lucian Andrei Perisoara	Optimized Slew Rate Control Technique for Automotive Low-Dropout Linear Voltage Regulators Simulation Models.	ECAI	2022	DBLP DOI BibTeX RDF
24	Karthik Debbadi, Yoann Pascal, Marco Liserre	dv/dt filter design incorporating machine impedance and voltage slew rate for WBG-based electric drives.	IECON	2022	DBLP DOI BibTeX RDF
24	Hyun-Ki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, Hong-Hyun Bae, Hyun-Sik Kim	A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
24	Tingxu Hu, Mo Huang, Yan Lu 0002, Rui Paulo Martins	A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD.	ISSCC	2022	DBLP DOI BibTeX RDF
24	Si Yuan Sim, Junmin Jiang, Cheng Huang 0004	A Half-Bridge GaN Driver with Real-Time Digital Calibration for VGS Ringing Regulation and Slew-Rate Optimization in 180nm BCD.	ISCAS	2022	DBLP DOI BibTeX RDF
24	Jinhen Lee, Jianming Zhao, Yuan Gao 0011	A Nanowatt Comparator with Feedforward Slew Rate Enhancement and PVT-Insensitive Bias for Always-on MEMS Switch Wake-up Sensor.	ISCAS	2022	DBLP DOI BibTeX RDF
24	Young-Ju Oh, Hyo-Jin Park 0002, Joo-Mi Cho, Hyeon-Ji Choi, Su-Min Park, Chan-Ho Lee, Esun Baik, Chan-Kyu Lee, Ho-Chan Ahn, Sung-Wan Hong	A High Slew-rate Wide-range Capacitive Load Driving Buffer Amplifier with Correlated Dual Positive Feedback Loops.	ISOCC	2022	DBLP DOI BibTeX RDF
24	Tianxian Wu, Yuting Zhang, Yanhan Zeng	A 0.3-μA Quiescent Current Output Capacitor-Less LDO with Dynamic Slew Rate Enhance Buffer.	APCCAS	2022	DBLP DOI BibTeX RDF
24	Eric J. Wyers	Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization.	APCCAS	2022	DBLP DOI BibTeX RDF
24	Yu-Yung Kao, Sheng-Hsi Hung, Hsuan-Yu Chen, Jia-Jyun Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai	Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch With Temperature-Compensated Fast Turn-on Technique for Achieving Switching Frequency of 50 MHz and Slew Rate of 118.3 V/Ns.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
24	Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee	2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
24	Marino De Jesus Guzman, Nima Maghari	Slew Rate in Self-Biased Ring Amplifiers.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
24	Mihika Mahendra, Shweta Kumari, Maneesha Gupta, Ankur Sangal	Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
24	Fang-Ming Yu, Kun-Cheng Lee, Ko-Wen Jwo, Rong-Seng Chang, Jun-Yi Lin	Low Distortion of Noise Filter Realization with 6.34 V/μs Fast Slew Rate and 120 mVp-p Output Noise Signal.	Sensors	2021	DBLP DOI BibTeX RDF
24	Manjunath Kareppagoudr, Emanuel Caceres, Gabor C. Temes	Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion.	MWSCAS	2021	DBLP DOI BibTeX RDF
24	Ree Jin Joe, Dong Gyu Kim, Kang-Yoon Lee	Increasing Slew rate of Charge pump by adopting Negative Feedback.	ICEIC	2021	DBLP DOI BibTeX RDF
24	Ziyu Xia, Jason T. Stauth	A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating 0.6V/μs Input Slew Rate During Startup.	ISSCC	2021	DBLP DOI BibTeX RDF
24	Joo-Mi Cho, Hyo-Jin Park 0002, Sung-Wan Hong	A 0.93-μW Single-Stage Rail-to-Rail Class AB Buffer Amplifier Improving DC gain and Slew-Rate with Different-Ratio Current-Mirrors and Positive-Feedback Loops.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
24	Gyeong-Gu Kang, Seok-Tae Koh, Woojin Jang, Jiho Lee, Seongjoo Lee, Ohjo Kwon, Keumdong Jung, Hyun-Sik Kim	A 12-Bit Mobile OLED/μLED Display Driver IC with Cascaded Loading-Free Capacitive Interpolation DAC and 6.24V/μs-Slew-Rate Buffer Amplifier.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
24	Weifu Chen, Mingyi Chen, Yuzhi Hao, Liang Qi, Jian Zhao 0004	A 1-μA-Quiescent-Current Capacitor-Less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit.	ISCAS	2021	DBLP DOI BibTeX RDF
24	Gianluca Giustolisi, Gaetano Palumbo	Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints.	ISCAS	2021	DBLP DOI BibTeX RDF
24	Gargi Nandi, Sameer Yadav, P. N. Kondekar	A Fast Settling, High Slew Rate CMOS Recycling Folded Cascode Operational Transconductance Amplifier (OTA) for High Speed Applications.	ICCCNT	2021	DBLP DOI BibTeX RDF
24	Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino, Chua-Chin Wang	A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment.	APCCAS	2021	DBLP DOI BibTeX RDF
24	Kan Li, Chuanshi Yang, Ting Guo, Yuanjin Zheng	A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
24	Jaedo Kim, Seokjae Song, Jeongjin Roh	A High Slew-Rate Enhancement Class-AB Operational Transconductance Amplifier (OTA) for Switched-Capacitor (SC) Applications.	IEEE Access	2020	DBLP DOI BibTeX RDF
24	Deng-Fong Lu, Chin Hsia, Kun-Chu Lee	An Integrated Wideband Operational Transconductance Amplifier with Complementary Slew-Rate Enhancer.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2020	DBLP BibTeX RDF
24	Manikandan Pappiah, Bindu Boby	Capacitor-less FVF low drop-out regulator with active feed-forward compensation and efficient slew-rate enhancer circuit.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
24	Cheuk Ho Hung, Yanqi Zheng, Jianping Guo, Ka Nang Leung	Bandwidth and Slew Rate Enhanced OTA With Sustainable Dynamic Bias.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
24	Luis Miguel Carvalho Freitas, Fernando Morgado Dias	A CMOS slew-rate enhanced OTA for imaging.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
24	Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang	2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
24	Caffey Jindal, Rishikesh Pandey	A class-AB flipped voltage follower cell with high symmetrical slew rate and high current sourcing/sinking capability.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
24	Ahmed Gharib Gadel-Karim, Ahmed N. Mohieldin, Faisal Hussien, Mohamed M. Aboudina	Linearity-Enhanced Ring Amplifier Using Adaptive Slew-Rate Feed-Forward Path.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
24	Jian-An Wang, Yuan-Yao Zhao, Zhengping Zhang	A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
24	Tzung-Je Lee, Ssu-Wei Huang, Chua-Chin Wang	A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
24	Sizhen Li, Kai Yu 0008, Li-xiang Ou, Pan Zhou, Gary Zhang	A compact hybrid envelope tracking supply modulator with wide-band high-slew-rate linear amplifier.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
24	Alec Yen, Benjamin J. Blalock	A High Slew Rate, Low Power, Compact Operational Amplifier Based on the Super-Class AB Recycling Folded Cascode.	MWSCAS	2020	DBLP DOI BibTeX RDF
24	Ola Ibrahim, Rana Hesham, Ahmed Soltan	Controllable OTA Slew-rate for CMOS Image Sensor.	ICM	2020	DBLP DOI BibTeX RDF
24	R. Ghosh, Paolo Seri, Gian Carlo Montanari	Measuring PD under Fast Slew Rate, High Voltage and High Frequency Repetitive Voltage Impulses.	ICIIS	2020	DBLP DOI BibTeX RDF
24	Kun Cai, Gang Zhang	High-Gain PFD/Charge Pump with Gain Proportional to Slew Rate of Up/Down Signals.	ICTA	2020	DBLP DOI BibTeX RDF
24	Timo Mai, Robert Weigel	A 5V, 20MHz Bandwidth, fully differential Operational Amplifier with 70 V/μs Slew Rate and 205 ns/30 ns enable/disable time in 180 nm CMOS.	ISIE	2020	DBLP DOI BibTeX RDF
24	Yong Zhou, Yanqi Zheng, Ka Nang Leung	An Output-Capacitorless Low-Dropout Regulator with High Slew Rate and Unity-Gain Bandwidth.	ISCAS	2020	DBLP DOI BibTeX RDF
24	Kan Li, Chuanshi Yang, Ting Guo, Yuanjin Zheng	A Multi-Loop Slew-Rate Enhanced NMOS LDO Handling 1A Load Current Step with Fast Transient.	ISCAS	2020	DBLP DOI BibTeX RDF
24	Parisa Mahmoudidaryan, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei	Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
24	Po-Yu Kuo, Sheng-Da Tsai	An Enhanced Scheme of Multi-Stage Amplifier With High-Speed High-Gain Blocks and Recycling Frequency Cascode Circuitry to Improve Gain-Bandwidth and Slew Rate.	IEEE Access	2019	DBLP DOI BibTeX RDF
24	Anindita Paul, Jaime Ramírez-Angulo, Antonio Torralba 0002	Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
24	Fatemeh Abdi, Mahnaz Janipoor Deylamani, Parviz Amiri, Mohammad Hossein Refan	Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
24	M. Pilar Garde, Antonio Lopez-Martin, José María Algueta-Miguel, Ramón González Carvajal, Jaime Ramírez-Angulo	Class AB amplifier with enhanced slew rate and GBW.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF