| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 139 | Khurram Waheed, Robert Bogdan Staszewski, John L. Wallberg |
Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation.  |
ISCAS  |
2007 |
DBLP DOI BibTeX RDF |
|
| 62 | Andrew T. K. Tang |
Bandpass spread spectrum clocking for reduced clock spurs in autozeroed amplifiers. |
ISCAS (1) |
2001 |
DBLP DOI BibTeX RDF |
|
| 58 | Debapriya Sahu |
A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 48 | Frederick M. Bingham |
Subfootprint Variability of Sea Surface Salinity Observed during the SPURS-1 and SPURS-2 Field Campaigns. |
Remote. Sens. |
2019 |
DBLP DOI BibTeX RDF |
|
| 48 | Paul P. Sotiriadis |
Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2016 |
DBLP DOI BibTeX RDF |
|
| 48 | Sumit A. Talwalkar |
Digital-to-Time Synthesizers: Separating Delay Line Error Spurs and Quantization Error Spurs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2013 |
DBLP DOI BibTeX RDF |
|
| 38 | T.-L. Hung, J.-L. Huang |
A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 38 | Paul V. Brennan, Dai Jiang, Jianxin Zhang |
Analyses of intermodulation effects in fractional-N frequency synthesis. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
| 38 | Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram |
A low spur fractional-N frequency synthesizer architecture. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
| 38 | Jouko Vankka, Jonne Lindeberg, Kari Halonen |
Direct digital synthesizer with tunable phase and amplitude error feedback structures. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
| 38 | A. E. Hussein, Mohamed I. Elmasry |
Fractional-N frequency synthesizer for wireless communications. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
| 38 | Woogeun Rhee, Akbar Ali |
An on-chip phase compensation technique in fractional-N frequency synthesis. |
ISCAS (3) |
1999 |
DBLP DOI BibTeX RDF |
|
| 36 | Himanshu Arora, Nikolaus Klemmer, Patrick D. Wolf |
A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
RMS phase error, delta-sigma, fractional-N, gain mismatch, phase frequency detector, spurs, thermal noise, VCO, phase noise, frequency synthesizer, charge pump |
| 24 | Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. AbdelRahman, Tianyu Wang 0006, Kyu-Sang Park, Pavan Kumar Hanumolu |
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise. |
ISSCC |
2024 |
DBLP DOI BibTeX RDF |
|
| 24 | Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin |
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs. |
ISSCC |
2024 |
DBLP DOI BibTeX RDF |
|
| 24 | Sumit Kumar, Gaurab Banerjee |
An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in FMCW Radar Synthesizers. |
VLSID |
2024 |
DBLP DOI BibTeX RDF |
|
| 24 | Zhe Li 0014, Elizabeth J. Thompson, Haonan Chen 0001 |
The Uncertainty of IMERG Over the Western Edge of the Eastern Pacific Fresh Pool: An Error Model Based on SPURS-2 Field Campaign Observations. |
IEEE Trans. Geosci. Remote. Sens. |
2023 |
DBLP DOI BibTeX RDF |
|
| 24 | Ang Hu, Zirui Jin, Xiaoyu Shan, Mengming Zhang, Dongsheng Liu, Xuecheng Zou |
Fractional Spurs Reduction Technique Using Probability Density Shaping Sigma-Delta Modulator and Fractional Frequency Divider. |
IEEE Trans. Circuits Syst. II Express Briefs |
2023 |
DBLP DOI BibTeX RDF |
|
| 24 | Shlomo Engelberg |
Education I&M: Seeing Phase Truncation Spurs in the Output of Direct Digital Synthesizers. |
IEEE Instrum. Meas. Mag. |
2023 |
DBLP DOI BibTeX RDF |
|
| 24 | Xu Wang, Michael Peter Kennedy |
Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers. |
ICECS |
2023 |
DBLP DOI BibTeX RDF |
|
| 24 | Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada |
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. |
CICC |
2023 |
DBLP DOI BibTeX RDF |
|
| 24 | Yumeng Yang, Wei Deng 0001, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang 0001, Baoyong Chi |
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration. |
ISSCC |
2023 |
DBLP DOI BibTeX RDF |
|
| 24 | Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka |
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2022 |
DBLP DOI BibTeX RDF |
|
| 24 | Michael Peter Kennedy, Valerio Mazzaro, Dawei Mai |
Nonlinearity-Induced Spurs in Fractional-N Frequency Synthesizers. |
IEEE Trans. Circuits Syst. II Express Briefs |
2022 |
DBLP DOI BibTeX RDF |
|
| 24 | Xingbo Yin, Xiaohua Zong |
International student mobility spurs scientific research on foreign countries: Evidence from international students studying in China. |
J. Informetrics |
2022 |
DBLP DOI BibTeX RDF |
|
| 24 | Xin Lei, Junan Zhang, Jun Deng, Peng Yin 0004, Zhou Shu, Fang Tang |
An Automatic Clock-Induced-Spurs Detector Based on Energy Detection for Direct Digital Frequency Synthesizer. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
| 24 | Dawei Mai, Michael Peter Kennedy |
Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers - How They Arise and How to Get Rid of Them |
|
2022 |
DOI RDF |
|
| 24 | Valerio Mazzaro, Michael Peter Kennedy |
Immunity of ENOP-based Fractional-N Frequency Synthesizer to Wandering and Horn Spurs. |
PRIME |
2022 |
DBLP DOI BibTeX RDF |
|
| 24 | Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie |
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
| 24 | Dawei Mai, Michael Peter Kennedy |
MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency Synthesizer. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2021 |
DBLP DOI BibTeX RDF |
|
| 24 | Mark D. Hickle, Kevin Grout, Curtis Grens, Gregory M. Flewelling, Steven Eugene Turner |
A Single-Chip 25.3-28.0 GHz SiGe BiCMOS PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset and -96 dBc Reference Spurs. |
BCICTS |
2021 |
DBLP DOI BibTeX RDF |
|
| 24 | Frederick M. Bingham, Zhijin Li |
Spatial Scales of Sea Surface Salinity Subfootprint Variability in the SPURS Regions. |
Remote. Sens. |
2020 |
DBLP DOI BibTeX RDF |
|
| 24 | Lingbo Cheng, Mahdi Tavakoli |
COVID-19 Pandemic Spurs Medical Telerobotic Systems: A Survey of Applications Requiring Physiological Organ Motion Compensation. |
Frontiers Robotics AI |
2020 |
DBLP DOI BibTeX RDF |
|
| 24 | Valerio Mazzaro, Michael Peter Kennedy |
Mitigation of "Horn Spurs" in a MASH-Based Fractional-N CP-PLL. |
IEEE Trans. Circuits Syst. II Express Briefs |
2020 |
DBLP DOI BibTeX RDF |
|
| 24 | Hossein Rahmanian Kooshkaki, Patrick P. Mercier |
A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT. |
CICC |
2020 |
DBLP DOI BibTeX RDF |
|
| 24 | Luigi Grimaldi, Dmytro Cherniak, Werner Grollitsch, Roberto Nonis |
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems. |
ISCAS |
2020 |
DBLP DOI BibTeX RDF |
|
| 24 | Yann Donnelly, Michael Peter Kennedy |
Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency Synthesizer. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Yann Donnelly, Michael Peter Kennedy |
Wandering Spurs in MASH 1-1 Delta-Sigma Modulators. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Dawei Mai, Adil Dahlan, Michael Peter Kennedy |
MASH DDSM-Induced Spurs in a Fractional-N Frequency Synthesizer. |
ICECS |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Valerio Mazzaro, Michael Peter Kennedy |
Observations concerning "Horn Spurs" in a MASH-based Fractional-N CP-PLL. |
ICECS |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Michael Peter Kennedy |
Nonlinearity-Induced Spurs in Fractional-N Frequency Synthesizers: State of the Art. |
ICECS |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Dihang Yang, Asad A. Abidi, Hooman Darabi, Hao Xu 0005, David Murphy, Hao Wu 0026, Zhaowen Wang |
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs. |
ISSCC |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Silvester Sadjina, Krzysztof Dufrene, Ram Sunil Kanumalli, Mario Huemer, Harald Pretl |
A Mixed-Signal Circuit Technique for Cancellation of Multiple Modulated Spurs in 4G/5G Carrier-Aggregation Transceivers. |
ISSCC |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001 |
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. |
VLSI Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Debdut Biswas, Tarun Kanti Bhattacharyya |
A Model of Spurs for Delta-Sigma Fractional PLLs. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 24 | Christopher Marquis, Yanhua Bird |
The Paradox of Responsive Authoritarianism: How Civic Activism Spurs Environmental Penalties in China. |
Organ. Sci. |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Dawei Mai, Hongjia Mo, Michael Peter Kennedy |
Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers. |
IEEE Trans. Circuits Syst. II Express Briefs |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen 0001, Robert Bogdan Staszewski |
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Tingbing Ouyang, Kanglin Xiao, Xiaoqi Lin, Changpei Qiu, Bo Wang 0016 |
A multi-phase detecting method for spurs cancellation in all digital fractional-N phase-lock loops. |
MWSCAS |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Gregory Darcheville, Cyril Voillequin, Jean-Baptiste Bégueret |
Direct Digital Frequency Synthesis design methodology for optimized spurs / jitter performances. |
ICECS |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Shravan S. Nagam, Peter R. Kinget |
A 0.008mm2 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a -239.7dB FoM and -64dBc reference spurs. |
CICC |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Cheng-Ru Ho, Mike Shuo-Wei Chen |
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. |
ISSCC |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Jahnavi Sharma, Harish Krishnaswamy |
A dividerless reference-sampling RF PLL with -253.5dB jitter FOM and <-67dBc Reference Spurs. |
ISSCC |
2018 |
DBLP DOI BibTeX RDF |
|
| 24 | Ahmed I. Hussein, Sriharsha Vasadi, Jeyanandh Paramesh |
A 50-66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs. |
IEEE J. Solid State Circuits |
2017 |
DBLP DOI BibTeX RDF |
|
| 24 | Amir Kiperwas, Daniel Rosenfeld, Yonina C. Eldar |
The SPURS Algorithm for Resampling an Irregularly Sampled Signal onto a Cartesian Grid. |
IEEE Trans. Medical Imaging |
2017 |
DBLP DOI BibTeX RDF |
|
| 24 | Tom Verhoeff |
The spurs of D. H. Lehmer - Hamiltonian paths in neighbor-swap graphs of permutations. |
Des. Codes Cryptogr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 24 | Federico Bizzarri, Angelo Brambilla, Alessandro Colombo, Sergio Callegari |
Constant-time discontinuity map for forward sensitivity analysis to initial conditions: Spurs detection in fractional-N PLL as a case study. |
ISCAS |
2017 |
DBLP DOI BibTeX RDF |
|
| 24 | Amir Kiperwas, Daniel Rosenfeld, Yonina C. Eldar |
The SPURS Algorithm for Resampling an Irregularly Sampled Signal onto a Cartesian Grid. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
| 24 | Jianwu Dong, Tian Liu, Feng Chen 0007, Dong Zhou, Alexey Dimov, Ashish Raj, Qiang Cheng, Pascal Spincemaille, Yi Wang 0028 |
Simultaneous Phase Unwrapping and Removal of Chemical Shift (SPURS) Using Graph Cuts: Application in Quantitative Susceptibility Mapping. |
IEEE Trans. Medical Imaging |
2015 |
DBLP DOI BibTeX RDF |
|
| 24 | Jianyu Zhao, Xi Xi, Su Yi |
Resource allocation under a strategic alliance: How a cooperative network with knowledge flow spurs co-evolution. |
Knowl. Based Syst. |
2015 |
DBLP DOI BibTeX RDF |
|
| 24 | Pao-Lung Chen, Ting-Yao Chen |
Digitally controlled oscillator with storage based randomization for spurs reduction. |
ICCE-TW |
2015 |
DBLP DOI BibTeX RDF |
|
| 24 | Paul P. Sotiriadis |
Spurs-free single-bit-output frequency synthesizers for fully-digital RF transmitters. |
ISCAS |
2015 |
DBLP DOI BibTeX RDF |
|
| 24 | Ye Zhang 0003, Ralf Wunderlich, Stefan Heinen |
A low-complexity low-spurs digital architecture for wideband PLL applications. |
Microelectron. J. |
2014 |
DBLP DOI BibTeX RDF |
|
| 24 | Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour |
Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2014 |
DBLP DOI BibTeX RDF |
|
| 24 | Jorge F. Schmidt, Roberto López-Valcarce |
OFDM spectrum sculpting with active interference cancellation: Keeping spectral spurs at bay. |
ICASSP |
2014 |
DBLP DOI BibTeX RDF |
|
| 24 | Nicolas Le Dortz, Jean-Pierre Blanc, Thierry Simon, Sarah Verhaeren, Emmanuel Rouat, Pascal Urard, Stéphane Le Tual, Dimitri Goguet, Caroline Lelandais-Perrault, Philippe Bénabès |
22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS. |
ISSCC |
2014 |
DBLP DOI BibTeX RDF |
|
| 24 | Mohyee Mikhemar, David Murphy, Ahmad Mirzaei, Hooman Darabi |
A Cancellation Technique for Reciprocal-Mixing Caused by Phase Noise and Spurs. |
IEEE J. Solid State Circuits |
2013 |
DBLP DOI BibTeX RDF |
|
| 24 | Vahideh Sadat Sadeghi, Hossein Miar Naimi, Michael Peter Kennedy |
The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better. |
IEEE Trans. Circuits Syst. II Express Briefs |
2013 |
DBLP DOI BibTeX RDF |
|
| 24 | M. Reza Sadeghifar, J. Jacob Wikner |
Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators. |
ISCAS |
2013 |
DBLP DOI BibTeX RDF |
|
| 24 | Tai-You Lu, Wei-Zen Chen |
A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System. |
IEEE Trans. Very Large Scale Integr. Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 24 | Paul P. Sotiriadis, Kostas Galanopoulos |
Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2012 |
DBLP DOI BibTeX RDF |
|
| 24 | Chengwu Tao, Ayman A. Fayed |
A Buck Converter With Reduced Output Spurs Using Asynchronous Frequency Hopping. |
IEEE Trans. Circuits Syst. II Express Briefs |
2011 |
DBLP DOI BibTeX RDF |
|
| 24 | Liming Xiu, Ming Lin, Hong Jiang |
A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer. |
IEEE Trans. Circuits Syst. II Express Briefs |
2011 |
DBLP DOI BibTeX RDF |
|
| 24 | Paul-Peter Sotiriadis |
Spurs suppression and deterministic jitter correction in all-digital frequency synthesizers, current state and future directions. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 24 | Changhong Huan, Xiushan Wu, Dan Wang |
A charge-pump circuit to restrain reference spurs in the PLL. |
ASICON |
2011 |
DBLP DOI BibTeX RDF |
|
| 24 | Colin Weltin-Wu, Enrico Temporiti, Marco Cusmai, Daniele Baldi, Francesco Svelto |
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2010 |
DBLP DOI BibTeX RDF |
|
| 24 | Xiaozhou Yan, Xiaofei Kuang, Nanjian Wu |
An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction. |
CICC |
2009 |
DBLP DOI BibTeX RDF |
|
| 24 | Zhuo Gao, D. Kesharwani, Patrick Chiang 0001, Weiwu Hu |
Measuring and Compensating for Process Mismatch-induced, Reference Spurs in Phase-locked Loops using a Sub-sampled DSP. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 24 | Chen-Wei Huang, Ping Gui, Liming Xiu |
A Wide-tuning-range and Reduced-fractional-spurs Synthesizer Combining Sigma-Delta Fractional-N and Integer Flying-Adder Techniques. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 24 | Valentyn A. Solomko, Peter Weger |
Monolithically integrated SD frequency synthesiser with distributed reference spurs. |
IET Circuits Devices Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 24 | Xiao Pu 0006, Axel Thomsen, Jacob A. Abraham |
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 24 | Tai-You Lu, Wei-Zen Chen |
A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System. |
ISSCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 24 | |
Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture. |
IEEE J. Solid State Circuits |
2007 |
DBLP DOI BibTeX RDF |
|
| 24 | Xiaopin Zhang |
A Fractional- N Frequency Synthesizer With No Fractional Spurs. |
IEEE Trans. Circuits Syst. II Express Briefs |
2006 |
DBLP DOI BibTeX RDF |
|
| 24 | Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Jianguo Ma |
Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2005 |
DBLP DOI BibTeX RDF |
|
| 24 | Max-Elie Salomon, Abdelhakim Khouas, Yvon Savaria |
A complete spurs distribution model for direct digital period synthesizers. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
| 24 | Enrico Temporiti, Guido Albasini, Ivan Bietti, Rinaldo Castello, Matteo Colombo |
A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. |
IEEE J. Solid State Circuits |
2004 |
DBLP DOI BibTeX RDF |
|
| 24 | Hui Pan 0002, Asad A. Abidi |
Spectral spurs due to quantization in Nyquist ADCs. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2004 |
DBLP DOI BibTeX RDF |
|
| 24 | Badre Izouggaghen, Abdelhakim Khouas, Yvon Savaria |
Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
| 24 | Ivan Bietti, Enrico Temporiti, Guido Albasini, Rinaldo Castello |
An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques. |
CICC |
2003 |
DBLP DOI BibTeX RDF |
|
| 24 | Jun S. Huang, Wen J. Lee |
A New Thinning Algorithm for Removing Noise-Spurs and Retaining End-points. |
J. Inf. Sci. Eng. |
1985 |
DBLP BibTeX RDF |
|
| 19 | Martin Knöll |
Diabetes City: How Urban Game Design Strategies Can Help Diabetics. |
eHealth |
2008 |
DBLP DOI BibTeX RDF |
Ubiquitous & Pervasive Computing, Medical Documentation, Diabetes Care, Serious Games, Pervasive Healthcare, Urban Design |
| 19 | M. Ángeles Serrano, Ana Gabriela Maguitman, Marián Boguñá, Santo Fortunato, Alessandro Vespignani |
Decoding the structure of the WWW: A comparative analysis of Web crawls. |
ACM Trans. Web |
2007 |
DBLP DOI BibTeX RDF |
Web graph structure, crawler biases, statistical analysis, Web measurement |
| 19 | Shuilong Huang, Huainan Ma, Zhihua Wang |
Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 19 | Benoit Catteau, Pieter Rombouts, Ludo Weyten |
A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 19 | Paul-Peter Sotiriadis |
Diophantine Frequency Synthesis The Mathematical Principles. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 19 | Barry J. Kronenfeld |
Triangulation of Gradient Polygons: A Spatial Data Model for Categorical Fields. |
COSIT |
2007 |
DBLP DOI BibTeX RDF |
|
| 19 | Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi |
A fractional delay-locked loop for on chip clock generation applications. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 19 | Xinhua Chen, Qiuting Huang |
A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOS. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
low power, CMOS, WCDMA, phase-locked loop, frequency synthesizer |
| 19 | Shuenn-Yuh Lee, Chung-Han Cheng, Ming-Feng Huang, Shyh-Chyang Lee |
A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
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