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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18 occurrences of 17 keywords
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Results
Found 12 publication records. Showing 12 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
84 | Valery A. Vardanian |
Exact probabilistic analysis of error detection for parity checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 222-229, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
circuit under check, multi-output supergate, combinational CUC, restricted observability, restricted detectability, concurrent checker, latency, error detection, combinational circuits, probabilistic analysis, single stuck-at fault, parity checker |
84 | U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta |
PLA based synthesis and testing of hazard free logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 121-124, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions |
61 | Fei Hu, Vishwani D. Agrawal |
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 366-372, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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35 | Henrique Kessler, Murilo Bohlke, Leomar S. da Rosa, Marcelo Schiavon Porto, Vinicius V. Camargo |
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 13th IEEE Latin America Symposium on Circuits and System, LASCAS 2022, Puerto Varas, Chile, March 1-4, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-2008-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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35 | Tooraj Nikoubin, Hareesh-Reddy Basireddy |
Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 17312-17327, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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35 | Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera |
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, pp. 372-377, 2019, IEEE, 978-3-9819263-2-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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35 | Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques 0001, Leomar S. da Rosa Jr. |
Post-processing of supergate networks aiming cell layout optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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35 | Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr. |
Graph-Based Transistor Network Generation Method for Supergate Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(2), pp. 692-705, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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35 | Maicon Schneider Cardoso, Gustavo H. Smaniotto, Regis Zanandrea, Renato Souza de Souza, Leomar S. da Rosa, Felipe de Souza Marques |
Physical design of supergate cells aiming geometrical optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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35 | Dimitrios Kagaris, Themistoklis Haniotakis |
A Methodology for Transistor-Efficient Supergate Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 488-492, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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31 | Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man |
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(3), pp. 217-238, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
supergate, prime-and-irredundant, ATPG, BDD |
26 | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam |
Reducing Structural Bias in Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2894-2903, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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