Search results for "supergate"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
84	Valery A. Vardanian	Exact probabilistic analysis of error detection for parity checkers.	VTS	1997	DBLP DOI BibTeX RDF	circuit under check, multi-output supergate, combinational CUC, restricted observability, restricted detectability, concurrent checker, latency, error detection, combinational circuits, probabilistic analysis, single stuck-at fault, parity checker
84	U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta	PLA based synthesis and testing of hazard free logic.	VLSI Design	1995	DBLP DOI BibTeX RDF	PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions
61	Fei Hu, Vishwani D. Agrawal	Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
35	Henrique Kessler, Murilo Bohlke, Leomar S. da Rosa, Marcelo Schiavon Porto, Vinicius V. Camargo	Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design.	LASCAS	2022	DBLP DOI BibTeX RDF
35	Tooraj Nikoubin, Hareesh-Reddy Basireddy	Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells.	IEEE Access	2019	DBLP DOI BibTeX RDF
35	Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera	SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars.	DATE	2019	DBLP DOI BibTeX RDF
35	Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques 0001, Leomar S. da Rosa Jr.	Post-processing of supergate networks aiming cell layout optimization.	ISCAS	2017	DBLP DOI BibTeX RDF
35	Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.	Graph-Based Transistor Network Generation Method for Supergate Design.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
35	Maicon Schneider Cardoso, Gustavo H. Smaniotto, Regis Zanandrea, Renato Souza de Souza, Leomar S. da Rosa, Felipe de Souza Marques	Physical design of supergate cells aiming geometrical optimizations.	MWSCAS	2016	DBLP DOI BibTeX RDF
35	Dimitrios Kagaris, Themistoklis Haniotakis	A Methodology for Transistor-Efficient Supergate Design.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
31	Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man	Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	supergate, prime-and-irredundant, ATPG, BDD
26	Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam	Reducing Structural Bias in Technology Mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF