Search results for "transaction-level-modeling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
56	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Extending the transaction level modeling approach for fast communication architecture exploration.	DAC	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
49	Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes 0001, Everton Carara	From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.	SBCCI	2003	DBLP DOI BibTeX RDF	transaction level, VHDL, SystemC, System modeling, register transfer level
47	Gunar Schirner, Rainer Dömer	Quantitative analysis of the speed/accuracy trade-off in transaction level modeling.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	system-on-chip, System level design, transaction level modeling
46	Di Wang, Vyas Venkataraman, Zhen Wang 0001, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra	Accelerating multi-party scheduling for transaction-level modeling.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	concurrent programming., multiparty rendezvous, scheduling, transaction level modeling
45	Tayeb Bouhadiba, Florence Maraninchi, Giovanni Funchal	Formal and executable contracts for transaction-level modeling in SystemC.	EMSOFT	2009	DBLP DOI BibTeX RDF	formal component models, systems-on-a-chip, virtual prototyping, transaction-level-modeling
42	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based communication architectures at the CCATB abstraction.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus
40	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, fast communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
37	Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross	Transaction-Level Modeling for Sensor Networks Using SystemC.	SUTC/UMC	2010	DBLP DOI BibTeX RDF	SystemC profiling, simulation, Sensor networks, transaction-level modeling
37	Abhijit K. Deb, Axel Jantsch, Johnny Öberg	System design for DSP applications in transaction level modeling paradigm.	DAC	2004	DBLP DOI BibTeX RDF	system design, DSP, grammar, transaction level modeling
36	Lilian Janin, Doug Edwards	CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse.	ICCSA (3)	2007	DBLP DOI BibTeX RDF
36	Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture.	DATE	2005	DBLP DOI BibTeX RDF
35	Anh-Vu Dinh-Duc, Pascal Vivet, Alain Clouard	A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation.	RIVF	2007	DBLP DOI BibTeX RDF
34	Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser	An MPSoC Performance Estimation Framework Using Transaction Level Modeling.	RTCSA	2007	DBLP DOI BibTeX RDF
33	Lukai Cai, Daniel Gajski	Transaction level modeling: an overview.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	modeling, validation, refinement, synthesis, exploration, transaction level model
31	A. Bernstein, M. Burton, Frank Ghenassia	How to bridge the abstraction gap in system level modeling and design.	ICCAD	2004	DBLP DOI BibTeX RDF
31	Imed Moussa, Thierry Grellier, Giang Nguyen	Exploring SW Performance Using SoC Transaction-Level Modeling.	DATE	2003	DBLP DOI BibTeX RDF
30	Wolfgang Klingauf	Systematic Transaction Level Modeling of Embedded Systems with SystemC.	DATE	2005	DBLP DOI BibTeX RDF
29	Jin Lee, Sin-Chong Park	Transaction level modeling of IEEE 802.11 system.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
28	Grant Martin	The First Transaction, but not the Last.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	SystemC, transaction-level modeling, ESL, TLM
28	Nicola Bombieri, Franco Fummi, Davide Quaglia	TLM/network design space exploration for networked embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	transaction-level modeling, networked embedded systems
28	Maman Abdurohman, Kuspriyanto, Sarwono Sutikno, Arif Sasongko	Transaction Level Modeling for Early Verification on Embedded System Design.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
26	Bastian Haetzer, Martin Radetzki	Systemc transaction level modeling with transaction events.	FDL	2013	DBLP BibTeX RDF
26	Giovanni Beltrame, Donatella Sciuto, Cristina Silvano	Multi-Accuracy Power and Performance Transaction-Level Modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
25	Nicola Bombieri, Andrea Fedeli, Franco Fummi	On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.	MTV	2005	DBLP DOI BibTeX RDF
24	Lin Chen, Wanzhong Sun, Zhixin Wang, Chao Zhou	A SystemC-Based Transaction Level Modeling of On-Chip-Bus.	CSSE (4)	2008	DBLP DOI BibTeX RDF
24	Alena Tsikhanovich, Frédéric Rousseau 0001, El Mostapha Aboulhamid, Guy Bois	Transaction Level Modeling in Hardware/Software System Design using .Net Framework.	CCECE	2006	DBLP DOI BibTeX RDF
24	Heinz-Josef Schlebusch, Gary Smith 0001, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel	Transaction Based Design: Another Buzzword or the Solution to a Design Problem?	DATE	2003	DBLP DOI BibTeX RDF
23	Marco Caldari, Massimo Conti, Massimo Coppola, Stephane Curaba, Lorenzo Pieralisi, Claudio Turchetti	Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0.	DATE	2003	DBLP DOI BibTeX RDF
21	Chen Kang Lo, Ren-Song Tsay	Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model.	ASP-DAC	2009	DBLP DOI BibTeX RDF
21	Katalin Popovici, Xavier Guerin, Frédéric Rousseau 0001, Pier Stanislao Paolucci, Ahmed Amine Jerraya	Platform-based software design flow for heterogeneous MPSoC.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	multimedia, programming environment, software design, SystemC, Simulink, transaction level modeling, Multiprocessor system-on chip
21	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
21	Tse-Chen Yeh, Tsung-Yu Ho, Hung-Yu Chen, Ing-Jer Huang	SystemC-Based Design Space Exploration of a 3D Graphics Acceleration SoC for Consumer Electronics.	EUC	2007	DBLP DOI BibTeX RDF	SystemC modeling, 3D graphics SoC, design space exploration, transaction-level modeling
21	Fabiano Hessel, Vitor M. da Rosa, Carlos Eduardo Reif, César A. M. Marcon, Tatiana Gadelha Serra dos Santos	Scheduling refinement in abstract RTOS models.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	RTOS scheduling, Real-time operating systems, transaction level Modeling
21	Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung	Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	SoC, systemc, transaction-level modeling, TLM, simulation acceleration
21	Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski	Automatic generation of transaction level models for rapid design space exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	transaction-level model, communication synthesis
21	Jens Gladigau	Combining formal model-based system-level design with SystemC transaction level modeling.		2012	RDF
21	Jin Lee, Sin-Chong Park	Methodology of High-Level Transaction Level Modeling Using 802.11 PHY Example.	IEICE Trans. Inf. Syst.	2005	DBLP DOI BibTeX RDF
20	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
20	Bernhard Niemann, Christian Haubelt	Towards a Unified Execution Model for Transactions in TLM.	MEMOCODE	2007	DBLP DOI BibTeX RDF
20	Frederic Doucet, R. K. Shyamasundar, Ingolf H. Krüger, Saurabh Joshi 0001, Rajesh K. Gupta 0001	Reactivity in SystemC Transaction-Level Models.	Haifa Verification Conference	2007	DBLP DOI BibTeX RDF
19	Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi	Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.	DSD	2007	DBLP DOI BibTeX RDF
19	Gunar Schirner, Rainer Dömer	Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	A methodology for abstracting RTL designs into TL descriptions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
17	Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil	TLM: Crossing Over From Buzz To Adoption.	DAC	2007	DBLP DOI BibTeX RDF
17	Amr Baher, Ahmed N. El-Zeiny, Ahmed Aly, Ahmed H. Khalil, Adham Hassan, AbdelRahman Saeed, Karim Abo El Makarem, Magdy A. El-Moursy, Hassan Mostafa	Dynamic power estimation using Transaction Level Modeling.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
17	Takieddine Majdoub, Sébastien Le Nours, Olivier Pasquier, Fabienne Nouvel	Performance evaluation of an automotive distributed architecture based on a high speed power line communication protocol using a transaction level modeling approach.	J. Real Time Image Process.	2014	DBLP DOI BibTeX RDF
17	Rainer Findenig, Thomas Leitner, Wolfgang Ecker	Transaction-Level Modeling and Refinement Using State Charts.	EUROCAST (1)	2013	DBLP DOI BibTeX RDF
17	Rauf Salimi Khaligh	Transaction level modeling and high performance simulation of embedded systems.		2013	RDF
17	Takieddine Majdoub, Sébastien Le Nours, Olivier Pasquier, Fabienne Nouvel	Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication Protocol.	DSD	2011	DBLP DOI BibTeX RDF
17	Alexander W. Rath, Volkan Esen, Wolfgang Ecker	Analog transaction level modeling.	HLDVT	2011	DBLP DOI BibTeX RDF
17	Bastian Haetzer, Martin Radetzki	A case study on message-based discrete event simulation for Transaction Level Modeling.	FDL	2011	DBLP BibTeX RDF
17	Rauf Salimi Khaligh, Martin Radetzki	A metamodel and semantics for transaction level modeling.	FDL	2011	DBLP BibTeX RDF
17	Takieddine Majdoub, Sébastien Le Nours, Olivier Pasquier, Fabienne Nouvel	Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach.	DASIP	2011	DBLP DOI BibTeX RDF
17	François Duhem, Fabrice Muller, Philippe Lorenzini	Methodology for designing partially reconfigurable systems using transaction-level modeling.	DASIP	2011	DBLP DOI BibTeX RDF
17	Yonghyun Hwang, Gunar Schirner, Samar Abdi, Daniel D. Gajski	Accurate timed RTOS model for transaction level modeling.	DATE	2010	DBLP DOI BibTeX RDF
17	Markus Damm, Javier Moreno 0003, Jan Haase 0001, Christoph Grimm 0001	Using Transaction Level Modeling techniques for wireless sensor network simulation.	DATE	2010	DBLP DOI BibTeX RDF
17	Guido Stehr, Josef Eckmuuller	Transaction level modeling in practice: Motivation and introduction.	ICCAD	2010	DBLP DOI BibTeX RDF
17	Anthony Barreteau	Techniques de modélisation transactionnelle pour le dimensionnement des futurs systèmes de radiocommunication mobiles. (Transaction-level modeling techniques for radio communication systems architecting).		2010	RDF
17	Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su	Transaction Level Modeling and Design Space Exploration for SOC Test Architectures.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
17	Amal Banerjee, Andreas Gerstlauer	Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices.	IESS	2009	DBLP DOI BibTeX RDF
17	Anthony Barreteau, Sébastien Le Nours, Olivier Pasquier, Jean Paul Calvez	Transaction level modeling of an adaptive multi-standard and multi-application radio communication system.	FDL	2009	DBLP BibTeX RDF
17	M. Cheikhwafa, Sébastien Le Nours, Olivier Pasquier, Jean Paul Calvez	Transaction level modeling of a FlexRay communication network.	FDL	2009	DBLP BibTeX RDF
17	Sami Boukhechem, El-Bay Bourennane	SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication.	Int. J. Reconfigurable Comput.	2008	DBLP DOI BibTeX RDF
17	Alessandro Mignogna, Massimo Conti, M. D'Angelo, Massimo Baleani, Alberto Ferrari	Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard.	DSD	2008	DBLP DOI BibTeX RDF
17	Chih-Hung Li, Wen-Hsiao Peng, Tihao Chiang	Design space exploration of an H.264/AVC-based video embedding transcoder using transaction level modeling.	ICME	2008	DBLP DOI BibTeX RDF
17	Thomas Lenart, Henrik Svensson, Viktor Öwall	A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing.	DELTA	2008	DBLP DOI BibTeX RDF	SCENIC, Network-on-Chip, Reconfigurable Computing, TLM, 2D Mesh
17	Wolfgang Klingauf	Systematic Transaction Level Modeling of Embedded Systems with SystemC	CoRR	2007	DBLP BibTeX RDF
17	Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture	CoRR	2007	DBLP BibTeX RDF
17	Rauf Salimi Khaligh, Martin Radetzki	Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions.	IESS	2007	DBLP DOI BibTeX RDF
17	Mathieu Dubois, El Mostapha Aboulhamid, Frédéric Rousseau 0001	Acceleration for a compiled Transaction Level Modeling simulation.	ICECS	2006	DBLP DOI BibTeX RDF
17	Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten	Case Study on Transaction Level Modeling.	FDL	2006	DBLP BibTeX RDF
17	Vesa Lahtinen, Jouni Siirtola, Tommi Mäkeläinen	Transaction Level Modeling in Communication Engine Design.	FDL	2006	DBLP BibTeX RDF
17	Liang Liang, Bo Zhou, Xuegong Zhou, Chenglian Peng	System Prototyping Based on SystemC Transaction-Level Modeling.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF
17	Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin	Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.	Des. Autom. Embed. Syst.	2005	DBLP DOI BibTeX RDF
17	Nicola Bombieri, Andrea Fedeli, Franco Fummi	Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling.	MEMOCODE	2005	DBLP DOI BibTeX RDF
17	Wolfgang Klingauf, Robert Günzel	From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling.	FPT	2005	DBLP BibTeX RDF
17	Sherif G. Aly 0001	Transaction Level Modeling of Network Protocols Using Java.	MSV/AMCS	2004	DBLP BibTeX RDF
17	Adam Donlin	Transaction level modeling: flows and use models.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	design abstractions, use models, design flows, TLM
17	Sherif G. Aly 0001, Ashraf M. Salem	Transaction Level Modeling in Java.	FDL	2004	DBLP BibTeX RDF
17	Imed Moussa, Thierry Grellier, Giang Nguyen	Exploring SW Performance Using SoC Transaction-Level Modeling.	Embedded Software for SoC	2003	DBLP DOI BibTeX RDF
16	Ali Habibi, Sofiène Tahar	Design and verification of SystemC transaction-level models.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
14	Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin	You can catch more bugs with transaction level honey.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	system diagnostics, transaction-level models
14	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.	DATE	2006	DBLP DOI BibTeX RDF
14	Tim Kogel, Matthew Braun	Virtual prototyping of embedded platforms for wireless and multimedia.	DATE	2006	DBLP DOI BibTeX RDF
14	Gunar Schirner, Rainer Dömer	Accurate yet fast modeling of real-time communication.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	result oriented modeling, system level design, real-time communication, CAN, controller area network, transaction level model, TLM, ROM
13	Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Andrea Fedeli	Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	hybrid, RTL, design flow, TLM, assertion-based verification
13	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Incremental ABV for functional validation of TL-to-RTL design refinement.	DATE	2007	DBLP DOI BibTeX RDF
13	Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh 0001, Marjan Sirjani, Zainalabedin Navabi	A New Approach for Design and Verification of Transaction Level Models.	ISCAS	2007	DBLP DOI BibTeX RDF
13	Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed	Efficient assertion based verification using TLM.	DATE	2006	DBLP DOI BibTeX RDF
13	Ali Habibi, Sofiène Tahar	Design for Verification of SystemC Transaction Level Models.	DATE	2005	DBLP DOI BibTeX RDF
13	Jin Lee, Sin-Chong Park	Orthogonalized Communication Architecture for MP-SoC with Global Bus.	IWSOC	2005	DBLP DOI BibTeX RDF
13	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	A Modular Approach to Model Heterogeneous MPSoC at Cycle Level.	DSD	2008	DBLP DOI BibTeX RDF
13	Cedric Walravens, Yves Vanderperren, Wim Dehaene	ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models.	DAC	2009	DBLP DOI BibTeX RDF	system C, power modeling, activity monitoring
13	Gunar Schirner, Rainer Dömer	Fast and accurate transaction level models using result oriented modeling.	ICCAD	2006	DBLP DOI BibTeX RDF
12	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	TBV, Model checking, fault models, functional verification, TLM
12	Jae W. Lee, Myron King, Krste Asanovic	Continual hashing for efficient fine-grain state inconsistency detection.	ICCD	2007	DBLP DOI BibTeX RDF
11	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.	DATE	2008	DBLP DOI BibTeX RDF
11	Olivier Ponsini, Wendelin Serwe	A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS.	FM	2008	DBLP DOI BibTeX RDF
11	Gunar Schirner, Rainer Dömer	Quantitative analysis of transaction level models for the AMBA bus.	DATE	2006	DBLP DOI BibTeX RDF
11	Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu	SoC-level risk assessment using FMEA approach in system design with SystemC.	SIES	2009	DBLP DOI BibTeX RDF