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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10 occurrences of 9 keywords
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Results
Found 24 publication records. Showing 24 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
83 | Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 9-14, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin |
42 | Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong |
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 145-152, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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42 | Jin He 0003, Xing Zhang 0002, Ganggang Zhang, Yangyuan Wang |
A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 127-132, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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41 | Hongxia Chen, Sufen Wei, Jing Liu, Guohe Zhang, Cheng-Fu Yang |
A Physical Threshold Voltage Model of Nanoscale Ultra-thin Body Ultra-thin Box SOI MOSFETs with a Gaussian Doping Profile. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICKII ![In: IEEE 2nd International Conference on Knowledge Innovation and Invention, ICKII 2019, Seoul, Korea (South), July 12-15, 2019, pp. 89-92, 2019, IEEE, 978-1-7281-0110-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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32 | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin |
Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 653-656, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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28 | Tamer Cakici, Keejong Kim, Kaushik Roy 0001 |
FinFET Based SRAM Design for Low Standby Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 127-132, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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24 | Nicolo Zagni, Francesco Maria Puglisi, Giovanni Verzellesi, Paolo Pavan |
Variability and sensitivity to process parameters variations in InGaAs dual-gate ultra-thin body MOSFETs: A scaling perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017, pp. 1-5, 2017, IEEE, 978-1-5090-6462-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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24 | Chang Liu, Qinghua Han, Gia Vinh Luong, Keyvan Narimani, Stefan Glass, Andreas T. Tiedemann, Stefan Trellenkamp, Wenjie Yu, Xi Wang, Siegfried Mantl, Qing-Tai Zhao |
Si n-TFETs on ultra thin body with suppressed ambipolarity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, September 12-15, 2016, pp. 408-411, 2016, IEEE, 978-1-5090-2969-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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24 | Martin Rau, Troels Markussen, Enrico Caruso, David Esseni, Elena Gnani, Antonio Gnudi, Petr A. Khomyakov, Mathieu Luisier, Patrik Osgnach, Pierpaolo Palestri, Susanna Reggiani, Andreas Schenk, Luca Selmi, Kurt Stokbro |
Performance study of strained III-V materials for ultra-thin body transistor applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, September 12-15, 2016, pp. 184-187, 2016, IEEE, 978-1-5090-2969-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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24 | Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 2106-2109, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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24 | Chandan Yadav, Amit Agarwal 0007, Yogesh Singh Chauhan |
Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016, pp. 571-572, 2016, IEEE Computer Society, 978-1-4673-8700-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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24 | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 601-604, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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24 | Wen-Teng Chang, Chun-Ming Lai, Wen-Kuan Yeh |
Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(2), pp. 485-489, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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24 | J. Mazurier, Olivier Weber, François Andrieu, Cyrille Le Royer, Olivier Faynot, Maud Vinet |
Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2014 IEEE International Conference on IC Design & Technology, ICICDT 2014, Austin, TX, USA, May 28-30, 2014, pp. 1-4, 2014, IEEE, 978-1-4799-2153-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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24 | Lukas Czornomaz, Nicolas Daix, Pranita Kerber, Kevin Lister, Daniele Caimi, Christophe Rossel, Marilyne Sousa, Emanuele Uccelli, Jean Fompeyrine |
Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: Proceedings of the European Solid-State Device Research Conference, ESSDERC 2013, Bucharest, Romania, September 16-20, 2013, pp. 143-146, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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24 | J. Mazurier, Olivier Weber, François Andrieu, Alain Toffoli, Olivier Thomas, Fabienne Allain, Jean-Philippe Noel, Marc Belleville, Olivier Faynot, T. Poiroux |
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 8(1), pp. 125-132, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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24 | Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman 0001, Parthasarathi Dasgupta |
Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings, pp. 379-380, 2012, Springer, 978-3-642-31493-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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24 | Gang Du, Xiaoyan Liu, Ruqi Han |
High frequency performance of nano-scale ultra-thin-body Schottky-barrier n-MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 54(8), pp. 1756-1761, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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24 | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3), pp. 335-342, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | H. H. Liu, Y. S. Lin, Chen-Chia Chen, Jeng-Tzong Sheu |
Selective functionalization on ultra-thin body FETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEMS ![In: 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2011, Kaohsiung, Taiwan, February 20-23, 2011, pp. 1000-1003, 2011, IEEE, 978-1-61284-775-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
Analysis of power-performance for ultra-thin-body GeOI logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 115-120, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
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24 | Olivier Thomas, Jean-Philippe Noel, Claire Fenouillet-Béranger, Marie-Anne Jaud, J. Dura, P. Perreau, Frédéric Boeuf, François Andrieu, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Andrei Vladimirescu, Amara Amara |
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 1703-1706, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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18 | Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi |
Creating an affordable 22nm node using design-lithography co-optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 95-96, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design technology co-optimization, templates, DFM, regular fabric |
18 | Paul Beckett |
Low-power circuits using dynamic threshold devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 213-216, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
silicide, thin-body, CMOS, nanotechnology, SOI, subthreshold leakage, double-gate |
Displaying result #1 - #24 of 24 (100 per page; Change: )
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