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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6 occurrences of 5 keywords
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Results
Found 28 publication records. Showing 28 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 71 | Yajun Ran, Malgorzata Marek-Sadowska |
On designing via-configurable cell blocks for regular fabrics.  |
DAC  |
2004 |
DBLP DOI BibTeX RDF |
via configurable, layout, regular fabric |
| 69 | Yajun Ran, Malgorzata Marek-Sadowska |
Designing via-configurable logic blocks for regular fabric. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
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| 55 | Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su |
Via configurable three-input lookup-tables for structured ASICs. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
via-configurable, layout, look-up-table, vlsi, structured ASIC |
| 38 | Yajun Ran, Malgorzata Marek-Sadowska |
An integrated design flow for a via-configurable gate array. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 25 | Yajun Ran, Malgorzata Marek-Sadowska |
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
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| 25 | Yajun Ran, Malgorzata Marek-Sadowska |
The Magic of a Via-Configurable Regular Fabric. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
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| 14 | Riccardo Poiani, Ciprian Stirbu, Alberto Maria Metelli, Marcello Restelli |
Optimizing Empty Container Repositioning and Fleet Deployment via Configurable Semi-POMDPs. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
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| 14 | Toshinori Sato, Tomoaki Ukezono |
Tolerating Aging-Induced Timing Violations Via Configurable Approximations. |
GCCE |
2019 |
DBLP DOI BibTeX RDF |
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| 14 | Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas |
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. |
IEEE Trans. Emerg. Top. Comput. |
2017 |
DBLP DOI BibTeX RDF |
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| 14 | Vinícius Dal Bem |
SAT based environment for logical capacity evaluation of via configurable block templates. |
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2016 |
RDF |
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| 14 | Chiung-Chih Ho, Hsin-Pei Tsai, Liang-Chi Lai, Rung-Bin Lin |
A router for via configurable structured ASIC with standard cells and relocatable IPs. |
ISQED |
2015 |
DBLP DOI BibTeX RDF |
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| 14 | Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin |
Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. |
ACM Great Lakes Symposium on VLSI |
2014 |
DBLP DOI BibTeX RDF |
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| 14 | Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng |
Relocatable and resizable SRAM synthesis for via configurable structured ASIC. |
ISQED |
2013 |
DBLP DOI BibTeX RDF |
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| 14 | Hui-Hsiang Tung, Rung-Bin Lin, Mei-Chen Li, Tsung-Han Heish |
Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow. |
IEEE Trans. Very Large Scale Integr. Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 14 | Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai |
Design and analysis of via-configurable routing fabrics for structured ASICs. |
DATE |
2012 |
DBLP DOI BibTeX RDF |
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| 14 | Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas |
Lithography analysis of via-configurable transistor-array fabrics. |
NORCHIP |
2012 |
DBLP DOI BibTeX RDF |
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| 14 | Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas |
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. |
SBCCI |
2011 |
DBLP DOI BibTeX RDF |
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| 14 | Marc Pons 0001, Francesc Moll, Antonio Rubio 0001, Jaume Abella 0001, Xavier Vera, Antonio González 0001 |
Design of complex circuits using the Via-Configurable transistor array regular layout fabric. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
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| 14 | Liang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin |
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 14 | Marc Pons 0001, Francesc Moll, Antonio Rubio 0001, Jaume Abella 0001, Xavier Vera, Antonio González 0001 |
VCTA: A Via-Configurable Transistor Array regular fabric. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 14 | Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen |
Clock routing for structured ASICs with via-configurable fabrics. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 14 | Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin |
Standard Cell Like Via-Configurable Logic Block for Structured ASICs. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
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| 14 | Yajun Ran, Malgorzata Marek-Sadowska |
Via-configurable routing architectures and fast design mappability estimation for regular fabrics. |
ICCAD |
2005 |
DBLP DOI BibTeX RDF |
|
| 14 | Yajun Ran, Malgorzata Marek-Sadowska |
Designing a via-configurable regular fabric. |
CICC |
2004 |
DBLP DOI BibTeX RDF |
|
| 14 | Alwyn Goh, Geong Sen Poh, David Ngo Chek Ling |
Loss-Tolerant Stream Authentication via Configurable Integration of One-Time Signatures and Hash-Graphs. |
Communications and Multimedia Security |
2003 |
DBLP DOI BibTeX RDF |
|
| 14 | Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan |
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. |
ICCD |
2001 |
DBLP DOI BibTeX RDF |
|
| 13 | Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi |
Exploring Logic Block Granularity for Regular Fabrics. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 11 | Holger Lange, Andreas Koch 0001 |
Memory Access Schemes for Configurable Processors. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
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