Search results for "voltage-island"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
121	Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu	Post-placement voltage island generation.	ICCAD	2006	DBLP DOI BibTeX RDF	tree, floorplanning, voltage island
104	Bruce Tseng, Hung-Ming Chen	Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.	ISPD	2008	DBLP DOI BibTeX RDF	voltage island architecture, low power, buffer insertion
103	Dipanjan Sengupta, Resve A. Saleh	Application-driven floorplan-aware voltage island design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic programming, energy, floorplan, voltage island
92	Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu	Architecting voltage islands in core-based system-on-a-chip designs.	ISLPED	2004	DBLP DOI BibTeX RDF	multiple VDD, low-power, floorplanning, system-on-a-chip, voltage island
91	Qiang Ma 0002, Evangeline F. Y. Young	Voltage island-driven floorplanning.	ICCAD	2007	DBLP DOI BibTeX RDF
67	Dipanjan Sengupta, Resve A. Saleh	Supply voltage selection in Voltage Island based SoC design.	SoCC	2008	DBLP DOI BibTeX RDF
67	Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong	Incremental power optimization for multiple supply voltage design.	ISQED	2009	DBLP DOI BibTeX RDF
65	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.	ICCAD	2007	DBLP DOI BibTeX RDF
63	Huaizhi Wu, Martin D. F. Wong	Incremental Improvement of Voltage Assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
63	Huaizhi Wu, Martin D. F. Wong	Improving Voltage Assignment by Outlier Detection and Incremental Placement.	DAC	2007	DBLP DOI BibTeX RDF
59	Dipanjan Sengupta, Resve A. Saleh	Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
56	Huaizhi Wu, Martin D. F. Wong, I-Min Liu	Timing-constrained and voltage-island-aware voltage assignment.	DAC	2006	DBLP DOI BibTeX RDF	voltage assignment, low power, timing, voronoi diagram
55	Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou 0001, Xianlong Hong	Power Delivery Aware Floorplanning for Voltage Island Designs.	ISQED	2007	DBLP DOI BibTeX RDF
53	Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang	Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
49	Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti	Postplacement voltage assignment under performance constraints.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	voltage assignment, Low power, timing, Voronoi diagram
48	Bei Yu 0001, Sheqin Dong, Satoshi Goto, Song Chen 0001	Voltage-island driven floorplanning considering level-shifter positions.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	convex network flow, level shifter assignment, voltage assignment, white space redistribution, voltage-island
45	Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Logic and Layout Aware Voltage Island Generation for Low Power Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
45	Lap-Fai Leung, Chi-Ying Tsui	Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands.	DAC	2007	DBLP DOI BibTeX RDF
41	Wai-Kei Mak, Jr-Wei Chen	Voltage Island Generation under Performance Requirement for SoC Designs.	ASP-DAC	2007	DBLP DOI BibTeX RDF
37	Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman	A semi-custom voltage-island technique and its application to high-speed serial links.	ISLPED	2003	DBLP DOI BibTeX RDF	island, voltage, communications, low power, links, serial
36	Wan-Yu Lee, Iris Hui-Ru Jiang	VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, process variation, monte carlo analysis
36	Wei-Lun Hung, Greg M. Link, Yuan Xie 0001, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner	Temperature-Aware Voltage Islands Architecting in System-on-Chip Design.	ICCD	2005	DBLP DOI BibTeX RDF
35	Gang Qu 0001	Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
35	Abhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N. Choudhary	Evaluating voltage islands in CMPs under process variations.	ICCD	2007	DBLP DOI BibTeX RDF
31	Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs.	ISPD	2009	DBLP DOI BibTeX RDF	multiple-supply voltage designs, physical design, floorplanning, vlsi
28	Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu	Optimality study of resource binding with multi-Vdds.	DAC	2006	DBLP DOI BibTeX RDF	low power design, behavioral synthesis, resource binding
26	Rajarshi Mukherjee, Seda Ogrenci Memik	Evaluation of dual VDD fabrics for low power FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn	Managing power and performance for System-on-Chip designs using Voltage Islands.	ICCAD	2002	DBLP DOI BibTeX RDF
25	Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward	Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
25	Bin Liu 0007, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
22	Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001	Reliability-Aware SOC Voltage Islands Partition and Floorplan.	ISVLSI	2006	DBLP DOI BibTeX RDF
22	Yici Cai, Bin Liu 0007, Qiang Zhou 0001, Xianlong Hong	A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.	PATMOS	2005	DBLP DOI BibTeX RDF
22	Koushik Niyogi, Diana Marculescu	Speed and voltage selection for GALS systems based on voltage/frequency islands.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Iwo Bekker, Lutz Hofmann	Communication-free control concept for operating a low voltage island grid.	ISGT Asia	2023	DBLP DOI BibTeX RDF
19	Shimin Du, Yang Runping, Yuejun Zhang, Yu Shenglu	A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
19	Nicolas Melot, Christoph W. Kessler, Jörg Keller 0001	Voltage Island-Aware Energy-Efficient Scheduling of Parallel Streaming Tasks on Many-Core CPUs.	PDP	2020	DBLP DOI BibTeX RDF
19	Georgios Zervakis 0001, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi	Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
19	Krashna Nand Mishra, Ruchin Jain, Shailendra Sharad, Ravindra Shrivastava	Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs.	VLSID	2019	DBLP DOI BibTeX RDF
19	Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano	Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees.	Near Threshold Computing	2016	DBLP DOI BibTeX RDF
19	Aminollah Mahabadi, Ahmad Khonsari, Behnam Khodabandeloo, Hamid Noori, Alireza Majidi	Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems.	Integr.	2015	DBLP DOI BibTeX RDF
19	Ayhan Demiriz, Nader Bagherzadeh, Özcan Özturk 0001	Voltage island based heterogeneous NoC design through constraint programming.	Comput. Electr. Eng.	2014	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Ji-Heng Wu	F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
19	Zhufei Chu, Yinshui Xia, Lun-Yao Wang, Jian Wang	Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
19	Cristina Silvano, Gianluca Palermo, Sotirios Xydis, Ioannis S. Stamelakos	Voltage island management in near threshold manycore architectures to mitigate dark silicon.	DATE	2014	DBLP DOI BibTeX RDF
19	Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano	Variation-aware voltage island formation for power efficient near-threshold manycore architectures.	ASP-DAC	2014	DBLP DOI BibTeX RDF
19	Jun Liu, Jinhua Guo	Voltage Island Aware Energy Efficient Scheduling of Real-Time Tasks on Multi-core Processors.	HPCC/CSS/ICESS	2014	DBLP DOI BibTeX RDF
19	Ning Xu 0006, Yuchun Ma, Jia Liu 0025, Shou-Chun Tao	Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs.	J. Comput. Sci. Technol.	2013	DBLP DOI BibTeX RDF
19	Rong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu 0001	Post-placement voltage island generation for timing-speculative circuits.	DAC	2013	DBLP DOI BibTeX RDF
19	Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov	Multi-objective voltage island floorplanning using sequence pair representation.	Sustain. Comput. Informatics Syst.	2012	DBLP DOI BibTeX RDF
19	Mario K. Y. Leung, Eric K. I. Chio, Evangeline F. Y. Young	Postplacement Voltage Island Generation.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
19	Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu	Voltage island-driven floorplanning considering level shifter placement.	ASP-DAC	2012	DBLP DOI BibTeX RDF
19	Song Chen 0001, Xiaolin Zhang, Takeshi Yoshimura	Practically scalable floorplanning with voltage island generation.	ISLPED	2012	DBLP DOI BibTeX RDF
19	Aiguo Shen, Fangwei Li	DRX mechanism with hierarchical multi-level voltage island partion.	FSKD	2012	DBLP DOI BibTeX RDF
19	Kan Wang, Sheqin Dong, Satoshi Goto	Voltage island-driven power optimization for application specific network-on-chip design.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
19	Huan Ren, Shantanu Dutt	Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous Vdd, Vth Assignments, Gate Sizing, and Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
19	Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh	Sequence pair based voltage island floorplanning.	IGCC	2011	DBLP DOI BibTeX RDF
19	Nishit Ashok Kapadia, Sudeep Pasricha	VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
19	Sohaib Majzoub	Voltage island design in multi-core SIMD processors.	IDT	2010	DBLP DOI BibTeX RDF
19	Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen	Simultaneous voltage island generation and floorplanning.	SoCC	2010	DBLP DOI BibTeX RDF
19	Behnam Amelifard, Massoud Pedram	Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
19	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	Voltage-Island Partitioning and Floorplanning Under Timing Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
19	Sohaib Majzoub, Resve A. Saleh, Rabab K. Ward	PVT variation impact on voltage island formation in MPSoC design.	ISQED	2009	DBLP DOI BibTeX RDF
19	Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward	Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms.	SoC	2009	DBLP DOI BibTeX RDF
19	Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii	Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.	DATE	2008	DBLP DOI BibTeX RDF
19	Yici Cai, Bin Liu 0007, Qiang Zhou 0001, Xianlong Hong	Voltage Island Generation in Cell Based Dual-Vdd Design.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
19	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	Voltage island aware floorplanning for power and timing optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Emil Talpes, Diana Marculescu	Toward a multiple clock/voltage island design style for power-aware processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang	Post-placement voltage island generation under performance requirement.	ICCAD	2005	DBLP DOI BibTeX RDF
18	Yinghai Lu, Hai Zhou 0001, Li Shang, Xuan Zeng 0001	Multicore parallel min-cost flow algorithm for CAD applications.	DAC	2009	DBLP DOI BibTeX RDF	min-cost flow, parallel programming, multicore
18	Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001	Case Study of Reliability-Aware and Low-Power Design.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF