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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 40 occurrences of 30 keywords
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Results
Found 70 publication records. Showing 70 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
114 | Ram K. Krishnamurthy, Ramalingam Sridhar |
A CMOS wave-pipelined image processor for real-time morphology . |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity |
85 | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
Wave-pipelined on-chip global interconnect. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
79 | V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani |
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
66 | Wei Ling, Yvon Savaria |
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
63 | Debabrata Ghosh, Soumitra Kumar Nandy |
Wave pipelined architecture folding: a method to achieve low power and low area. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits |
61 | Debabrata Ghosh, S. K. Nandy 0001 |
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
56 | Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura |
Scaling Up Of Wave Pipelines. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
49 | Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu |
Wave-pipelining: a tutorial and research survey. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
48 | Junji Ogawa, Mark Horowitz |
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. |
Intelligent Memory Systems |
2000 |
DBLP DOI BibTeX RDF |
|
48 | C. Thomas Gray, Wentai Liu, Ralph K. Cavin III |
Timing constraints for wave-pipelined systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
47 | Gopalakrishnan Lakshminarayanan, B. Venkataramani |
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Suryanarayana Tatapudi, José G. Delgado-Frias |
A High Performance Hybrid Wave-Pipelined Multiplier. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Ajay Joshi, Jeffrey A. Davis |
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
interconnect sharing, time division, wave-pipelining |
39 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Global interconnections in FPGAs: modeling and performance analysis. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
FPGA, throughput, interconnection, wave-pipelined |
37 | Oliver Hauck, A. Katoch, Sorin A. Huss |
VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip. |
ASYNC |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Woo Jin Kim, Yong-Bin Kim |
Automating Wave-Pipelined Circuit Design. |
IEEE Des. Test Comput. |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault tolerant clockless wave pipeline design. |
Conf. Computing Frontiers |
2004 |
DBLP DOI BibTeX RDF |
clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability |
31 | Jiang Xu 0001, Wayne H. Wolf |
Wave pipelining for application-specific networks-on-chips. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance |
31 | Derek C. Wong, Giovanni De Micheli, Michael J. Flynn |
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
31 | Fabian Klass, Michael J. Flynn, Ad J. van de Goor |
Fast multiplication in VLSI using wave pipelining techniques. |
J. VLSI Signal Process. |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis |
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis |
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Ajay Joshi, Jeffrey A. Davis |
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Vinita V. Deodhar, Jeffrey A. Davis |
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Srivastav Sethupathy, Nohpill Park, Marcin Paprzycki |
Logic Restructuring for Delay Balancing in Wave-Pipelined Circuits: An Integer Programming Approach. |
SYNASC |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
High-throughput interconnect wave-pipelining for global communication in FPGAs. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Oliver Hauck, M. Garg, Sorin A. Huss |
Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT. |
ASYNC |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Mark R. Greenstreet, Brian D. Winters |
A Negative-Overhead, Self-Timed Pipeline. |
ASYNC |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar |
Parallel vs. serial on-chip communication. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits |
17 | Sebastian Fischer, Amir Najafi 0001, Alberto García Ortiz |
Wave-Pipelined Source-Synchronous Circuit-Switched Data Transmission. |
MOCAST |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar 0006, Gaurav Singh, Santosh Kumar Vishvakarma |
A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application. |
J. Circuits Syst. Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Amir Najafi 0001, Ardalan Najafi, Alberto García Ortiz |
Stochastic Wave-Pipelined On-Chip Interconnect. |
IEEE Trans. Circuits Syst. II Express Briefs |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul |
Wiring control by RTL design for reconfigurable wave-pipelined circuits. |
APSIPA |
2014 |
DBLP DOI BibTeX RDF |
|
17 | Ashok Jaiswal, Dominik walk, Yuan Fang, Klaus Hofmann |
Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes. |
SoCC |
2014 |
DBLP DOI BibTeX RDF |
|
17 | Aloke Saha, Dipankar Pal, Mahesh Chandra |
Low-power 6-GHz wave-pipelined 8b x 8b multiplier. |
IET Circuits Devices Syst. |
2013 |
DBLP DOI BibTeX RDF |
|
17 | M. Bhaskar 0001, A. Jaswanth, B. Venkataramani |
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing. |
Microprocess. Microsystems |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Tobias Strauch |
Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing. |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Wave-pipelined intra-chip signaling for on-FPGA communications. |
Integr. |
2010 |
DBLP DOI BibTeX RDF |
|
17 | G. Seetharaman, B. Venkataramani |
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. |
ACM Trans. Reconfigurable Technol. Syst. |
2009 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA |
17 | Jiang Xu 0001, Wayne H. Wolf, Wei Zhang 0012 |
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs. |
IEEE Micro |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. |
NOCS |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
17 | Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung |
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Gopalakrishnan Seetharaman, Balasubramanian Venkataramani, Gopalakrishnan Lakshminarayanan |
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
17 | G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan |
Automation techniques for implementation of hybrid wave-pipelined 2D DWT. |
J. Real Time Image Process. |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Vinita V. Deodhar, Jeffrey A. Davis |
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Implementation of Wave-Pipelined Interconnects in FPGAs. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Wave-pipelined signaling for on-FPGA communication. |
FPT |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny |
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. |
ASYNC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Gopalakrishnan Seetharaman, Balasubramanian Venkataramani |
SOC implementation of wave-pipelined circuits. |
FPT |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ajay Jayant Joshi |
Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI). |
|
2006 |
RDF |
|
17 | Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Young-Hyun Jun, Soo-In Cho, Chil-Gee Lee |
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. |
IEEE J. Solid State Circuits |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Ajay Joshi, Jeffrey A. Davis |
Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing. |
SoCC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Vinita V. Deodhar, Jeffrey A. Davis |
Designing for signal integrity in wave-pipelined SOC global interconnects. |
SoCC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Chung-Yu Wu, Yu-Yee Liow |
New current-mode wave-pipelined architectures for high-speed analog-to-digital converters. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Michael Wieckowski, Martin Margala |
A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders. |
SoCC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jiang Xu 0001, Wayne H. Wolf |
A wave-pipelined on-chip interconnect structure for networks-on-chips. |
Hot Interconnects |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Tero Säntti, Jouni Isoaho |
Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Chung-Yu Wu, Yu-Yee Liow |
High-speed CMOS current-mode wave-pipelined analog-to-digital converter. |
ICECS |
2000 |
DBLP DOI BibTeX RDF |
|
17 | José G. Delgado-Frias, Jabulani Nyathi |
A wave-pipelined CMOS associate router for communication switches. |
ISCAS |
2000 |
DBLP DOI BibTeX RDF |
|
17 | José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan |
A wave-pipelined router architecture using ternary associative memory. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura |
Automated Design of Wave Pipelined Multiport Register Files. |
ASP-DAC |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Ho-Jun Song, Jung-Pill Kim, Jae-Jin Lee, Jong-Hoon Oh, Seung-Han Ahn, Inseok Hwang |
A 200 MHz register-based wave-pipelined 64 M synchronous DRAM. |
IEEE J. Solid State Circuits |
1997 |
DBLP DOI BibTeX RDF |
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17 | Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome |
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. |
IEEE J. Solid State Circuits |
1995 |
DBLP DOI BibTeX RDF |
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17 | Wentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III |
A 250-MHz wave pipelined adder in 2-μm CMOS. |
IEEE J. Solid State Circuits |
1994 |
DBLP DOI BibTeX RDF |
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17 | Xuguang Zhang, Ramalingam Sridhar |
Synchronization of Wave-Pipelined Circuits. |
ICCD |
1994 |
DBLP DOI BibTeX RDF |
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17 | Fabian Klass, Michael J. Flynn, Ad J. van de Goor |
A 16x16-bit Static CMOS Wave-Pipelined Multiplier. |
ISCAS |
1994 |
DBLP DOI BibTeX RDF |
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17 | Jui-Ching Shyur, Hung-Pin Chen 0001, Tai-Ming Parng |
On Testing Wave Pipelined Circuits. |
DAC |
1994 |
DBLP DOI BibTeX RDF |
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17 | Debabrata Ghosh, S. K. Nandy 0001 |
A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. |
ICCD |
1993 |
DBLP DOI BibTeX RDF |
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12 | Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny |
Fast Asynchronous Shift Register for Bit-Serial Communication. |
ASYNC |
2006 |
DBLP DOI BibTeX RDF |
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