Search results for "wireability"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Wing K. Luk, Alvar A. Dean	Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout.	DAC	1989	DBLP DOI BibTeX RDF
55	Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan	PEPPER - a timing driven early floorplanner.	ICCD	1995	DBLP DOI BibTeX RDF	PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
42	Jing Lee, Jung-Hua Chou	Hierarchical placement for power hybrid circuits under reliability and wireability constraints.	IEEE Trans. Reliab.	1996	DBLP DOI BibTeX RDF
42	Sarma Sastry, Alice C. Parker	Stochastic Models for Wireability Analysis of Gate Arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1986	DBLP DOI BibTeX RDF
33	Michael D. Hutton	Interconnect prediction for programmable logic devices.	SLIP	2001	DBLP DOI BibTeX RDF	interconnect prodiction, wireability, architecture, programmable logic device
22	Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002	Yield Improvement by Local Wiring Redundancy.	ISQED	2006	DBLP DOI BibTeX RDF
22	Min Tang, Jun-Fa Mao	Optimization of Global Interconnects in High Performance VLSI Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
22	Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt	Toward accurate models of achievable routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
22	Paul Kartschoke, Stephen F. Geissler	Timing Driven Wiring on an Advanced Microprocessor.	DSD	2001	DBLP DOI BibTeX RDF
22	Kanad Chakraborty, Natesan Venkateswaran	Congestion Mitigation During Placement.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Jun Dong Cho, Majid Sarrafzadeh	Four-bend top-down global routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
22	Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah	Congestion Driven Quadratic Placement.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
22	Wing K. Luk, Donald T. Tang, C. K. Wong	Hierarchial global wiring for custom chip design.	DAC	1986	DBLP DOI BibTeX RDF
22	Michael Burstein, Mary N. Youssef	Timing influenced layout design.	DAC	1985	DBLP DOI BibTeX RDF