Search results for "wiresizing"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
171	Jason Cong, Kwok-Shing Leung	Optimal wiresizing under Elmore delay model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
132	Jason Cong, Lei He 0001	Optimal wiresizing for interconnects with multiple sources.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	bundled refinement, decomposition of multi-source routing tree, dominance property, multi-source net, multi-source routing tree, optimal wiresizing, variable segment-division, high performance, SPICE, fidelity, interconnect optimization, Elmore delay, local refinement, layout optimization
132	Tianxiong Xue, Ernest S. Kuh	Post routing performance optimization via multi-link insertion and non-uniform wiresizing.	ICCAD	1995	DBLP DOI BibTeX RDF	post routing performance optimization, link insertion and wiresizing, delay skew, routing area, delay
132	Jason Cong, Lei He 0001	Optimal wiresizing for interconnects with multiple sources.	ICCAD	1995	DBLP DOI BibTeX RDF	performance driven layout, optimal wiresizing, interconnect optimization, VLSI routing
79	Minghorng Lai, Martin D. F. Wong	Maze routing with buffer insertion and wiresizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
63	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
56	Minghorng Lai, D. F. Wong 0001	Maze routing with buffer insertion and wiresizing.	DAC	2000	DBLP DOI BibTeX RDF
33	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Post-processing of clock trees via wiresizing and buffering for robust design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
33	Jatan C. Shah, Sachin S. Sapatnekar	Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.	VLSI Design	1996	DBLP DOI BibTeX RDF	power-delay tradeoffs, dynamic programming, Interconnect, sensitivity, buffer, sizing, repeaters, drivers
33	Tianxiong Xue, Ernest S. Kuh	Post routing performance optimization via tapered link insertion and wiresizing.	EURO-DAC	1995	DBLP DOI BibTeX RDF
33	Jason Cong, Kwok-Shing Leung	Optimal wiresizing under the distributed Elmore delay model.	ICCAD	1993	DBLP DOI BibTeX RDF
23	Sean X. Shi, David Z. Pan	Wire sizing with scattering effect for nanoscale interconnection.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar	A hierarchical decomposition methodology for multistage clock circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	performance driven router, routing, process variations, manufacturability, clock
23	Jason Cong, David Zhigang Pan, Lei He 0001, Cheng-Kok Koh, Kei-Yong Khoo	Interconnect design for deep submicron ICs.	ICCAD	1997	DBLP BibTeX RDF	required-arrival-time Steiner tree higher-order moment signal delay and integrity