Search results for "IWLS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera	Experimental Study on Cell-Base High-Performance Datapath Design.	IWLS	2002	DBLP BibTeX RDF
1	Silviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton	Synthesis of Morphable Multipliers.	IWLS	2002	DBLP BibTeX RDF
1	Stephen A. Edwards	High-Level Synthesis from the Synchronous Language Esterel.	IWLS	2002	DBLP BibTeX RDF
1	Alan Mishchenko, Robert K. Brayton	A Boolean Paradigm in Multi-Valued Logic Synthesis.	IWLS	2002	DBLP BibTeX RDF
1	Jaijeet S. Roychowdhury	Optical Systems 101 for EDA Practitioners.	IWLS	2002	DBLP BibTeX RDF
1	Masayuki Tsukisaka, Masashi Imai, Takashi Nanya	High Throughput Asynchronous Domino Using Dual output Buffer.	IWLS	2002	DBLP BibTeX RDF
1	Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz	A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification.	IWLS	2002	DBLP BibTeX RDF
1	Nattawut Thepayasuwan, Alex Doboli	A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints.	IWLS	2002	DBLP BibTeX RDF
1	Fan Mo, Robert K. Brayton	Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design.	IWLS	2002	DBLP BibTeX RDF
1	Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes	Reversible Logic Circuit Synthesis.	IWLS	2002	DBLP BibTeX RDF
1	Theodore W. Manikas, Gerald R. Kane	Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement.	IWLS	2002	DBLP BibTeX RDF
1	Farzan Fallah	Binary Time Frame Expansion.	IWLS	2002	DBLP BibTeX RDF
1	Chang Woo Kang, Massoud Pedram	Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration.	IWLS	2002	DBLP BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah	Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits.	IWLS	2002	DBLP BibTeX RDF
1	Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton	Reducing Multi-Valued Algebraic Operations to Binary.	IWLS	2002	DBLP BibTeX RDF
1	Christoph Meinel, Harald Sack, Volker Schillings	VisBDD - A Web-based Visualization Framework for OBDD Algorithms.	IWLS	2002	DBLP BibTeX RDF
1	Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain	Improving Sequential ATPG Using SAT Methods.	IWLS	2002	DBLP BibTeX RDF
1	Jason Cong, Joey Y. Lin, Wangning Long	Enhanced SPFD Rewiring on Improving Rewiring Ability.	IWLS	2002	DBLP BibTeX RDF
1	Jorgiano Vidal, David Déharbe, Dominique Borrione	Improving Static Ordering of BDDs for Reachability Analysis.	IWLS	2002	DBLP BibTeX RDF
1	Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala	On-line Error Detection in a Carry-free Adder.	IWLS	2002	DBLP BibTeX RDF
1	Loïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan	A LUT based Approach for High Level Synthesis on FPGAs.	IWLS	2002	DBLP BibTeX RDF
1	Mohamed A. Elgamel, Magdy A. Bayoumi	On Low Power High Level Synthesis Using Genetic Algorithms.	IWLS	2002	DBLP BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani, Fabrizio Luccio, Linda Pagli	Implicit Test of Regularity for Not Completely Specified Boolean Functions.	IWLS	2002	DBLP BibTeX RDF
1	Alexandre V. Bystrov, Alexandre Yakovlev	Synthesis of Asynchronous Circuits with Predictable Latency.	IWLS	2002	DBLP BibTeX RDF
1	Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah	ZBDD-Based Backtrack Search SAT Solver.	IWLS	2002	DBLP BibTeX RDF
1	Prabhakar Kudva, Andrew Sullivan, William E. Dougherty	Metrics for Structural Logic Synthesis.	IWLS	2002	DBLP BibTeX RDF
1	Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis	Comparing Transistor-Level Implementations of 4-Input Logic Functions.	IWLS	2002	DBLP BibTeX RDF
1	Anas Al-Rabadi, Lee W. Casperson	Optical Realizations of Reversible Logic.	IWLS	2002	DBLP BibTeX RDF
1	Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton	Low Power Optimization Techniques for BDD Mapped Finite State Machines.	IWLS	2002	DBLP BibTeX RDF
1	Leyla Nazhandali, Karem A. Sakallah	Majority-Based Decomposition of Carry Logic in Binary Adders.	IWLS	2002	DBLP BibTeX RDF
1	Xinning Wang, Prashant Sawkar, Barbara A. Chappell	A Constructive Matching Algorithm for Library-Based Domino Technology Mapping.	IWLS	2002	DBLP BibTeX RDF
1	Svetlana N. Yanushkevich, Vlad P. Shmerko, V. D. Malyugin, Piotr Dziurzanski	Linearity of World-Level Circuit Models: New Understanding.	IWLS	2002	DBLP BibTeX RDF
1	Rajeev Murgai	Net Buffering in the Presence of Multiple Timing Views.	IWLS	2002	DBLP BibTeX RDF
1	Geun Rae Cho, Tom Chen 0001	On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis.	IWLS	2002	DBLP BibTeX RDF
1	Jordi Cortadella	Bi-Decomposition and Tree-Height Reduction for Timing Optimization.	IWLS	2002	DBLP BibTeX RDF
1	Ankur Srivastava 0001, Majid Sarrafzadeh	Predictability: Definition, Analysis and Optimization.	IWLS	2002	DBLP BibTeX RDF
1	Amit Tandon, Federico Politi	Model Generation and Gate Level Abstraction of Complex CMOS Custom Design for Functional and DFT Validation.	IWLS	2002	DBLP BibTeX RDF
1	Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton	Topologically Constrained Logic Synthesis.	IWLS	2002	DBLP BibTeX RDF
1	Tomas Bengtsson, Andrés Martinelli, Elena Dubrova	A Fast Heuristic Algorithm for Disjunctive.	IWLS	2002	DBLP BibTeX RDF
1	Miodrag Vujkovic, Carl Sechen	Optimized Power-Delay Curve Generation for Standard Cell ICs.	IWLS	2002	DBLP BibTeX RDF
1	Hui-Yuan Song, R. Iris Bahar, Joel Grodstein	Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations.	IWLS	2002	DBLP BibTeX RDF
1	Pawel Kerntopf	An Approach to Designing Complex Reversible Logic Gates.	IWLS	2002	DBLP BibTeX RDF
1	Hua Tang, Alex Doboli	Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing.	IWLS	2002	DBLP BibTeX RDF
1	Federico Politi	Recognition of Transistor Level Complex Sequential and Dynamic Circuits using State Based BDD's.	IWLS	2002	DBLP BibTeX RDF
1	Anas Al-Rabadi	Symmetry as a Base for a New Decomposition of Boolean Logic.	IWLS	2002	DBLP BibTeX RDF
1	Tiberiu Chelcea, Steven M. Nowick	Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems.	IWLS	2002	DBLP BibTeX RDF
1	Pawel Kerntopf	Nonlinear Sifting of Decision Diagrams.	IWLS	2002	DBLP BibTeX RDF
1	Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev	Visualization of Coding Conflicts in Asynchronous Circuit Design.	IWLS	2002	DBLP BibTeX RDF
1	Christoph Meinel, Christian Stangier	Modular Partitioning and Dynamic Conjunction Scheduling in Image Computation.	IWLS	2002	DBLP BibTeX RDF
1	DoRon B. Motter, Igor L. Markov	Overcoming Resolution-Based Lower Bounds for SAT Solvers.	IWLS	2002	DBLP BibTeX RDF
1	Jun Yuan 0007, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz	A Method for Synthesizing Boolean Constrains.	IWLS	2002	DBLP BibTeX RDF
1	Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin	Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net.	IWLS	2002	DBLP BibTeX RDF
1	Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou	A Practical Approach to Cycle Bound Estimation for Property Checking.	IWLS	2002	DBLP BibTeX RDF
1	Steven P. Levitan	Giga = 1/Nano: CAD Tools and Modeling Challenges for Giga-Scale Mixed Technology Micro-Systems.	IWLS	2002	DBLP BibTeX RDF
1	Alan Mishchenko, Tsutomu Sasao	Encoding of Boolean Functions and its Application to LUT Cascade Synthesis.	IWLS	2002	DBLP BibTeX RDF
1	Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah	Efficient Gate and Input Ordering for Circuit-to-BDD Conversion.	IWLS	2002	DBLP BibTeX RDF
1	Rupesh S. Shelar, Sachin S. Sapatnekar	Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits.	IWLS	2002	DBLP BibTeX RDF
1		11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA.	IWLS	2002	DBLP BibTeX RDF
1	Jie-Hong Roland Jiang, Robert K. Brayton	On the Verification of Sequential Equivalence.	IWLS	2002	DBLP BibTeX RDF
1	S. G. Gibb, Laurence E. Turner	The Automatic Generation of Application Specific Processors.	IWLS	2002	DBLP BibTeX RDF
1	René Krenz, Elena Dubrova, Andreas Kuehlmann	Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions.	IWLS	2002	DBLP BibTeX RDF
1	Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita	Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.	IWLS	2002	DBLP BibTeX RDF
1	Alan Mishchenko, Robert K. Brayton	Simplification of Non-Deterministic Multi-Valued Networks.	IWLS	2002	DBLP BibTeX RDF
1	Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura	Comparison of Decision Diagrams for Multiple-Output Logic Functions.	IWLS	2002	DBLP BibTeX RDF
1	Andrei B. Khlopotine, Marek A. Perkowski, Pawel Kerntopf	Reversible Logic Synthesis by Iterative Compositions.	IWLS	2002	DBLP BibTeX RDF
1	Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta 0001	Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals.	IWLS	2002	DBLP BibTeX RDF
1	Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya	Logic Optimization for Asynchronous SI Controllers using Transduction Method.	IWLS	2002	DBLP BibTeX RDF
1	Petra Färm, Elena Dubrova	Technology Mapping for Chemically Assembled Electronic Nanotechnology.	IWLS	2002	DBLP BibTeX RDF
1	Yunjian Jiang, Robert K. Brayton	Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic.	IWLS	2002	DBLP BibTeX RDF
1	Cliff C. N. Sze, Ting-Chi Wang	Multi-Level Circuit Clustering for Delay Minimization.	IWLS	2002	DBLP BibTeX RDF
1	Nina Yevtushenko 0001, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli	Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.	IWLS	2002	DBLP BibTeX RDF
1	Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan	An Efficient Two-Level Filter Scheme for Low Power Cache.	IWLS	2002	DBLP BibTeX RDF
1	Jun Yuan 0007, Ken Albin, Adnan Aziz, Carl Pixley	Simplifying Constraint Solving in Random Simulation Generation.	IWLS	2002	DBLP BibTeX RDF
1	Alan Mishchenko, Marek A. Perkowski	Logic Synthesis of Reversible Wave Cascades.	IWLS	2002	DBLP BibTeX RDF

Publications at "IWLS"( http://dblp.L3S.de/Venues/IWLS )