Search results for "MTCMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya	A 0.5-V MTCMOS/SIMOX logic gate.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
22	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
22	Aveek Sarkar, Shen Lin, Kai Wang	A methodology for analysis and verification of power gated circuits with correlated results.	ISLPED	2007	DBLP DOI BibTeX RDF	RedHawk, standby leakage current, design, verification, analysis, power gate, MTCMOS
22	Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty	Managing standby and active mode leakage power in deep sub-micron design.	ISLPED	2004	DBLP DOI BibTeX RDF	SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
22	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
16	R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh 0004	Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.	ISQED	2009	DBLP DOI BibTeX RDF
16	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
16	Vishal Khandelwal, Ankur Srivastava 0001	Monte-Carlo driven stochastic optimization framework for handling fabrication variability.	ICCAD	2007	DBLP DOI BibTeX RDF
16	B. Chung, J. B. Kuo	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
16	David T. Blaauw, Bo Zhai	Energy efficient design for subthreshold supply voltage operation.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Harmander Deogun, Dennis Sylvester, Kevin J. Nowka	Fine grained multi-threshold CMOS for enhanced leakage reduction.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	Hassan Hassan 0001, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry	Activity Packing in FPGAs for Leakage Power Reduction.	DATE	2005	DBLP DOI BibTeX RDF
16	David T. Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
16	Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo	Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design.	RTCSA	2005	DBLP DOI BibTeX RDF	Tool Chain, Architecture, Compiler, System-on-Chip, Real-Time Operating System
16	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
16	Frank Honoré, Benton H. Calhoun, Anantha P. Chandrakasan	Power-aware architectures and circuits for FPGA-based signal processing.	FPGA	2003	DBLP DOI BibTeX RDF
16	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	Subthreshold leakage modeling and reduction techniques.	ICCAD	2002	DBLP DOI BibTeX RDF
16	Weiping Liao, Joseph M. Basile, Lei He 0001	Leakage power modeling and reduction with data retention.	ICCAD	2002	DBLP DOI BibTeX RDF
16	Mircea R. Stan	Low threshold CMOS circuits with low standby current.	ISLPED	1998	DBLP DOI BibTeX RDF