Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	Resilient microprocessor design for high performance & energy efficiency.	ISLPED	2010	DBLP DOI BibTeX RDF	resilient design
31	Uwe Brinkschulte, Daniel Lohn, Mathias Pacher	Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls.	SEUS	2009	DBLP DOI BibTeX RDF
31	Frederik Vandeputte, Lieven Eeckhout	Finding Stress Patterns in Microprocessor Workloads.	HiPEAC	2009	DBLP DOI BibTeX RDF
31	Hisashige Ando, Ryuji Kan, Yoshiharu Tosaka, Keiji Takahisa, Kichiji Hatanaka	Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor.	DSN	2008	DBLP DOI BibTeX RDF
31	Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang	Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor.	ASP-DAC	2008	DBLP DOI BibTeX RDF
31	Venkatesh Arunachalam, Wayne P. Burleson	Low-power clock distribution in a multilayer core 3d microprocessor.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	3D ic's, 3D processor architectures, clock grids
31	Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti	Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.	DFT	2008	DBLP DOI BibTeX RDF
31	Syed Zafar Shazli, Mehdi Baradaran Tahoori	Obtaining Microprocessor Vulnerability Factor Using Formal Methods.	DFT	2008	DBLP DOI BibTeX RDF
31	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Coprocessor data-path, Template units, Performance, Synthesis, Kernels, Design flow, Chaining
31	Love Kothari, Nicholas P. Carter	Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	memory technologies, low-power design, Emerging technologies
31	Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar	Design fault directed test generation for microprocessor validation.	DATE	2007	DBLP DOI BibTeX RDF
31	Albert Meixner, Daniel J. Sorin	Unified microprocessor core storage.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	unified caching, resource allocation, microarchitecture, power-efficiency
31	Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin	Architecting Microprocessor Components in 3D Design Space.	VLSI Design	2007	DBLP DOI BibTeX RDF
31	Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang	Automatic Verification of External Interrupt Behaviors for Microprocessor Design.	DAC	2007	DBLP DOI BibTeX RDF
31	Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis	Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path.	ICSAMOS	2006	DBLP DOI BibTeX RDF
31	Jin Yang 0006	Verification Challenges and Opportunities in the New Era of Microprocessor Design.	ATVA	2006	DBLP DOI BibTeX RDF
31	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001	Design of a Robust 8-Bit Microprocessor to Soft Errors.	IOLTS	2006	DBLP DOI BibTeX RDF
31	Murari Mani, Mahesh Sharma, Michael Orshansky	Application of fast SOCP based statistical sizing in the microprocessor design flow.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
31	Kotaro Shimamura, Takeshi Takehara, Yosuke Shima, Kunihiko Tsunedomi	A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature.	PRDC	2006	DBLP DOI BibTeX RDF
31	Tun Li, Dan Zhu, Yang Guo 0003, GongJie Liu, Sikun Li	MA2TG: A Functional Test Program Generator for Microprocessor Verification.	DSD	2005	DBLP DOI BibTeX RDF
31	Tun Li, Dan Zhu, Lei Liang, Yang Guo 0003, Sikun Li	Automatic functional test program generation for microprocessor verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
31	Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou	A hardware extension of the RISC microprocessor for Attribute Grammar evaluation.	SAC	2004	DBLP DOI BibTeX RDF	RISC microprocessors, Attribute Grammars, declarative programs
31	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	Fully Automatic Test Program Generation for Microprocessor Cores.	DATE	2003	DBLP DOI BibTeX RDF
31	Mountassar Maamoun, Abdelhalim Benbelkacem, Daoud Berkani, Abderrezak Guessoum	Interfacing in Microprocessor-based Systems with a Fast Physical Addressing.	IWSOC	2003	DBLP DOI BibTeX RDF	Software/hardware System, Fast Physical Addressing, Interfacing, DMA
31	Manish Amde, Ivan Blunno, Christos P. Sotiriou	Automating the design of an asynchronous DLX microprocessor.	DAC	2003	DBLP DOI BibTeX RDF	DLX, asynchronous, design flow
31	Bob Bentley	alidating the Intel® Pentium® 4 Microprocessor.	DSN	2001	DBLP DOI BibTeX RDF
31	Paul Kartschoke, Stephen F. Geissler	Timing Driven Wiring on an Advanced Microprocessor.	DSD	2001	DBLP DOI BibTeX RDF
31	Li-C. Wang, Magdy S. Abadir	Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	high-level test generation, assertion test generation, design validation, logic verification, symbolic trajectory evaluation
31	Leland L. Day, Paul A. Ganfield, Dennis M. Rickert, Fred J. Ziegler	Test methodology for a microprocessor with partial scan.	ITC	1998	DBLP DOI BibTeX RDF
31	Tsang-Ling Sheu, Yuan-Bao Shieh, Woei Lin	The selection of optimal cache lines for microprocessor-based controllers.	MICRO	1990	DBLP BibTeX RDF
31	Alan J. Weissberger	Keeping pace with a single-chip 16-bit microprocessor.	AFIPS National Computer Conference	1975	DBLP DOI BibTeX RDF
30	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.	MTV	2005	DBLP DOI BibTeX RDF
26	Iman Faraji, Moslem Didehban, Hamid R. Zarandi	Analysis of Transient Faults on a MIPS-Based Dual-Core Processor.	ARES	2010	DBLP DOI BibTeX RDF	Dual-core microprocessor, Microprocessor without Interlocked Pipeline Stages (MIPS), simulation-based fault injection, vulnerability analysis, fault propagation
26	Soo-Mook Moon, Scott D. Carson	Generalized Multiway Branch Unit for VLIW Microprocessors.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	generalized multiway branching, VLIW microprocessor, condition tree, mirror normalization, VLIW compiler, Instruction-level parallelism, superscalar microprocessor
26	Walter A. Helbig, Veljko M. Milutinovic	A DCFL E/D-MESFET GaAs Experimental RISC Machine.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	RCA, DCFL E/D-MESFET, RISC machine, GaAs microprocessor, instruction execution sequence, III-V semiconductors, microprocessor chips, instruction set architecture, software environment, reduced instruction set computing, 32 bit, field effect integrated circuits, gallium arsenide
26	Terry J. Fountain, K. N. Matthews, Michael J. B. Duff	The CLIP7A Image Processor.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	CLIP7A, image-processing chip, 16 bit, computer vision, computer vision, computerised picture processing, computerised picture processing, microprocessor chip, microprocessor chips, data processing, 8 bit
25	Jian Shen, Jacob A. Abraham	An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	microprocessor design validation, coverage measurement, test generation
25	A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble	Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces.	EUROMICRO	1997	DBLP DOI BibTeX RDF	memory hierarchy simulation, desktop PC, commodity chips, PC microcomputers, synthetic bus traces, dynamically scheduled superscalar microprocessor, performance evaluation, memory architecture
25	Robert B. Jones, David L. Dill, Jerry R. Burch	Efficient validity checking for processor verification.	ICCAD	1995	DBLP DOI BibTeX RDF	formal verification, validation, decision procedure, uninterpreted functions, microprocessor architecture
25	G. Rothbart, R. Fullwood, H. O. Conde	Automatic data acquisition and processing of train deceleration for rapid transit train systems.	ACM Annual Conference (2)	1978	DBLP DOI BibTeX RDF	Microprocessor monitor, Rapid transit system, Data acquisition
25	Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	instruction-level error, microprocessor controller, Fault simulation, concurrent error detection
25	Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris	Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	scheduler, microprocessor, invariance, Concurrent error detection
25	Klaus-Dietrich Kramer, Thomas Stolze, Alexander Oppelt	Microprocessor Benchmarks - A Detailed Look at Techniques, Problems and Solutions.	ICSEng	2011	DBLP DOI BibTeX RDF	Performance Assessment and Rating, Runtime Measurement, Benchmarks, Microprocessor, Microcontroller
25	Lingkan Gong, Jingfen Lu	Verification-Purpose Operating System for Microprocessor System-Level Functions.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	microprocessor verification, system-level function, Verification-Purpose Operating System, VPOS, FPGA, design and test
25	Amol Vasudeva, Arvind Kumar Sharma, Ashish Kumar	Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator.	CICSyN	2009	DBLP DOI BibTeX RDF	Microprocessor Simulator, x86 Architecture Simulator, Register/Instruction Set Simulator, Object oriented, Assembler
25	Cecilia Metra, Daniele Rossi 0001, Martin Omaña 0001, Abhijit Jas, Rajesh Galivanche	Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.	ETS	2008	DBLP DOI BibTeX RDF	microprocessor, error detecting codes, on-line testing, control logic
25	Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward	Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	fault modeling and simulation, fault tolerance, fault injection, soft error, SEU, microprocessor test
25	Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David M. Brooks	Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance.	IEEE Micro	2006	DBLP DOI BibTeX RDF	microprocessor, energy savings, Dynamic-compilation
25	Scott Davidson 0001	An insider's look at microprocessor design.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	Pentium Pro, management, Intel, microprocessor design
25	Michael J. Flynn, Patrick Hung	Microprocessor Design Issues: Thoughts on the Road Ahead.	IEEE Micro	2005	DBLP DOI BibTeX RDF	SIA, performance consideration, reliability, Power, SoC designs, microprocessor design, process technology
25	Lieh-Ming Wu, Kuochen Wang, Chuang-Yi Chiu	A BNF-based automatic test program generator for compatible microprocessor verification.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Advanced microprocessor, compatibility verification, top-down recursive descent parsing method, coverage, automatic program generator, BNF
25	Cecilia Metra, T. M. Mak, Martin Omaña 0001	Fault secureness need for next generation high performance microprocessor design for testability structures.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	built in self test, design for testability, microprocessor, comparator, fault secureness
25	Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson	Design and implementation of the POWER5 microprocessor.	DAC	2004	DBLP DOI BibTeX RDF	POWER5, simultaneous multi-threading (SMT), clock gating, power reduction, microprocessor design, temperature sensor
25	Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama	A 1.3GHz fifth generation SPARC64 microprocessor.	DAC	2003	DBLP DOI BibTeX RDF	unix server, reliability, microprocessor, microarchitecture, SPARC, clock distribution
25	Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo	A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications.	ASAP	2000	DBLP DOI BibTeX RDF	FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV
25	Rajesh Raina, Robert F. Molyneaux	Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	High-Level Design Validation, Silicon Validation, Pseudo-Random Testing, Microprocessor Testing
25	Scott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey	Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	21264, coverage anaysis, verification, architecture, validation, microprocessor, pseudo-random, Alpha
25	Mohammed Atiquzzaman, W. H. Shehadah	A Microprocessor-Based Office Image Processing System-An Extension of Work.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	microprocessor-based office image processing system, compute-bound, I/O-bound state, image input time, computerised picture processing
25	Luigi Ciminiera, Adriano Valenzano	Authentication Mechanisms in Microprocessor-Based Local Area Networks.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	authentication mechanisms, microprocessor-based local area networks, unauthorized use, intruders, interface process, user-server connection, unauthorized requests, capability checking, iAPX432-based hosts, database, cache, searching, service, local area networks, security of data, identity, protect, server, hardware support, shared resources, parallel search, access rights, check, performance issues
25	Kwok-Tung Fung, Hwa C. Torng	On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	multiple-microprocessor system, interference, memory mapping, memory conflict, Bus contention
25	Jan Van Campenhout, Paul H. Notredame	A Stochastic Model for Closed-Loop Preemptive Microprocessor I/O Organizations.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Microprocessor systems, priority systems, performance analysis, stochastic modeling
25	Marshall C. Pease III	The Indirect Binary n-Cube Microprocessor Array.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Admissible maps, microprocessor array, n-cube array, triangular permutations, virtual array, grid computations, parallel processing, fast Fourier transform, switching network, array processor, permutation network, parallel matrix multiplication
25	Edward Chen, William A. Gruver, Dorian Sabaz, Lesley Shannon	Facilitating Processor-Based DPR Systems for non-DPR Experts.	FCCM	2008	DBLP DOI BibTeX RDF
25	Smriti Bhatnagar, Richa Gupta, Kapil Kumar Singla	Apparatus for Ensuring Seat Belt Usage and Checking Blood Alcohol Concentration.	RAM	2008	DBLP DOI BibTeX RDF
25	Cecilia Metra, Daniele Rossi 0001, T. M. Mak	Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	fault tolerance, Reliability, VLSI, testing
25	Youngjin Cho, Naehyuck Chang	Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
25	Fred A. Bower, Daniel J. Sorin, Sule Ozev	Online diagnosis of hard faults in microprocessors.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Hard fault tolerance, fine-grained diagnosis, processor microarchitecture
25	Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel	Coverage Driven Verification applied to Embedded Software.	ISVLSI	2007	DBLP DOI BibTeX RDF
25	Nick Tredennick	Computing in transition.	HPRCTA	2007	DBLP DOI BibTeX RDF
25	Fred A. Bower, Daniel J. Sorin, Sule Ozev	A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
25	Sitaram Yadavalli, Sandip Kundu	On Fault-Simulation Through Embedded Memories On Large Industrial Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
25	William Cunningham, Steven E. Wixson	Useful ideas for microcomputer operating systems.	ACM Southeast Regional Conference	1979	DBLP DOI BibTeX RDF
24	Jonathan Owen, Maurice Steinman	Northbridge Architecture of AMD's Griffin Microprocessor Family.	IEEE Micro	2008	DBLP DOI BibTeX RDF	data communications devices, low-power design, power management, processors, I/O and data communications, Hot Chips 19
24	Davy Genbrugge, Lieven Eeckhout	Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Simulation, Modeling techniques, Performance Analysis and Design Aids
24	Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis	Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	coprocessor data-path, template units, kernels, performance improvements, design flow, energy reductions, architectural synthesis
24	Yu Zhou, Somnath Paul, Swarup Bhunia	Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement.	DATE	2008	DBLP DOI BibTeX RDF
24	Shijian Zhang, Weiwu Hu	Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor.	PRDC	2008	DBLP DOI BibTeX RDF
24	Marek Chrobak, Christoph Dürr, Mathilde Hurand, Julien Robert	Algorithms for Temperature-Aware Task Scheduling in Microprocessor Systems.	AAIM	2008	DBLP DOI BibTeX RDF
24	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Microprocessor Verification via Feedback-Adjusted Markov Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro	Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	error tolerant system, single event upset (SEU), Digital SignalProcessing (DSP), fault-tolerance, sigma-delta
24	Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid	Two-level microprocessor-accelerator partitioning.	DATE	2007	DBLP DOI BibTeX RDF
24	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path.	IPDPS	2007	DBLP DOI BibTeX RDF
24	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	coprocessor data-path, synthesis, energy savings, performance improvements, design flow
24	Rajdeep Chakraborty, J. K. Mandal 0001	A Microprocessor-based Block Cipher through Rotational Addition Technique (RAT).	ICIT	2006	DBLP DOI BibTeX RDF
24	Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu	Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.	ISMVL	2006	DBLP DOI BibTeX RDF
24	Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese	Workload Slicing for Characterizing New Features in High Performance Microprocessors.	MTV	2006	DBLP DOI BibTeX RDF
24	Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake	Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
24	Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David M. Brooks	A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance.	MICRO	2005	DBLP DOI BibTeX RDF
24	Danghui Wang, Xiaoya Fan, Deyuan Gao, Shengbing Zhang, Jianfeng An	Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip.	ICESS	2005	DBLP DOI BibTeX RDF
24	Masayuki Miyazaki, Goichi Ono, Takayuki Kawahara	Optimum threshold-voltage tuning for low-power, high-performance microprocessor.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
24	Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.	MTV	2005	DBLP DOI BibTeX RDF
24	Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.	MTV	2005	DBLP DOI BibTeX RDF
24	Warren A. Hunt Jr.	Mechanical Mathematical Methods for Microprocessor Verification.	CAV	2004	DBLP DOI BibTeX RDF
24	Shlomi Dolev, Yinnon A. Haviv	Self-Stabilizing Microprocessor - Analyzing and Overcoming Soft-Errors (Extended Abstract).	ARCS	2004	DBLP DOI BibTeX RDF
24	Ming-che Lai, Kui Dai, Li Shen 0007, Zhiying Wang 0003	A New Technique for Program Code Compression in Embedded Microprocessor.	ICESS	2004	DBLP DOI BibTeX RDF
24	Byung-Soo Choi, Jeong-A Lee, Dong-Soo Har	High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
24	Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal	Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.	ISCA	2004	DBLP DOI BibTeX RDF
24	George K. Adam	Design of a Microprocessor-Based Control System of a Compression Molding Process.	ICECCS	2004	DBLP DOI BibTeX RDF
24	W. Lindsay, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Automatic Test Programs Generation Driven by Internal Performance Counters.	MTV	2004	DBLP DOI BibTeX RDF
24	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static energy reduction techniques for microprocessor caches.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF