Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Sorin Cotofana, Stamatis Vassiliadis |
Signed Digit Addition and Related Operations with Threshold Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 193-207, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation |
18 | C.-C. Wang, C. J. Huang, G.-C. Lin |
A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 439-442, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr. |
Modified Booth algorithm for high radix fixed-point multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(2), pp. 164-167, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Paolo Montuschi, Luigi Ciminiera |
n × n carry-save multipliers without final addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 54-61, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Stephen E. McQuillan, John V. McCanny, Robert Hamill |
New algorithms and VLSI architectures for SRT division and square root. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 80-86, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Hosahalli R. Srinivas, Keshab K. Parhi |
High-speed VLSI arithmetic processor architectures using hybrid number representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 4(2-3), pp. 177-198, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Laxmi N. Bhuyan, Dharma P. Agrawal |
Applications of SIMD computers in signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1982 National Computer Conference, 7-10 June, 1982, Houston, Texas, USA, pp. 135-142, 1982, AFIPS Press, 0-88283-035-X. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
15 | Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama |
Fully Source-Coupled Logic Based Multiple-Valued VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 270-275, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic |
15 | Jeong-A Lee, Tomás Lang |
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 1016-1025, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
rotation direction, angle calculation, constant-factor redundant-CORDIC, plane rotations, correcting iterations, radix-4, convergence, iterative methods, digital arithmetic, number theory, convergence of numerical methods, algorithm theory, scale factor, radix-2 |
15 | Homayoon Sam, Arupratan Gupta |
A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1006-1015, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
fixed coefficient multiplication, controlled coefficient multiplication, multibit recoding algorithm, signed two's complement binary numbers, radix 2/sup k/, very high speed adders, hardware parallel multipliers, 5-bit recoding, performance, computer arithmetic, digital arithmetic, multiplying circuits, signed-digit representation |
14 | Diego F. G. Coelho, Renato J. Cintra |
Discrete Fourier Transform Approximations Based on the Cooley-Tukey Radix-2 Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2402.16225, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Xiao Zhou, Xuerong Chen, Yi He, Xingang Mou |
A Flexible-Channel MDF Architecture for Pipelined Radix-2 FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 38023-38033, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | |
Fast multiplication by two's complement addition of numbers represented as a set of polynomial radix 2 indexes, stored as an integer list for massively parallel computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.09922, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Zongsheng Hou, Neng Zhang 0002, Bohan Yang 0004, Hanning Wang, Min Zhu 0001, Shouyi Yin, Shaojun Wei, Leibo Liu |
Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7), pp. 2024-2037, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Sirani M. Perera, Arjuna Madanayake, Renato J. Cintra |
Radix-2 Self-Recursive Sparse Factorizations of Delay Vandermonde Matrices for Wideband Multi-Beam Antenna Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.00779, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Xiangren Chen, Bohan Yang 0004, Shouyi Yin, Shaojun Wei, Leibo Liu |
CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1), pp. 94-126, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Garima Thakur, Harsh Sohal, Shruti Jain |
A novel parallel prefix adder for optimized Radix-2 FFT processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multidimens. Syst. Signal Process. ![In: Multidimens. Syst. Signal Process. 32(3), pp. 1041-1063, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Sirani M. Perera, Levi E. Lingsch |
Sparse Matrix Based Low-Complexity, Recursive, and Radix-2 Algorithms for Discrete Sine Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 141181-141198, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Lucius T. Schoenbaum |
A Tapered Floating Point Extension for the Redundant Signed Radix 2 System Using the Canonical Recoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2105.14401, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
14 | Pawel Tarasiuk, Adam Wojciechowski, Mykhaylo Yatsymirskyy |
Iterative Radix-2 FHT Algorithm with DIF that Minimizes Number of Computed Twiddle Factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSIT (1) ![In: IEEE 16th International Conference on Computer Sciences and Information Technologies, CSIT 2021, Lviv, Ukraine, September 22-25, 2021, pp. 283-286, 2021, IEEE, 978-1-6654-4257-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Lei Qiu 0002, Keping Wang, Chuanshi Yang, Yuanjin Zheng |
A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 83062-83069, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Sirani M. Perera, Arjuna Madanayake, Renato J. Cintra |
Radix-2 Self-Recursive Sparse Factorizations of Delay Vandermonde Matrices for Wideband Multi-Beam Antenna Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 25498-25508, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Diwei Li, Dixian Zhao |
High-Throughput Low-Power Area-Efficient Outphasing Modulator Based on Unrolled and Pipelined Radix-2 CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(2), pp. 480-491, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | M. S. Kavitha, P. Rangarajan |
An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2 r Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 39(11), pp. 5801-5829, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Ahmed Liacha, Abdelkrim Kamel Oudjida, Mohammed Bakiri, José Monteiro 0001, Paulo F. Flores |
Radix-2 r recoding with common subexpression elimination for multiple constant multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 14(7), pp. 990-994, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Sirani M. Perera, Jianhua Liu |
Complexity reduction, self/completely recursive, radix-2 DCT I/IV algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Appl. Math. ![In: J. Comput. Appl. Math. 379, pp. 112936, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Jingxin Dai, Hang Yin |
Design and Realization of Non-radix-2 FFT Prime Factor Processor for 5G Broadcasting in Release 16. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCID ![In: 13th International Symposium on Computational Intelligence and Design, ISCID 2020, Hangzhou, China, December 12-13, 2020, pp. 406-409, 2020, IEEE, 978-1-7281-8446-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Zhongju Li, Ahmad Nimr, Gerhard P. Fettweis |
Implementation and Performance Measurement of Flexible Radix-2 GFDM Modem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
5G World Forum ![In: 2nd IEEE 5G World Forum, 5GWF 2019, Dresden, Germany, September 30 - October 2, 2019, pp. 130-134, 2019, IEEE, 978-1-7281-3627-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | M. Mahendra Reddy, Sounak Roy |
Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers, pp. 141-149, 2019, Springer, 978-981-32-9766-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Kamlesh Gupta, Shabbir N. Merchant, Uday B. Desai |
Inherence of Hard Decision Fusion in Soft Decision Fusion and a Generalized Radix-2 Multistage Decision Fusion Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 6, pp. 55701-55711, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Chen Yang 0003, Yizhuang Xie, He Chen |
A novel word length optimization method for radix-2 k fixed-point FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 61(2), pp. 029301:1-029301:3, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Sirani M. Perera, Jianhua Liu |
Lowest Complexity Self-Recursive Radix-2 DCT II/III Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Matrix Anal. Appl. ![In: SIAM J. Matrix Anal. Appl. 39(2), pp. 664-682, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Yazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman, Md. Shabiul Islam |
FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1806.04570, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
14 | Rozita Teymourzadeh, Mometo Jim Abigo, Mok Vee Hoong |
Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1806.03716, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
14 | Yazan Samir Algnabi, Furat A. Aldaamee, Rozita Teymourzadeh |
Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1806.04573, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
14 | Rozita Teymourzadeh, Memtode Jim, Mok Vee Hong |
Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1806.04572, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
14 | Rahul Shrestha, Ashutosh Sharma |
VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 131-136, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Anirban Ganguly, Anirban Chakraborty 0004, Ayan Banerjee 0003 |
A Highly Accurate Current Mode Analog Implementation of Radix-2 FFT/IFFT Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: 8th International Symposium on Embedded Computing and System Design, ISED 2018, Cochin, India, December 13-15, 2018, pp. 90-94, 2018, IEEE, 978-1-5386-6575-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Harsha Keerthan Samudrala, Shaik A. Qadeer, Syed Azeemuddin, Mohammed Zafar Ali Khan |
Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018, pp. 21-26, 2018, IEEE, 978-1-5386-9172-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Qianjian Xing, Zhen-guo Ma, Feng Yu 0003 |
A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(6), pp. 1333-1337, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Behnam Samadpoor Rikan, Dong-Soo Lee, Kang-Yoon Lee |
A 6-bit 4 MS/s, VCM-based sub-radix-2 SAR ADC with inverter type comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 62, pp. 120-125, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Lee F. Richardson, William F. Eddy |
An Algorithm for the 2D Radix-2 Sliding Window Fourier Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1707.08213, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
14 | Hossein Moradian, Jeong-A Lee, Joonsang Yu |
Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 88(3), pp. 297-309, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Ahmad Nimr, Maximilian Matthé, Dan Zhang 0003, Gerhard P. Fettweis |
Optimal Radix-2 FFT Compatible Filters for GFDM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Commun. Lett. ![In: IEEE Commun. Lett. 21(7), pp. 1497-1500, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Fahad Qureshi, Muazam Ali, Jarmo Takala |
Multiplierless reconfigurable processing element for mixed radix-2/3/4/5 FFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2017 IEEE International Workshop on Signal Processing Systems, SiPS 2017, Lorient, France, October 3-5, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0446-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Sian-Jheng Lin, Amira Alloum, Tareq Y. Al-Naffouri |
Principal pivot transforms on radix-2 DFT-type matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIT ![In: 2017 IEEE International Symposium on Information Theory, ISIT 2017, Aachen, Germany, June 25-30, 2017, pp. 2358-2362, 2017, IEEE, 978-1-5090-4096-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Fahad Qureshi, Jarmo Takala |
Twiddle factor complexity analysis of Radix-2 FFT algorithms for pipelined architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 51st Asilomar Conference on Signals, Systems, and Computers, ACSSC 2017, Pacific Grove, CA, USA, October 29 - November 1, 2017, pp. 1034-1037, 2017, IEEE, 978-1-5386-1823-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Fahad Qureshi, Jarmo Takala, Anastasia Volkova, Thibault Hilaire |
Multiplierless unified architecture for mixed radix-2/3/4 FFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 25th European Signal Processing Conference, EUSIPCO 2017, Kos, Greece, August 28 - September 2, 2017, pp. 1334-1338, 2017, IEEE, 978-0-9928626-7-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan |
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(6), pp. 2402-2406, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi |
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(6), pp. 703-709, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Hossein Moradian, Jeong-A Lee, Adnan Hashmi |
Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 63, pp. 256-266, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Xiaobo Yin, Feng Yu 0003, Zhen-guo Ma |
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(8), pp. 803-807, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Tomasz Patyk, Jarmo Takala |
Hardware-efficient index mapping for mixed radix-2/3/4/5 FFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016, pp. 196-201, 2016, IEEE, 978-1-5090-3076-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Tomasz Patyk, Fahad Qureshi, Jarmo Takala |
Hardware-Efficient Twiddle Factor Generator for Mixed Radix-2/3/4/5 FFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2016 IEEE International Workshop on Signal Processing Systems, SiPS 2016, Dallas, TX, USA, October 26-28, 2016, pp. 201-206, 2016, IEEE, 978-1-5090-3361-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Fahad Qureshi, Jarmo Takala |
New Identical Radix-2^k Fast Fourier Transform Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2016 IEEE International Workshop on Signal Processing Systems, SiPS 2016, Dallas, TX, USA, October 26-28, 2016, pp. 195-200, 2016, IEEE, 978-1-5090-3361-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Roumen Kountchev, Suzan Anwar, Roumiana Kountcheva, Mariofanna G. Milanova |
Face Recognition in Home Security System Using Tensor Decomposition Based on Radix-(2 × 2) Hierarchical SVD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MPRSS ![In: Multimodal Pattern Recognition of Social Signals in Human-Computer-Interaction - 4th IAPR TC 9 Workshop, MPRSS 2016, Cancun, Mexico, December 4, 2016, Revised Selected Papers, pp. 48-59, 2016, Springer, 978-3-319-59258-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima |
ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COOL Chips ![In: 2016 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XIX, Yokohama, Japan, April 20-22, 2016, pp. 1-3, 2016, IEEE Computer Society, 978-1-5090-1386-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen |
LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016, pp. 577-580, 2016, IEEE, 978-1-5090-1570-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Ze-ke Wang, Xue Liu 0003, Bingsheng He, Feng Yu 0003 |
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(5), pp. 973-977, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Jo C. Ebergen, Navaneeth Jamadagni |
Radix-2 Division Algorithms with an Over-Redundant Digit Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 64(9), pp. 2652-2663, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Hélio M. de Oliveira, Viviane L. Sousa, A. N. Helfarne, Ricardo M. Campello de Souza |
Radix-2 Fast Hartley Transform Revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1503.03794, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
14 | Rahul Shrestha, Roy P. Paily |
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 81(2), pp. 305-320, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Jinqi Liu, Qianjian Xing, Xiaobo Yin, Xiubin Mao, Feng Yu 0003 |
Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 62-II(11), pp. 1083-1087, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Zhen-guo Ma, Xiaobo Yin, Feng Yu 0003 |
A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 62-II(9), pp. 876-880, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Sidinei Ghissoni, Eduardo Costa 0001, Ricardo Reis 0001 |
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2015, Salvador, Brazil, September 1-4, 2015, pp. 169-176, 2015, IEEE, 978-1-4673-9419-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Hsin-Fu Luo, Ming-Der Shieh, Kun-Hsien Lee |
A radix-2/3/22/23 MDC architecture for variable-length FFT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-TW ![In: IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015, Taipei, Taiwan, June 6-8, 2015, pp. 180-181, 2015, IEEE, 978-1-4799-8745-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Goutham N. C. Shanmugam, Yingjie Lao, Keshab K. Parhi |
An obfuscated radix-2 real FFT architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 2015 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2015, South Brisbane, Queensland, Australia, April 19-24, 2015, pp. 1056-1060, 2015, IEEE, 978-1-4673-6997-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Soumak Mookherjee, Linda DeBrunner, Victor E. DeBrunner |
A low power radix-2 FFT accelerator for FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015, Pacific Grove, CA, USA, November 8-11, 2015, pp. 447-451, 2015, IEEE, 978-1-4673-8576-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Jiajia Chen 0002, Jiatao Ding |
New algorithm for design of low complexity twiddle factor multipliers in radix-2 FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 958-961, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Mohammed Dali, Ryan M. Gibson, Abbes Amira, Abdelrezak Guessoum, Naeem Ramzan |
An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: 2015 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015, Montreal, QC, Canada, June 15-18, 2015, pp. 1-7, 2015, IEEE, 978-1-4673-7501-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Weihua Zheng, Kenli Li 0001, Keqin Li 0001 |
Scaled Radix-2/8 Algorithm for Efficient Computation of Length-N=2m DFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 62(10), pp. 2492-2503, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Se-Hyu Choi, Keon-Jik Lee |
Enhancement of a modified radix-2 Montgomery modular multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 11(19), pp. 20140782, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Shaik A. Qadeer, Mohammed Zafar Ali Khan, Syed Abdul Sattar, Ahmed |
A Radix-2 DIT FFT with reduced arithmetic complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014, pp. 1892-1896, 2014, IEEE, 978-1-4799-3078-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Yu-Chih Huang, Wen-Chung Kuo, Ching-Nung Yang |
Data Hiding Based on Radix-2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaJCIS ![In: Ninth Asia Joint Conference on Information Security, AsiaJCIS 2014, Wuhan, China, September 3-5, 2014, pp. 170-174, 2014, IEEE Computer Society, 978-1-4799-5733-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Jun Han 0003, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng |
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(12), pp. 2325-2330, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Hai Huang, Liyi Xiao |
CORDIC Based Fast Radix-2 DCT Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Signal Process. Lett. ![In: IEEE Signal Process. Lett. 20(5), pp. 483-486, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Alexandru Amaricai, Oana Boncalo |
SRT radix-2 dividers with (5, 4) redundant representation of partial remainder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, pp. 1-5, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Hani H. Saleh, Baker S. Mohammad, Maher Maalouf |
A high-throughput, contention-free low-power, Radix-2 1k, 2k, 4k and 8k-point fast fourier transform engine using 28nm standard-cell process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2013, 26-28 March, 2013, Abu Dhabi, UAE, pp. 184-185, 2013, IEEE, 978-1-4673-6038-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Nishant Kumar Giri, Amitabha Sinha |
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 40(2), pp. 28-32, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | D. A. Montoya-Andrade, J. A. Rosendo-Macías, Antonio Gómez Expósito |
Efficient computation of the short-time DFT based on a modified radix-2 decimation-in-frequency algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Signal Process. ![In: Signal Process. 92(10), pp. 2525-2531, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Julio Villalba, Tomás Lang, Javier Hormigo |
Radix-2 Multioperand and Multiformat Streaming Online Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 61(6), pp. 790-803, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Vladimir Britanak |
New Recursive Fast Radix-2 Algorithm for the Modulated Complex Lapped Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 60(12), pp. 6703-6708, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Doru-Florin Chiper |
Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(5), pp. 297-301, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Nikolaos Polychronakis, Dionysios I. Reisis, Emmanouil Tsilis, Ioannis Zokas |
Conflict free, parallel memory access for radix-2 FFT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 973-976, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Zhen-guo Ma, Feng Yu 0003, Rui-feng Ge, Ze-ke Wang |
An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Zhejiang Univ. Sci. C ![In: J. Zhejiang Univ. Sci. C 12(4), pp. 323-329, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Mohamed Issad, Mohamed Anane, Nadjia Anane |
An optimised architecture for radix-2 Montgomery modular multiplication on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 3(4), pp. 175-183, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Doru-Florin Chiper |
Fast Radix-2 Algorithm for the Discrete Hartley Transform of Type II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Signal Process. Lett. ![In: IEEE Signal Process. Lett. 18(11), pp. 687-689, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Fahad Qureshi, Oscar Gustafsson |
Generation of all radix-2 fast Fourier transform algorithms using binary trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011, pp. 677-680, 2011, IEEE, 978-1-4577-0617-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Sidinei Ghissoni, Eduardo Costa 0001, José Monteiro 0001, Ricardo Reis 0001 |
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pp. 567-570, 2011, IEEE, 978-1-4577-1845-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Hyunseuk Yoo, Frédéric Guilloud, Ramesh Pyndiah |
Phase uncertainty algorithm on radix-2 for reducing the PAPR of multiple candidate OFDM system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WPMC ![In: 14th International Symposium on Wireless Personal Multimedia Communications, WPMC 2011, Brest, France, October 3-7, 2011, pp. 1-5, 2011, IEEE, 978-1-4577-1786-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
14 | Young-Ho Seo, Dong-Wook Kim |
A New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(2), pp. 201-208, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Kooroush Manochehri, Babak Sadeghiyan, Saadat Pourmozafari |
A modified radix-2 Montgomery modular multiplication with new recoding method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 7(8), pp. 513-519, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Sidinei Ghissoni, Eduardo Costa 0001, Cristiano Lazzari, José Monteiro 0001, Levent Aksoy, Ricardo Reis 0001 |
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 859-862, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa |
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 1083-1086, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Douglas Lyon |
The Discrete Fourier Transform, Part 2: Radix 2 FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Object Technol. ![In: J. Object Technol. 8(5), pp. 21-33, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Pere Martí-Puig |
Two Families of Radix-2 FFT Algorithms With Ordered Input and Output Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Signal Process. Lett. ![In: IEEE Signal Process. Lett. 16(2), pp. 65-68, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Omar Nibouche, Said Boussakta, Michael Darnell |
Pipeline Architectures for Radix-2 New Mersenne Number Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8), pp. 1668-1680, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Gautam A. Shah, Tejmal S. Rathore |
A New Position-Based Fast Radix-2 Algorithm for Computing the DHT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC3 ![In: Contemporary Computing - Second International Conference, IC3 2009, Noida, India, August 17-19, 2009. Proceedings, pp. 14-25, 2009, Springer, 978-3-642-03546-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Huazhong Shu, J. S. Wu, Lotfi Senhadji, Limin Luo |
Radix-2 algorithm for the fast computation of type-III 3-D discrete W transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Signal Process. ![In: Signal Process. 88(1), pp. 210-215, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos |
Addressing technique for parallel memory accessing in radix-2 FFT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 53-56, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|