Search results for "switches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Hagit Attiya, David Hay	The Inherent Queuing Delay of Parallel Packet Switches.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	ATM, Internetworking, packet-switching networks
29	Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi	A concurrent testing method for NoC switches.	DATE	2006	DBLP DOI BibTeX RDF
29	Deng Pan, Yuanyuan Yang 0001	Hardware Efficient Two Step Iterative Matching Algorithms for VOQ Switches.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
29	Wu Jigang, Thambipillai Srikanthan, Heiko Schröder	Efficient reconfigurable techniques for VLSI arrays with 6-port switches.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
29	Yashar Ganjali, Abtin Keshavarzian, Devavrat Shah	Cell switching versus packet switching in input-queued switches.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	cell switching, variable length packets, scheduling, packet switching
29	Marco Ajmone Marsan, Emilio Leonardi, Marco Mellia, Fabio Neri	On the stability of isolated and interconnected input-queueing switches under multiclass traffic.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
29	Assaf Avihoo, Danny Barash	Temperature and Mutation Switches in the Secondary Structure of Small RNAs.	CSB Workshops	2005	DBLP DOI BibTeX RDF
29	Edward Miller, Ran Libeskind-Hadas, D. Barnard, W. Chang, Kurt M. Dresner, W. M. Turner, Jeffrey R. K. Hartline	On the complexity of virtual topology design for multicasting in WDM trees with tap-and-continue and multicast-capable switches.	IEEE J. Sel. Areas Commun.	2004	DBLP DOI BibTeX RDF
29	Yossi Azar, Yossi Richter	An Improved Algorithm for CIOQ Switches.	ESA	2004	DBLP DOI BibTeX RDF
29	Morteza Fayyazi, David R. Kaeli, Waleed Meleis	Parallel Maximum Weight Bipartite Matching Algorithms for Scheduling in Input-Queued Switches.	IPDPS	2004	DBLP DOI BibTeX RDF
29	Hagit Attiya, David Hay	The inherent queuing delay of parallel packet switches.	SPAA	2004	DBLP DOI BibTeX RDF	leaky-bucket traffic, load balancing, packet switching, clos networks, queuing delay, delay jitter, inverse multiplexing
29	Nan Ni, Laxmi N. Bhuyan	Fair Scheduling for Input Buffered Switches.	Clust. Comput.	2003	DBLP DOI BibTeX RDF	input buffered switch, scheduling, switching, fair bandwidth allocation, multicast switching
29	Shridhar Mubaraq Mishra, A. Guruprasad, Chun Feng Hu, Pramod K. Pandey, Ming Hung	Wire-speed traffic management in Ethernet switches.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
29	Sayed Vahid Azhari, Nasser Yazdani, Ali Mohammad Zareh Bidoki	Providing Delay Guarantee in Input Queued Switches: A Comparative Analysis of Scheduling Algorithms.	ICOIN	2003	DBLP DOI BibTeX RDF
29	Vladimir V. Anisimov	Averaging in Markov Models with Fast Markov Switches and Applications to Queueing Models.	Ann. Oper. Res.	2002	DBLP DOI BibTeX RDF	averaging principle, switching process, random environment, Markov process, queueing system, stationary distribution
29	Pedro Javier García, M. D. Mora, Francisco José Alfaro, José L. Sánchez 0002, José Flich	Evaluation of Alternative Arbitration Policies for Myrinet Switches.	IPDPS	2002	DBLP DOI BibTeX RDF	Performance, Myrinet, Arbitration, NOWs
29	Andrea Francini, Fabio M. Chiussi	Integrated Provision of QoS Guarantees to Unicast and Multicast Traffic in Packet Switches.	IWDC	2001	DBLP DOI BibTeX RDF
29	Ingebjørg Theiss, Olav Lysne	Deadlock Avoidance for Wormhole Based Switches.	Euro-Par	2000	DBLP DOI BibTeX RDF
29	Rossano Gaeta, Marco Ajmone Marsan	SWN Analysis and Simulation of Large Knockout ATM Switches.	ICATPN	1998	DBLP DOI BibTeX RDF
29	Junjie Wang, Khaled Ben Letaief, Mounir Hamdi, Xi-Ren Cao	Efficient Estimation of Cell Loss and Cell Delay of Nonblocking ATM Switches.	LCN	1997	DBLP DOI BibTeX RDF
29	Marius Evers, Po-Yung Chang, Yale N. Patt	Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches.	ISCA	1996	DBLP DOI BibTeX RDF	branch prediction, speculative execution, superscalar, context switch
29	Amr Elsaadany, Mukesh Singhal, Ming T. Liu	Performance study of buffering within switches in local area networks.	ICCCN	1995	DBLP DOI BibTeX RDF	switch performance, network transfer rates, output ports, input ports, LAN performance, multimedia, delay, throughput, local area networks, local area networks, buffering, queueing model, buffer size, performance study, output buffer, packet loss rate
29	Hamid Z. Fardi	Simulation and modeling of p-n-p-n optical switches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
27	Yuanyuan Yang 0001, Jianchao Wang	Cost-Effective Designs of WDM Optical Interconnects.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	multicast, permutation, network architectures, optical interconnects, Wavelength-division-multiplexing (WDM), optical switches, wavelength conversion, multistage networks, sparse crossbars
27	Sudarshan Banerjee, Nikil D. Dutt	FIFO power optimization for on-chip networks.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	wide flits, low power design, shared memory, switches, FIFO, on-chip networks
27	Itsuo Takanami, Tadayoshi Horita	A built-in self-reconfigurable scheme for 3D mesh arrays.	ISPAN	1997	DBLP DOI BibTeX RDF	fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures
27	Yeimkuan Chang	Partitionability of the Multistage Interconnection Networks.	IPPS	1996	DBLP DOI BibTeX RDF	network partitionability, physically independent subsystems, communication interference, permutation functions, mapping scheme, hypercube structure, fault tolerance, parallel architectures, fault tolerant computing, hypercube networks, multistage interconnection networks, multistage interconnection networks, MIN, switches
27	Verna J. Friesen, Johnny W. Wong	A case study in local area migration to ATM.	ICCCN	1995	DBLP DOI BibTeX RDF	local area migration, local ATM, ATM switched internetwork, switching hubs, ATM-equipped end devices, ATM backbone, ATM adaptation, campus environment, network components, end-to-end loss, asynchronous transfer mode, local area network, Ethernets, simulation results, routers, servers, simulation model, multiplexers, network performance, ATM switches, end-to-end delay, network configurations, clients
27	Wilbert H. F. J. Körver	A universal formalization of the effects of threshold voltages for discrete switch-level circuit models.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits
27	Kemal Efe	The Crossed Cube Architecture for Parallel Computation.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	self routing network, crossed cube architecture, distributed routingalgorithm, high connectivity, SIMD algorithms, CQ/sub n/ architecture, dynamicreconfiguration, embedding properties, parallel algorithms, parallel computation, parallel architectures, regularity, symmetry, switches, multiprocessorinterconnection networks, massively parallel architectures, hypercube algorithms, recursive structure
27	Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty	Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches.	ETS	2011	DBLP DOI BibTeX RDF	Multi-Mode Power Switches, DFT for Multicore Chips, Static Power Management, Testing, Voltage-Control Oscillator
27	George F. Georgakopoulos	Buffered cross-bar switches, revisited: design steps, proofs and simulations towards optimal rate and minimum buffer memory.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	buffered crossbar switches, packet switching, strategic games
27	Rajaa S. Shindi, Shaun Cooper	Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated.	SIGAda	2006	DBLP DOI BibTeX RDF	sim-alpha, cache, cpu, context switches, processor simulators
27	Emilio Leonardi, Marco Mellia, Fabio Neri, Marco Ajmone Marsan	On the stability of input-queued switches with speed-up.	IEEE/ACM Trans. Netw.	2001	DBLP DOI BibTeX RDF	input buffered switches, stability, scheduling algorithm, Lyapunov methods
27	Giuseppe Ascia, Vincenzo Catania, Daniela Panno	An adaptive fuzzy threshold scheme for high performance shared-memory switches.	SAC	2001	DBLP DOI BibTeX RDF	fuzzy logic, shared-memory, buffer management, ATM switches
27	Biplab Sikdar 0001, D. Manjunath	Queueing analysis of scheduling policies in copy networks of space-based multicast packet switches.	IEEE/ACM Trans. Netw.	2000	DBLP DOI BibTeX RDF	copy networks, scheduling algorithms, queueing analysis, multicast switches
27	Maher Ali	Assignment of Multicast Switches in Optical Networks.	LCN	2000	DBLP DOI BibTeX RDF	telecommunication switching, optimal placement, multicast nodes, famous warehouse allocation heuristic, simulated annealing, simulated annealing, network topology, optical networks, multicast communication, blocking probability, all-optical networks, optical fibre networks, ADD, placement problem, multicast switches
27	Supriya Sharma, Yannis Viniotis	Optimal buffer management policies for shared-buffer ATM switches.	IEEE/ACM Trans. Netw.	1999	DBLP DOI BibTeX RDF	optimal policies, buffer management, ATM switches
27	Krishna Kant 0001	Performance of internal overload controls in large switches.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	internal overload control performance, large switches, switch sizes, call capacity, voice circuits, overload performance, network integrity, peripheral scanning schemes, scheduling, performance evaluation, virtual machines, logic CAD, circuit analysis computing, simulation model, service integrity, buffer sizes, switching circuits
27	Yuval Tamir, Hsin-Chou Chi	Symmetric Crossbar Arbiters for VLSI Communication Switches.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	VLSI communication switches, symmetric crossbar arbiters, multistage interconnectionnetwork, switch arbitration policy, worst-case latency, circuitsimulation, performance evaluation, VLSI, circuit analysis computing, network simulations, critical path, multiprocessorinterconnection networks, system clock
27	Sun-Yuan Kung, Shiann-Ning Jean, Chih-Wei Jim Chang	Fault-Tolerant Array Processors Using Single-Track Switches.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fabrication time processing, fault tolerant array processors, single-track switches, array grid model, reconfigurability theorem, run-time processing, propagation time, parallel processing, graph theory, graph theory, fault tolerant computing, yield enhancement
24	Oliver Brdiczka	From documents to tasks: deriving user tasks from document usage patterns.	IUI	2010	DBLP DOI BibTeX RDF	automatic task identification, user task modeling, document clustering
24	Minlan Yu, Jennifer Rexford, Michael J. Freedman, Jia Wang 0001	Scalable flow-based networking with DIFANE.	SIGCOMM	2010	DBLP DOI BibTeX RDF	scalability, access control, network architecture, openflow
24	Mustafa Altun, Marc D. Riedel	Lattice-based computation of Boolean functions.	DAC	2010	DBLP DOI BibTeX RDF	lattice duality, Boolean functions, lattices, switching circuits
24	Mohamed Faouzi Atig, Ahmed Bouajjani, Shaz Qadeer	Context-Bounded Analysis for Concurrent Programs with Dynamic Creation of Threads.	TACAS	2009	DBLP DOI BibTeX RDF
24	Hongbing Fan, Yu-Liang Wu	A New Approach for Rearrangeable Multicast Switching Networks.	COCOA	2009	DBLP DOI BibTeX RDF
24	Giuliano Casale, Amir S. Kalbasi, Diwakar Krishnamurthy, Jerry Rolia	Automatic Stress Testing of Multi-tier Systems by Dynamic Bottleneck Switch Generation.	Middleware	2009	DBLP DOI BibTeX RDF	bottleneck switch, performance, Benchmarking, burstiness
24	Satoshi Yamada, Shigeru Kusakabe	Effect of context aware scheduler on TLB.	IPDPS	2008	DBLP DOI BibTeX RDF
24	Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun	Power switch characterization for fine-grained dynamic voltage scaling.	ICCD	2008	DBLP DOI BibTeX RDF
24	Yarallah Koolivand, Seyed Morteza Alavi, Omid Shoaei	New technique in design of active rf cmos mixers for low flicker noise and high conversion gain.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	1.cmos mixer, direct conversion receiver, flicker noise, sub-threshold, ota, noise figure
24	Paul Congdon, Matthew K. Farrens, Prasant Mohapatra	Packet prediction for speculative cut-through switching.	ANCS	2008	DBLP DOI BibTeX RDF	cut-through, ethernet switching, packet prediction, speculation
24	Madanlal Musuvathi, Shaz Qadeer	Iterative context bounding for systematic testing of multithreaded programs.	PLDI	2007	DBLP DOI BibTeX RDF	context-bounding, model checking, concurrency, software testing, multithreading, partial-order reduction, shared-memory programs
24	Pradipta Patra, Amit Patra, Debaprasad Kastha	On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology.	VLSI Design	2007	DBLP DOI BibTeX RDF
24	Hyoung-Il Lee, Seung-Woo Seo	Matching output queueing with a multiple input/output-queued switch.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	combined input/output-queued (CIOQ) switch, multiple input/output-queued (MIOQ) switch, output queueing emulation, parallel switching architecture
24	Marcelino Minero-Muñoz, Vicente Alarcón Aquino	A Hierarchical Approach for Modelling an MPLS Network Using VHDL.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
24	Shuo-Yen Robert Li, Xuesong Tan	Theory on Switch Preservation under 2-stage Interconnection.	PDCAT	2005	DBLP DOI BibTeX RDF
24	Bin Liu, Fabrizio Lombardi, Nohpill Park, Minsu Choi	Testing Layered Interconnection Networks.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
24	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	FPGA, low power, interconnect, encoding
24	Rohini Krishnan, José Pineda de Gyvez	Low Energy Switch Block For FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
24	Sundar Iyer, Nick McKeown	Analysis of the parallel packet switch architecture.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	output queueing, load balancing, packet switch, Clos network, inverse multiplexing
24	Neil J. Gunther, Kenneth J. Christensen, Kenji Yoshigoe	Characterization of the Burst Stabilization Protocol for the RR/RR CICQ Switch.	LCN	2003	DBLP DOI BibTeX RDF
24	Rafael Casado, Aurelio Bermúdez, José Duato, Francisco J. Quiles 0001, José L. Sánchez 0002	A Protocol for Deadlock-Free Dynamic Reconfiguration in High-Speed Local Area Networks.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	Interconnection networks, dynamic reconfiguration, deadlock avoidance, irregular topologies, system availability
24	Rajeev Sivaram, Ram Kesavan, Dhabaleswar K. Panda 0001, Craig B. Stunkel	Architectural Support for Efficient Multicasting in Irregular Networks.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	cut-through routing, performance evaluation, multicast, broadcast, collective communication, Parallel computer architecture, irregular networks, switch-based networks
24	Rafael Casado, Aurelio Bermúdez, Francisco J. Quiles 0001, José L. Sánchez 0002, José Duato	Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks.	HPCA	2000	DBLP DOI BibTeX RDF
24	Der-Rong Din, Shian-Shyong Tseng, Mon-Fong Jiang	Genetic Algorithm for Extended Cell Assignment Problem in Wireless ATM Network.	ASIAN	2000	DBLP DOI BibTeX RDF
24	Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu 0001	Routing for symmetric FPGAs and FPICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
24	Abdulraouf Y. Al-Hallaq	Robustness of the destination tag based routing algorithm for the control of unique path networks (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
23	Hong Cheng, Yaohui Jin, Yu Gao, Ying Di Yu, Weisheng Hu, Nirwan Ansari	Per-Flow Re-Sequencing in Load-Balanced Switches by Using Dynamic Mailbox Sharing.	ICC	2008	DBLP DOI BibTeX RDF
23	Roberto Gaudino, Guido A. Gavilanes Castillo, Fabio Neri, Jorge M. Finochietto	Simple Optical Fabrics for Scalable Terabit Packet Switches.	ICC	2008	DBLP DOI BibTeX RDF
23	Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wladek Olesinski, Hans Eberle, Nils Gura	Backlog Aware Scheduling for Large Buffered Crossbar Switches.	ICC	2008	DBLP DOI BibTeX RDF
23	Benjamin Yolken, Nicholas Bambos	Power Management of Packet Switches via Differentiated Delay Targets.	ICC	2008	DBLP DOI BibTeX RDF
23	Minje Jun, Sungjoo Yoo, Eui-Young Chung	Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches.	ASP-DAC	2008	DBLP DOI BibTeX RDF
23	Alexander Kesselman, Kirill Kogan, Michael Segal 0001	Improved Competitive Performance Bounds for CIOQ Switches.	ESA	2008	DBLP DOI BibTeX RDF
23	Björn Andersson	Schedulability analysis of generalized multiframe traffic on multihop-networks comprising software-implemented ethernet-switches.	IPDPS	2008	DBLP DOI BibTeX RDF
23	Choudhury A. Al Sayeed, Dewan Tanvir Ahmed, Akbar Ghaffar Pour Rahbar	Hybrid Maximal Matching for Input Buffered Crossbar Switches.	CNSR	2007	DBLP DOI BibTeX RDF
23	Mark B. Colton, John M. Hollerbach	Reality-Based Haptic Force Models of Buttons and Switches.	ICRA	2007	DBLP DOI BibTeX RDF
23	Jaan Raik, Raimund Ubar, Vineeth Govind	Test Configurations for Diagnosing Faulty Links in NoC Switches.	ETS	2007	DBLP DOI BibTeX RDF
23	Alessandra Scicchitano, Andrea Bianco, Paolo Giaccone, Emilio Leonardi, Enrico Schiattarella	Distributed Scheduling in Input Queued Switches.	ICC	2007	DBLP DOI BibTeX RDF
23	Christopher M. Twigg, Jordan D. Gray, Paul E. Hasler	Programmable Floating Gate FPAA Switches Are Not Dead Weight.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Christopher M. Twigg, Paul E. Hasler	Programmable Conductance Switches for FPAAs.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Emmanuel Simeu, Salvador Mir, R. Kherreddine, Hoang Nam Nguyen	Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches.	IOLTS	2007	DBLP DOI BibTeX RDF	RF MEMS, capacitive switch, envelope detection, transition time, Online testing, recursive estimation
23	Andreas Schweizer, Tarith Devadason, John F. Siliquini	A Markov Model for Preference List Sizes in Combined Input Output Queued Switches with Stable Matching Algorithms.	ICON	2007	DBLP DOI BibTeX RDF
23	Wladek Olesinski, Nils Gura, Hans Eberle, Andres Mejia	Low-latency scheduling in large switches.	ANCS	2007	DBLP DOI BibTeX RDF	scheduling, switching, low latency, arbiter
23	Hung Q. Ngo 0001, Dazhen Pan, Chunming Qiao	Constructions and analyses of nonblocking WDM switches based on arrayed waveguide grating and limited wavelength conversion.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	limited-range wavelength converters, non-blocking WDM cross-connects
23	Hiroaki Harai, Masayuki Murata 0001	High-speed buffer management for 40 Gb/s-based photonic packet switches.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	photonic packet switching, variable-length optical packet, parallel processing, buffer management, pipeline processing
23	Hongyun Zheng, Yongxiang Zhao, Changjia Chen	Design and Implementation of Switches in Network Simulator (ns2).	ICICIC (1)	2006	DBLP DOI BibTeX RDF
23	Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen	On a design of crossroad switches for low-power on-chip communication architectures.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Hagit Attiya, David Hay, Isaac Keslassy	Packet-mode emulation of output-queued switches.	SPAA	2006	DBLP DOI BibTeX RDF	CIOQ switch, output-queued, packet-mode scheduling, switch emulation, packet switching, queuing delay
23	Gaspar Mora, José Flich, José Duato, Pedro López 0001, Elvira Baydal, Olav Lysne	Towards an efficient switch architecture for high-radix switches.	ANCS	2006	DBLP DOI BibTeX RDF	arbiter efficiency, partitioned crossbar, switch organization
23	Ted H. Szymanski, Honglin Wu, Amir Gourgy	Power complexity of multiplexer-based optoelectronic crossbar switches.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
23	Xiaohong Jiang 0001, Pin-Han Ho, Susumu Horiguchi	Performance Modeling for All-Optical Photonic Switches Based on the Vertical Stacking of Banyan Network Structures.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
23	Jonathan Lueke, Noor Al Quddus, Walied A. Moussa, Aman Chahal	A Parametric Study of Thermal Effects on the Reliability of RF MEMS Switches.	ICMENS	2005	DBLP DOI BibTeX RDF
23	Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis	Exact lower bound for the number of switches in series to implement a combinational logic cell.	ICCD	2005	DBLP DOI BibTeX RDF
23	Cheng-Shang Chang, Duan-Shin Lee	Quasi-circuit switching and quasi-circuit switches.	ITRE	2005	DBLP DOI BibTeX RDF
23	Hagit Attiya, David Hay	Randomization does not reduce the average delay in parallel packet switches.	SPAA	2005	DBLP DOI BibTeX RDF	oblivious adversary, load balancing, packet switching, randomization, clos networks, queuing delay, inverse multiplexing, adaptive adversary
23	Jingsong Xie, Michael G. Pecht	Contact discontinuity modeling of electromechanical switches.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
23	Sang-Ho Lee, Dong Ryeol Shin, Hee Yong Youn	Weighted Fair Scheduling Algorithm for QoS of Input-Queued Switches.	NPC	2004	DBLP DOI BibTeX RDF
23	Laixian Peng, Chang Tian, Shaoren Zheng	iRGRR: A Fast Scheduling Scheme with Less Control Messages for Scalable Crossbar Switches.	HSNMC	2004	DBLP DOI BibTeX RDF
23	Andreas Gothenberg, Hannu Tenhunen	Performance analysis of sampling switches in voltage and frequency domains using Volterra series.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
23	Deng Pan, Yuanyuan Yang	FIFO Based Multicast Scheduling Algorithm for VOQ Packet Switches.	ICPP	2004	DBLP DOI BibTeX RDF