Search results for "DSD"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Sergio Saponara, Nicola E. L'Insalata, Tony Bacchillone, Esa Petri, Iacopo Del Corona, Luca Fanucci	Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications.	DSD	2008	DBLP DOI BibTeX RDF
1	Ali Jahanian 0001, Morteza Saheb Zamani	Performance and Timing Yield Enhancement using Highway-on-Chip Planning.	DSD	2008	DBLP DOI BibTeX RDF
1	Martino Ruggiero, Michele Lombardi 0001, Michela Milano, Luca Benini	Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor.	DSD	2008	DBLP DOI BibTeX RDF
1	Andrea Alimonda, Andrea Acquaviva, Salvatore Carta	Temperature and Leakage Aware Power Control for Embedded Streaming Applications.	DSD	2008	DBLP DOI BibTeX RDF
1	Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani	Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics.	DSD	2008	DBLP DOI BibTeX RDF
1	Heinrich Theodor Vierhaus, René Kothe	Embedded Diagnostic Logic Test Exploiting Regularity.	DSD	2008	DBLP DOI BibTeX RDF
1	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	A Modular Approach to Model Heterogeneous MPSoC at Cycle Level.	DSD	2008	DBLP DOI BibTeX RDF
1	Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti	High Performance Computing for Embedded System Design: A Case Study.	DSD	2008	DBLP DOI BibTeX RDF
1	Markus Winter 0002, Gerhard P. Fettweis	A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips.	DSD	2008	DBLP DOI BibTeX RDF
1	Joseph C. Libby, Farnaz Gharibian, Kenneth B. Kent	Automatic Identification of Parallelism in Handel-C.	DSD	2008	DBLP DOI BibTeX RDF
1	Roberto Alesii, Fabio Graziosi, Luigi Pomante, Claudia Rinaldi	Exploiting WSN for Audio Surveillance Applications: The VoWSN Approach.	DSD	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Ding G. Guo, Francis Eng Hock Tay, Lin Xu, L. M. Yu, Myo Naing Nyan, F. W. Chong, K. L. Yap, B. Xu	A Long-term Wearable Vital Signs Monitoring System using BSN.	DSD	2008	DBLP DOI BibTeX RDF
1	Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi	An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty.	DSD	2008	DBLP DOI BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani, Roberto Cordone	On Projecting Sums of Products.	DSD	2008	DBLP DOI BibTeX RDF
1	Michele Magno, Davide Brunelli, Piero Zappi, Luca Benini	A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance.	DSD	2008	DBLP DOI BibTeX RDF
1	Simone Secchi, Francesca Palumbo, Danilo Pani, Luigi Raffo	A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching.	DSD	2008	DBLP DOI BibTeX RDF
1	Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration.	DSD	2008	DBLP DOI BibTeX RDF
1	Itziar Marín, Aitzol Zuloaga, Iker Losada	A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks.	DSD	2008	DBLP DOI BibTeX RDF
1	Giovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari, M. Nobis	An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal Images.	DSD	2008	DBLP DOI BibTeX RDF
1	Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit, Rui Dai	IRIS: A Firmware Design Methodology for SIMD Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Valentina Bianchi, Ferdinando Grossi, Guido Matrella, Ilaria De Munari, Paolo Ciampolini	A Wireless Sensor Platform for Assistive Technology Applications.	DSD	2008	DBLP DOI BibTeX RDF
1	José Luis Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares	Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization.	DSD	2008	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Dimitris Bakalis	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.	DSD	2008	DBLP DOI BibTeX RDF
1	Sébastien Bilavarn, Cécile Belleudy, Michel Auguin, T. Dupont, Anne-Marie Fouilliart	Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations.	DSD	2008	DBLP DOI BibTeX RDF
1	Maurizio Tranchero, Leonardo Maria Reyneri	Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools.	DSD	2008	DBLP DOI BibTeX RDF
1	François Charot, Christophe Wolinski, Nicolas Fau, François Hamon	A Parallel and Modular Architecture for 802.16e LDPC Codes.	DSD	2008	DBLP DOI BibTeX RDF
1	Daniel Piso Fernandez, Javier D. Bruguera	A New Rounding Algorithm for Variable Latency Division and Square Root Implementations.	DSD	2008	DBLP DOI BibTeX RDF
1	Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler	Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.	DSD	2008	DBLP DOI BibTeX RDF
1	Pawel Gburzynski, Bozena Kaminska, Ashikur Rahman	Reliable Data Transmission over Simple Wireless Channels: A Case Study.	DSD	2008	DBLP DOI BibTeX RDF
1	Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman	Power Conscious RTL Test Scheduling.	DSD	2008	DBLP DOI BibTeX RDF
1	Silvia Franchini, Antonio Gentile, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile	An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra.	DSD	2008	DBLP DOI BibTeX RDF
1	Andrea Marongiu, Luca Benini, Andrea Acquaviva, Andrea Bartolini	Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology.	DSD	2008	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi	Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.	DSD	2008	DBLP DOI BibTeX RDF
1	Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao	Programmable Numerical Function Generators for Two-Variable Functions.	DSD	2008	DBLP DOI BibTeX RDF
1	Abdalkarim Awad, Rodrigo Nebel, Reinhard German, Falko Dressler	On the Need for Passive Monitoring in Sensor Networks.	DSD	2008	DBLP DOI BibTeX RDF
1	Gianmaria Collazuol, S. Galeotti, E. Imbergamo, G. Lamanna, Guido Magazzù, M. Sozzi	Fast FPGA-based Trigger and Data Acquisition System for the CERN Experiment NA62: Architecture and Algorithms.	DSD	2008	DBLP DOI BibTeX RDF
1	Marcello Mura, Mariagiovanna Sami	Code Generation from Statecharts: Simulation of Wireless Sensor Networks.	DSD	2008	DBLP DOI BibTeX RDF
1	Muhammad Najam-ul-Islam, Rizwan Rasheed, Renaud Pacalet, Raymond Knopp, Karim Khalfallah	Flexible Baseband Architectures for Future Wireless Systems.	DSD	2008	DBLP DOI BibTeX RDF
1	Luca Bassi, Enrico Boni, Andrea Cellai, Alessandro Dallai, Francesco Guidi, Stefano Ricci, Piero Tortoli	A Novel Digital Ultrasound System for Experimental Research Activities.	DSD	2008	DBLP DOI BibTeX RDF
1	Stefano Recchi, Maurizio Persichitti, Massimo Conti	WirelessUSB - Performance Analysis of an Embedded System in a Peer-to-Peer Application.	DSD	2008	DBLP DOI BibTeX RDF
1	Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu	A Hardware Design for Camera-Based Power Management of Computer Monitor.	DSD	2008	DBLP DOI BibTeX RDF
1	Paola Baldrighi, Marco Castellano, Carla Vacchi, Davide Canina, Paolo Golzi, Gianni Ferrante	Digital Nuclear Magnetic Resonance Acquisition Channel.	DSD	2008	DBLP DOI BibTeX RDF
1	Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi	A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits.	DSD	2008	DBLP DOI BibTeX RDF
1	Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.	DSD	2008	DBLP DOI BibTeX RDF
1	Takashi Kambe, Makoto Saituji	A Variable Length Vector Pipeline Architecture Design Methodology.	DSD	2008	DBLP DOI BibTeX RDF
1	Tommaso Cecchini, Francesco Sechi, Luca Bacciarelli, Luca Mostardini, Francesco Battini, Luca Fanucci, Marco De Marinis	Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication.	DSD	2008	DBLP DOI BibTeX RDF
1	Josef Strnadel	TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path.	DSD	2008	DBLP DOI BibTeX RDF
1	Stefano Tennina, Marco Di Renzo, Fabio Graziosi, Fortunato Santucci	Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor Networks.	DSD	2008	DBLP DOI BibTeX RDF
1	Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich	Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.	DSD	2008	DBLP DOI BibTeX RDF
1	Demid Borodin, Ben H. H. Juurlink	A Low-Cost Cache Coherence Verification Method for Snooping Systems.	DSD	2008	DBLP DOI BibTeX RDF
1	Roderick R. Colenbrander, Arjen S. Damstra, C. Wim Korevaar, C. A. Verhaar, Albert Molderink	Co-design and Implementation of the H.264/AVC Motion Estimation Algorithm Using Co-simulation.	DSD	2008	DBLP DOI BibTeX RDF
1	Scott Miller, Ambrose Chu, Mihai Sima, Michael McGuire	VLSI Implementation of a Cryptography-Oriented Reconfigurable Array.	DSD	2008	DBLP DOI BibTeX RDF
1	Zubair Nawaz, Zaid Al-Ars, Koen Bertels, Mudassir Shabbir	Acceleration of Smith-Waterman using Recursive Variable Expansion.	DSD	2008	DBLP DOI BibTeX RDF
1	Petr Fiser, Pavel Kubalík, Hana Kubátová	An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA.	DSD	2008	DBLP DOI BibTeX RDF
1	Andrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini	Design of an Ultra Low-Power RFID Baseband Processor Featuring an AES Cryptography Engine.	DSD	2008	DBLP DOI BibTeX RDF
1	Gianni Antichi, Andrea Di Pietro, Domenico Ficara, Stefano Giordano, Gregorio Procissi, Fabio Vitucci	Design of a High Performance Traffic Generator on Network Processor.	DSD	2008	DBLP DOI BibTeX RDF
1	Abdalkarim Awad, Thorsten Frunzke, Falko Dressler	Adaptive Distance Estimation and Localization in WSN using RSSI Measures.	DSD	2007	DBLP DOI BibTeX RDF
1	Jesús Barba, Fernando Rincón, Francisco Moya, Felix Jesús Villanueva, David Villa, Julio Dondo, Juan Carlos López 0001	OOCE: Object-Oriented Communication Engine for SoC Design.	DSD	2007	DBLP DOI BibTeX RDF
1	Falk Salewski, Adam Taylor	Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative Survey.	DSD	2007	DBLP DOI BibTeX RDF
1	Moonvin Song, Sang Hoon Hong, Yunmo Chung	Reducing the Overhead of Real-Time Operating System through Reconfigurable Hardware.	DSD	2007	DBLP DOI BibTeX RDF
1	Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo	Design and Implementation of a 90nm Low bit-rate Image Compression Core.	DSD	2007	DBLP DOI BibTeX RDF
1	Santosh Ghosh, Monjur Alam, Indranil Sengupta 0001, Dipanwita Roy Chowdhury	A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography.	DSD	2007	DBLP DOI BibTeX RDF
1	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Merge Logic for Clustered Multithreaded VLIW Processors.	DSD	2007	DBLP DOI BibTeX RDF
1	Erno Salminen, Ari Kulmala, Timo D. Hämäläinen	On network-on-chip comparison.	DSD	2007	DBLP DOI BibTeX RDF
1	Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka	Online Protocol Testing for FPGA Based Fault Tolerant Systems.	DSD	2007	DBLP DOI BibTeX RDF
1	Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar	Hybrid BIST Optimization Using Reseeding and Test Set Compaction.	DSD	2007	DBLP DOI BibTeX RDF
1	Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan	Energy Based Design Space Exploration of Multiprocessor VLIW Architectures.	DSD	2007	DBLP DOI BibTeX RDF
1	Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek	Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties.	DSD	2007	DBLP DOI BibTeX RDF
1	Paolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo	On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.	DSD	2007	DBLP DOI BibTeX RDF
1	Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo	FPGA-based Road Traffic Videodetector.	DSD	2007	DBLP DOI BibTeX RDF
1	Seungjae Lee 0001, Changhwa Kim, Sangkyung Kim	A Proposal of New Join Operators for Sensor Network Databases.	DSD	2007	DBLP DOI BibTeX RDF
1	Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo	Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.	DSD	2007	DBLP DOI BibTeX RDF
1	Hosna Jabbari, Jon C. Muzio, Lin Sun	A New Class of Cellular Automata.	DSD	2007	DBLP DOI BibTeX RDF
1	Mohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi	Design and Implementation of a 50MHZ DXT CoProcessor.	DSD	2007	DBLP DOI BibTeX RDF
1	Youssef Serrestou, Vincent Beroulle, Chantal Robach	Functional Verification of RTL Designs driven by Mutation Testing metrics.	DSD	2007	DBLP DOI BibTeX RDF
1	Federico Baronti, Francesco Lenzi, Roberto Roncella, Roberto Saletti	A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems.	DSD	2007	DBLP DOI BibTeX RDF
1	Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai	Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.	DSD	2007	DBLP DOI BibTeX RDF
1	Matthew Marshall, Gordon Russell 0002	A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor.	DSD	2007	DBLP DOI BibTeX RDF
1	Kalle Holma, Mikko Setälä, Erno Salminen, Timo D. Hämäläinen	Evaluating the Model Accuracy in Automated Design Space Exploration.	DSD	2007	DBLP DOI BibTeX RDF
1	Gianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola	Application-Specific Topology Design Customization for STNoC.	DSD	2007	DBLP DOI BibTeX RDF
1	Richard Ruzicka, Josef Strnadel	Test Controller Synthesis Constrained by Circuit Testability Analysis.	DSD	2007	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos	An Efficient BIST Scheme for Non-Restoring Array Dividers.	DSD	2007	DBLP DOI BibTeX RDF
1	Ismail Assayad, Sergio Yovine	P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications.	DSD	2007	DBLP DOI BibTeX RDF
1	Alei Liang, Kejia Liu, Xiaoyong Li, Haibing Guan	FATTY: A Reliable FAT File System.	DSD	2007	DBLP DOI BibTeX RDF
1	Petr Fiser	Pseudo-Random Pattern Generator Design for Column-Matching BIST.	DSD	2007	DBLP DOI BibTeX RDF
1	Joseph C. Libby, Kenneth B. Kent	An Embedded Implementation of the Microsoft Common Language Infrastructure.	DSD	2007	DBLP DOI BibTeX RDF
1	Agustin Barberis, Leonardo Barboni, Maurizio Valle	Evaluating Energy Consumption in Wireless Sensor Networks Applications.	DSD	2007	DBLP DOI BibTeX RDF
1	Daniele Audino, Federico Baronti, Andrea Lazzeri, Roberto Roncella, Roberto Saletti	FPGA/DSP-based Configurable Multi-Channel Counter.	DSD	2007	DBLP DOI BibTeX RDF
1		Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany	DSD	2007	DBLP BibTeX RDF
1	Matti Eteläperä, Janne Vatjus Anttila, Juha Pekka Soinimen	Architecture Exploration of 3D Video Recorder Using Virtual Platform Models.	DSD	2007	DBLP DOI BibTeX RDF
1	Esra Sahin, Ilker Hamzaoglu	An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding.	DSD	2007	DBLP DOI BibTeX RDF
1	Chiyuan Ma, Shuming Chen	A DRAM Precharge Policy Based on Address Analysis.	DSD	2007	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi	On-Chip Verification of NoCs Using Assertion Processors.	DSD	2007	DBLP DOI BibTeX RDF
1	Arno Moonen, Marco Bekooij, René van den Berg, Jef L. van Meerbergen	Decoupling of Computation and Communication with a Communication Assist.	DSD	2007	DBLP DOI BibTeX RDF
1	Kolin Paul, Joël Porquet, Josep Llosa	Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.	DSD	2007	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi	Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.	DSD	2007	DBLP DOI BibTeX RDF
1	Federico Baronti, Roberto Roncella, Roberto Saletti, Paolo D'Abramo, L. Di Piro, H. Fabian, M. Giardi	The importance of At-Speed Scan Testing: an industrial experience.	DSD	2007	DBLP DOI BibTeX RDF
1	Tsutomu Sasao, Munehiro Matsuura	An Implementation of an Address Generator Using Hash Memories.	DSD	2007	DBLP DOI BibTeX RDF
1	Eugene Goldberg, Kanupriya Gulati	On Complexity of Internal and External Equivalence Checking.	DSD	2007	DBLP DOI BibTeX RDF

Publications at "DSD"( http://dblp.L3S.de/Venues/DSD )