Search results for "Retiming"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Dimitrios Kagaris, Spyros Tragoudas	A fast algorithm for minimizing FPGA combinational and sequential modules.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	field programmable gate arrays, retiming
17	Peichen Pan, C. L. Liu 0001	Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance.	FPGA	1996	DBLP DOI BibTeX RDF	FPGAs, sequential circuits, retiming, technology mapping, look-up table, logic replication, clock period
17	Pierre-Yves Calland, Alain Darte, Yves Robert	A New Guaranteed Heuristic for the Software Pipelining Problem.	International Conference on Supercomputing	1996	DBLP DOI BibTeX RDF	circuit retiming, guaranteed heuristic, software pipelining, list scheduling, cyclic scheduling
17	Nelson L. Passos, Edwin Hsing-Mean Sha	Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications.	ICCAD	1995	DBLP DOI BibTeX RDF	Scheduling Resource constraints Multi-dimensional Retiming Nested loops
11	Christopher Kennedy, Arash Reyhani-Masoleh	High-speed CRC computations using improved state-space transformations.	EIT	2009	DBLP DOI BibTeX RDF
11	Jennifer M. Davoren	Epsilon-Tubes and Generalized Skorokhod Metrics for Hybrid Paths Spaces.	HSCC	2009	DBLP DOI BibTeX RDF
11	Hui Liu 0006, Zili Shao, Meng Wang 0005, Ping Chen	Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip.	ECRTS	2008	DBLP DOI BibTeX RDF
11	Xinmiao Zhang, Jiangli Zhu	Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down.	SiPS	2008	DBLP DOI BibTeX RDF
11	Timothy Kam, Michael Kishinevsky, Jordi Cortadella, Marc Galceran Oms	Correct-by-construction microarchitectural pipelining.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony	Invariant-Strengthened Elimination of Dependent State Elements.	FMCAD	2008	DBLP DOI BibTeX RDF
11	Shahid Rizwan	Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding.	VLSI Design	2008	DBLP DOI BibTeX RDF
11	Kenneth Eguro, Scott Hauck	Enhancing timing-driven FPGA placement for pipelined netlists.	DAC	2008	DBLP DOI BibTeX RDF	timing-driven, FPGA, simulated annealing, pipelined, placement
11	Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001	FPGA area reduction by multi-output function based sequential resynthesis.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, logic synthesis, SAT, resynthesis
11	Love Singhal, Elaheh Bozorgzadeh, David Eppstein	Interconnect Criticality-Driven Delay Relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Bo Zhu, Xianglin Yang	Fiber soliton-form 3R regenerator and its performance analysis.	Sci. China Ser. F Inf. Sci.	2007	DBLP DOI BibTeX RDF	optical regenerator, optical soliton, high nonlinear fiber, optical amplitude modulation, analysis of stability
11	Yongru Gu, Keshab K. Parhi	Pipelined Parallel Decision-Feedback Decoders for High-Speed Ethernet Over Copper.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
11	Mark H. Nodine	Automatic Testbench Generation for Rearchitected Designs.	MTV	2007	DBLP DOI BibTeX RDF
11	Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton	Combinational and sequential mapping with priority cuts.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer	Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Oswaldo Cadenas, Graham M. Megson	Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor.	FPL	2006	DBLP DOI BibTeX RDF
11	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
11	Lei Wang 0011, Zhiying Wang 0003, Kui Dai	Cycle Period Analysis and Optimization of Timed Circuits.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
11	Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
11	Min Woo Kim, Jun Dong Cho	A VLSI Design of High Speed Bit-level Viterbi Decoder.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Daehong Kim, Dongwan Shin, Kiyoung Choi	Pipelining with common operands for power-efficient linear systems.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Marwa Chendeb, Mohamad Khalil, Jacques Duchêne	New Approach for Detection Using Wavelet Coefficients.	ICITA (2)	2005	DBLP DOI BibTeX RDF
11	Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan	Automatic synthesis and scheduling of multirate DSP algorithms.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Jason Baumgartner, Hari Mony	Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies.	CHARME	2005	DBLP DOI BibTeX RDF
11	Hari Mony, Jason Baumgartner, Adnan Aziz	Exploiting Constraints in Transformation-Based Verification.	CHARME	2005	DBLP DOI BibTeX RDF
11	Nathan Kitchen, Andreas Kuehlmann	Temporal Decomposition for Logic Optimization.	ICCD	2005	DBLP DOI BibTeX RDF
11	Nagendran Rangan, Karam S. Chatha	A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling.	VLSI Design	2005	DBLP DOI BibTeX RDF
11	Andrew B. Kahng, Xu Xu 0001	Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
11	Ali Dasdan	Experimental analysis of the fastest optimum cycle ratio and mean algorithms.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Cycle mean, cycle period, cycle ratio, iteration bound, system performance analysis, discrete event systems, data flow graphs, cycle time, experimental analysis
11	Davide Massimiliano Forin, Franco Curti, Giorgio Maria Tosi-Beleffi, Francesco Matera, Andrea Reale, Silvello Betti, Simone Monterosso, Alessandro Fiorelli, Michele Guglielmucci, Sergio Cascelli	All Optical 3R Regeneration and Wavelength Convertion.	OpNeTec	2004	DBLP DOI BibTeX RDF
11	Nicholas Weaver, John R. Hauser, John Wawrzynek	The SFRA: a corner-turn FPGA architecture.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture
11	Jason Baumgartner, Andreas Kuehlmann	Enhanced Diameter Bounding via Structural.	DATE	2004	DBLP DOI BibTeX RDF
11	Mongkol Ekpanyapong, Sung Kyu Lim	Performance-driven global placement via adaptive network characterization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
11	Andrew B. Kahng, Xu Xu 0001	Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning.	ISPD	2003	DBLP DOI BibTeX RDF
11	Noureddine Chabini, Wayne H. Wolf	Minimizing Variables' Lifetime in Loop-Intensive Applications.	EMSOFT	2003	DBLP DOI BibTeX RDF
11	Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung	State Reordering for Low Power Combinational Logic.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
11	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Minimum-Area Sequential Budgeting for FPGA.	ICCAD	2003	DBLP DOI BibTeX RDF
11	Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai	An Integrated Framework of Design Optimization and Space Minimization for DSP applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Robert Charles Koons, John R. Long	An inductively-tuned quadrature oscillator with extended frequency control range.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
11	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
11	Greg Snider	Performance-constrained pipelining of software loops onto reconfigurable hardware.	FPGA	2002	DBLP DOI BibTeX RDF
11	Qingfeng Zhuge, Bin Xiao 0001, Edwin Hsing-Mean Sha	Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP.	IPDPS	2002	DBLP DOI BibTeX RDF
11	Mário P. Véstias, Horácio C. Neto	System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
11	Qingfeng Zhuge, Bin Xiao 0001, Edwin Hsing-Mean Sha	Performance optimization of multiple memory architectures for DSP.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
11	Keliu Shu, Edgar Sánchez-Sinencio	A 5-GHz prescaler using improved phase switching.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
11	Timothy W. O'Neil, Edwin Hsing-Mean Sha	Minimizing resources in a repeating schedule for a split-node data-flow graph.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF
11	Shi-Yu Huang	On speeding up extended finite state machines using catalyst circuitry.	ASP-DAC	2001	DBLP DOI BibTeX RDF
11	Alvin R. Albrecht, Alan J. Hu	Register Transformations with Multiple Clock Domains.	CHARME	2001	DBLP DOI BibTeX RDF
11	Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal	Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.	VLSI Design	2001	DBLP DOI BibTeX RDF
11	Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan	Buffer Assignment Algorithms on Data Driven ASICs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture
11	Christoph Saas, Andreas Schlaffer, Josef A. Nossek	An Adiabatic Multiplier.	PATMOS	2000	DBLP DOI BibTeX RDF
11	Sundar Vedula, Simon Baker, Steven M. Seitz, Takeo Kanade	Shape and Motion Carving in 6D.	CVPR	2000	DBLP DOI BibTeX RDF
11	Jens Horstmannshoff, Heinrich Meyr	Efficient building block based RTL code generation from synchronous data flow graphs.	DAC	2000	DBLP DOI BibTeX RDF
11	Alberto Nannarelli, Tomás Lang	Low-Power Divider.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Floating-point division, low-power, digit-recurrence division
11	Jens Horstmannshoff, Heinrich Meyr	Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs.	ISSS	1999	DBLP DOI BibTeX RDF
11	Paul Tafertshofer, Andreas Ganz	SAT based ATPG using fast justification and propagation in the implication graph.	ICCAD	1999	DBLP DOI BibTeX RDF
11	Jun Ma 0011, Keshab K. Parhi, Ed F. Deprettere	Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
11	Mehrun Mokhtari, Ali Ladjemi, Urban Westergren, Lars Thylén	Bit-rate transparent electronic data regeneration in repeaters for high speed lightwave communication systems.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
11	Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi	ILP-based cost-optimal DSP synthesis with module selection and data format conversion.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
11	Raghu Burra, Dinesh Bhatia	Timing Driven Multi-FPGA Board Partitioning.	VLSI Design	1998	DBLP DOI BibTeX RDF
11	Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha	Rotation scheduling: a loop pipelining algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
11	Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao	Multidimensional interleaving for synchronous circuit design optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
11	Anand Raghunathan, Niraj K. Jha	SCALP: an iterative-improvement-based low-power data path synthesis system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
11	Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju	Algorithm and Hardware Support for Branch Anticipation.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
11	Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos	Scheduling with Confidence for Probabilistic Data-flow Graphs.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
11	Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski	A complexity analysis of sequential ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
11	Michael Sheliga, Nelson L. Passos, Edwin Hsing-Mean Sha	Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications.	CODES	1996	DBLP DOI BibTeX RDF	Multi-Dimensional Systems, High Level Synthesis, Hardware/Software Codesign
11	Keshab K. Parhi	High-level algorithm and architecture transformations for DSP synthesis.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
11	Ching-Yi Wang, Keshab K. Parhi	Resource-constrained loop list scheduler for DSP algorithms.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
11	Fermín Sánchez	Time-Constrained Loop Pipelining.	ICCAD	1995	DBLP DOI BibTeX RDF	timing and resource contraints, register optimization, scheduling, loop pipelining
11	Miodrag Potkonjak, Jan M. Rabaey	Optimizing resource utilization using transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
11	Phu Hoang, Jan M. Rabaey	A CAD environment for Real-time DSP implementations on multiprocessors.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
11	Miodrag Potkonjak, Jan M. Rabaey	Optimizing throughput and resource utilization using pipelining: Transformation based approach.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
11	Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi	Module selection and data format conversion for cost-optimal DSP synthesis.	ICCAD	1994	DBLP DOI BibTeX RDF
11	Catherine H. Gebotys	Throughput optimized architectural synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
11	Lori E. Lucke, Keshab K. Parhi	Data-flow transformations for critical path time reduction in high-level DSP synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Hervé Le Verge, Christophe Mauras, Patrice Quinton	The ALPHA language and its use for the design of systolic arrays.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF