Search results for "switches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson	Overdrive Power-Gating Techniques for Total Power Minimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
12	Christian Weiss, Hashem Tamimi, Andreas Masselli, Andreas Zell	A hybrid approach for vision-based outdoor robot localization using global and local image features.	IROS	2007	DBLP DOI BibTeX RDF
12	Sushanta Karmakar, Arobinda Gupta	Adaptive broadcast by distributed protocol switching.	SAC	2007	DBLP DOI BibTeX RDF
12	Kim Petersén, Johnny Öberg	Toward a scalable test methodology for 2D-mesh Network-on-Chips.	DATE	2007	DBLP DOI BibTeX RDF
12	Aditya Dua, Benjamin Yolken, Nicholas Bambos	Power Managed Packet Switching.	ICC	2007	DBLP DOI BibTeX RDF
12	Martín Casado, Michael J. Freedman, Justin Pettit, Jianying Luo, Nick McKeown, Scott Shenker	Ethane: taking control of the enterprise.	SIGCOMM	2007	DBLP DOI BibTeX RDF	security, architecture, network, management
12	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan	Accurate power grid analysis with behavioral transistor network modeling.	ISPD	2007	DBLP DOI BibTeX RDF	RC model of transistor, behavioral modeling of switch, power grid
12	Raluca Marin-Perianu, Mihai Marin-Perianu, Paul J. M. Havinga, Hans Scholten	Movement-Based Group Awareness with Wireless Sensor Networks.	Pervasive	2007	DBLP DOI BibTeX RDF
12	Michael Kluge, Wolfgang E. Nagel	Analysis of Linux Scheduling with VAMPIR.	International Conference on Computational Science (2)	2007	DBLP DOI BibTeX RDF
12	Onur Aciiçmez, Jean-Pierre Seifert	Cheap Hardware Parallelism Implies Cheap Security.	FDTC	2007	DBLP DOI BibTeX RDF
12	Byoung Chul Kim, In Suk Chun	Zero Latency Queuing System Based on Deficit Round Robin.	ICCCN	2007	DBLP DOI BibTeX RDF
12	Wing On Fung, Tughrul Arslan	A Power-Aware Algorithm for the Design of Reconfigurable Hardware during High Level Placement.	AHS	2007	DBLP DOI BibTeX RDF
12	Xiaofeng Yin, Dianlun Xue, Yun Cai	Application of Time-Optimal Strategy and Fuzzy Logic to the Engine Speed Control during the Gear-Shifting Process of AMT.	FSKD (4)	2007	DBLP DOI BibTeX RDF
12	Waleed K. Al-Assadi, Sindhu Kakarla	Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design.	DFT	2007	DBLP DOI BibTeX RDF
12	Jean-Claude Bermond, Frédéric Giroire, Stéphane Pérennes	Design of Minimal Fault Tolerant On-Board Networks: Practical Constructions.	SIROCCO	2007	DBLP DOI BibTeX RDF
12	Quanbao Sun, Minxuan Zhang, Liquan Xiao	Hardware-Based Multicast with Global Load Balance on k-ary n-trees.	ICPP	2007	DBLP DOI BibTeX RDF
12	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.	ICPP	2007	DBLP DOI BibTeX RDF
12	Akbar Ghaffar Pour Rahbar, Oliver W. W. Yang	Integrated TDM in Single-Hop Slotted All-Optical OPS Networks.	AINA	2007	DBLP DOI BibTeX RDF
12	Brandon Wagner, Stephen A. Renshaw, Kent Broadbent	A multi-part lab exercise for analyzing the effect of peer-to-peer software on a university network.	SIGITE Conference	2007	DBLP DOI BibTeX RDF	network traffic monitoring, networking lab, peer-to-peer, campus network
12	Akihiro Nomura 0002, Hiroya Matsuba, Yutaka Ishikawa	Network performance model for TCP/IP based cluster computing.	CLUSTER	2007	DBLP DOI BibTeX RDF
12	Rahul Ratan, Manish Kumar Shukla, A. Yavuz Oruç	Quantum Switching Networks with Classical Routing.	CISS	2007	DBLP DOI BibTeX RDF
12	Florin Avram, Antonio Gómez-Corral	On bulk-service MAP/PHL, N/1/N G-Queues with repeated attempts.	Ann. Oper. Res.	2006	DBLP DOI BibTeX RDF	Bulk-service, Repeated attempts, Markovian arrival process, Phase type distribution, Finite-buffer, Quasi-birth-and-death process
12	I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson	Placement for large-scale floating-gate field-programable analog arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Stavros Harizopoulos, Anastassia Ailamaki	Improving instruction cache performance in OLTP.	ACM Trans. Database Syst.	2006	DBLP DOI BibTeX RDF	Instruction cache, cache misses
12	Eryk Laskowski, Marek Tudruj	Assessment of Dynamic Look-Ahead Inter-Processor Connection Reconfiguration for Different Control Paradigms.	ISPDC	2006	DBLP DOI BibTeX RDF
12	Heeseon Hwang, Kevin M. Lynch, Youngil Youm	Locomotion via Impact Switching between Decoupling Vector Fields.	IROS	2006	DBLP DOI BibTeX RDF
12	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong	Performance benefits of monolithically stacked 3D-FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis
12	Sandro Penolazzi, Axel Jantsch	A High Level Power Model for the Nostrum NoC.	DSD	2006	DBLP DOI BibTeX RDF
12	Patrick Peursum, Svetha Venkatesh, Geoff A. W. West	Observation-Switching Linear Dynamic Systems for Tracking Humans Through Unexpected Partial Occlusions by Scene Objects.	ICPR (4)	2006	DBLP DOI BibTeX RDF
12	Enrique Soto, Elena Lago, Juan J. Rodríguez-Andina	FPGA Implementation of High-Performance PHM / DPHM Schedulers.	FPL	2006	DBLP DOI BibTeX RDF
12	Thilo Pionteck, Roman Koch, Carsten Albrecht	Applying Partial Reconfiguration to Networks-On-Chips.	FPL	2006	DBLP DOI BibTeX RDF
12	Yi-Fang Lin, Zhe-Hao Kang, Pangfeng Liu, Jan-Jan Wu	An Optimal Scheduling Algorithm for an Agent-Based Multicast Strategy on Irregular Networks.	GPC	2006	DBLP DOI BibTeX RDF
12	Shane O'Neill, Alan Marshall 0001, Roger F. Woods	Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch.	ISCC	2006	DBLP DOI BibTeX RDF
12	Afshin Shiravi, Paul S. Min, Yoon G. Kim	Traffic Dispatching Algorithm in Three-Stage Switch.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF	three-stage switch, sequence preserving, load balancing, Packet switch
12	Eryk Laskowski, Marek Tudruj	Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections.	PARELEC	2006	DBLP DOI BibTeX RDF
12	Yaniv Eytani, Timo Latvala	Explaining Intermittent Concurrent Bugs by Minimizing Scheduling Noise.	Haifa Verification Conference	2006	DBLP DOI BibTeX RDF	Concurrent debugging, scheduling noise, Java, testing
12	Rashad Ramzan, Lei Zou, Jerzy J. Dabrowski	LNA design for on-chip RF test.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Chia-Lung Liu, Chiou Moh, Chin-Chi Wu, Woei Lin	Performance Evaluation of the Parallel Packet Switch with a Sliding Window Scheme.	ICCSA (2)	2006	DBLP DOI BibTeX RDF
12	Ling Wu, Cheng Li 0005	Performance Analysis of Dynamic Reconfigurable Queues for High Speed Routers.	CCECE	2006	DBLP DOI BibTeX RDF
12	Yan Lin 0001, Fei Li 0003, Lei He 0001	Circuits and architectures for field programmable gate array with configurable supply voltage.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Krishna V. Palem	Energy Aware Computing through Probabilistic Switching: A Study of Limits.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	low-power design, Energy-aware systems, probabilistic computation
12	Brian Schott, Michael Bajura, Joseph Czarnaski, Jaroslav Flidr, Tam Tho, Li Wang	A modular power-aware microsensor with >1000X dynamic power range.	IPSN	2005	DBLP DOI BibTeX RDF
12	Yan Lin 0001, Fei Li 0003, Lei He 0001	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
12	Yan Lin 0001, Fei Li 0003, Lei He 0001	Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Tony K. Mak, Kenneth P. Laberteaux, Raja Sengupta 0002	A multi-channel VANET providing concurrent safety and commercial services.	Vehicular Ad Hoc Networks	2005	DBLP DOI BibTeX RDF	dedicated short range communication (DSRC), wireless LAN, broadcast, medium access control (MAC), multi-channels, PCF
12	Daniel Ortega, Salvador Revelo, José Mariano Fernández Nava, Pedro Bañuelos Sánchez	Output Voltage Effects in a 2x2 SMC Caused by Time Index Change.	CONIELECOMP	2005	DBLP DOI BibTeX RDF	Multilevel converters, SMC (Stacked Multicell Converter), Time Index (?), NPC (Neutral Point Clamp), PWM
12	Zhu Ding, Raymond R. Hoare, Alex K. Jones, Dan Li, Shou-Kuo Shao, Shen-Chien Tung, Jiang Zheng 0002, Rami G. Melhem	Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Teresa Nachiondo Frinós, José Flich, José Duato	Efficient Reduction of HOL Blocking in Multistage Networks.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan	Configuring the Circuit Switched Tree for Multiple Width Communications.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Ajay K. Katangur, Yi Pan 0001	Performance Analysis of Optical Multistage Interconnection Networks with Limited Crosstalk.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Igor Radusinovic, Zoran Veljovic	New Round-Robin Scheduling Algorithm for Combined Input-Crosspoint Buffered Switch.	ICN (1)	2005	DBLP DOI BibTeX RDF
12	Wenjie Li, Lei Shi 0002, Yang Xu 0010, Bin Liu 0001	Efficient Approach to Merge and Segment IP Packets.	ICCNMC	2005	DBLP DOI BibTeX RDF
12	Isaac Keslassy, Cheng-Shang Chang, Nick McKeown, Duan-Shin Lee	Optimal load-balancing.	INFOCOM	2005	DBLP DOI BibTeX RDF
12	Henrik Buchholz, Jürgen Döllner	View-Dependent Rendering of Multiresolution Texture-Atlases.	IEEE Visualization	2005	DBLP DOI BibTeX RDF	Multiresolution textures, texture levelof-detail, view-dependent rendering, realtime rendering
12	Gabriel M. Rebeiz	RF MEMS for Low Power Wireless Communications.	ICMENS	2005	DBLP DOI BibTeX RDF
12	Jordan E. Massad, Hartono Sumali, David S. Epp, Christopher W. Dyck	Modeling, Simulation, and Testing of the Mechanical Dynamics of an RF MEMS Switch.	ICMENS	2005	DBLP DOI BibTeX RDF
12	Shaz Qadeer, Jakob Rehof	Context-Bounded Model Checking of Concurrent Software.	TACAS	2005	DBLP DOI BibTeX RDF
12	Tetsuo Nishi, Masato Ogata	Graph-theoretic approach to the design of four-switch DC-DC converters.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
12	Axel Jantsch, Robert Lauter, Arseni Vitkovski	Power analysis of link level and end-to-end data protection in networks on chip.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
12	Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga	Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
12	David Marche, Yves Gagnon, Yvon Savaria	. A new switch compensation technique for inverted R-2R ladder DACs.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
12	Bor-Ren Lin, Chun-Hao Huang, Zheng-Zhang Yang	Three-phase power factor corrector based on capacitor-clamped topology.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Wu Jigang, Thambipillai Srikanthan, Heiko Schröder	Efficient Techniques and Hardware Analysis for Mesh-Connected Processors.	ICA3PP	2005	DBLP DOI BibTeX RDF	fault-tolerance, algorithm, parallel processing, reconfiguration, Mesh
12	Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman	Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.	ISQED	2005	DBLP DOI BibTeX RDF
12	Ding-Jyh Tsaur, Xian-Yang Lu, Chin-Chi Wu, Woei Lin	3D-VOQ Switch Design and Evaluation.	AINA	2005	DBLP DOI BibTeX RDF
12	Nen-Fu Huang, Kwei-Bor Chen, Whai-En Chen	Fast and Scalable Multi-TCAM Classification Engine for Wide Policy Table Lookup.	AINA	2005	DBLP DOI BibTeX RDF
12	Chia-Lung Liu, Woei Lin, Chin-Chi Wu	Evaluation and Analysis of the Sliding-Window Parallel Packet Switch.	AINA	2005	DBLP DOI BibTeX RDF
12	Kevin J. Barker, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones, Darren J. Kerbyson, Dan Li, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker	On the Feasibility of Optical Circuit Switching for High Performance Computing Systems.	SC	2005	DBLP DOI BibTeX RDF
12	Ziqian Dong, Roberto Rojas-Cessa	Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
12	Bill Lin 0001, Isaac Keslassy	A Scalable Switch for Service Guarantees.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
12	Shin'ichi Miura, Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Takayuki Okamoto	Low-cost High-bandwidth Tree Network for PC Clusters based on Tagged-VLAN Technology.	ISPAN	2005	DBLP DOI BibTeX RDF
12	Ahmad Faraj, Pitch Patarasuk, Xin Yuan 0001	Bandwidth Efficient All-to-All Broadcast on Switched Clusters.	CLUSTER	2005	DBLP DOI BibTeX RDF
12	William J. Turner	Preconditioners for singular black box matrices.	ISSAC	2005	DBLP DOI BibTeX RDF	Wiedemann method, black box linear algebra, rank preconditioner, singular linear system, switching network, Toeplitz matrix
12	Khaled M. F. Elsayed, Amr Saad Ayad, Mahmoud T. El-Hadidi	Performance Evaluation of Resource Reservation Policies for Rate-Controlled Earliest-Deadline-First Scheduling in Multi-Service Packet Networks.	Telecommun. Syst.	2004	DBLP DOI BibTeX RDF	rate-controlled earliest-deadline first scheduling, deterministic delay bounds, multi-service networks, call admission control, resource reservation
12	Stefano Bregni, Achille Pattavina	Performance Evaluation of Deflection Routing in Optical IP Packet-Switched Networks.	Clust. Comput.	2004	DBLP DOI BibTeX RDF	Arrayed Waveguide Grating (AWG), Internet Protocol (IP), optical networking, optical switching
12	Kyu-Jin Cho, Binayak Roy, Stephen A. Mascaro, H. Harry Asada	A Vast DOF Robotic Car Seat using SMA Actuators with a Matrix Drive System.	ICRA	2004	DBLP DOI BibTeX RDF
12	José Duato, José Flich, Teresa Nachiondo Frinós	A Cost-Effective Technique to Reduce HOL Blocking in Single-Stage and Multistage Switch Fabrics.	PDP	2004	DBLP DOI BibTeX RDF
12	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
12	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Fault Tolerance of Programmable Switch Blocks.	DATE	2004	DBLP DOI BibTeX RDF
12	Kyeong-Sik Min, Young-Hee Kim, Daejeong Kim, Dong Myeong Kim, Jin-Hong Ahn	A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Kiumi Akingbehin, Nilesh V. Patel	Development of a Hybrid Automotive Wireless Harness.	COMPSAC Workshops	2004	DBLP DOI BibTeX RDF
12	Kyung Dong Ryu, Nimish Pachapurkar, Liana L. Fong	Adaptive Memory Paging for Efficient Gang Scheduling of Parallel Applications.	IPDPS	2004	DBLP DOI BibTeX RDF	adaptive operating system, parallel computing, virtual memory, gang scheduling
12	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array.	IPDPS	2004	DBLP DOI BibTeX RDF	fault tolerance, FPGA, routing, testing
12	Zhenghao Zhang, Yuanyuan Yang	Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion Capability.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF	scheduling, bipartite graphs, optical interconnects, Wavelength-division-multiplexing (WDM), matroid, wavelength conversion, bipartite matching, limited range wavelength conversion
12	Renqiu Huang, Ranga Vemuri	Analysis and evaluation of a hybrid interconnect structure for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Jason Helge Anderson, Farid N. Najm	Low-power programmable routing circuitry for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha	Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures.	ICCD	2004	DBLP DOI BibTeX RDF
12	Håkan Sivencrona, Torbjörn Olsson, Roger Johansson, Jan Torin	RedCAN: Simulations of Two Fault Recovery Algorithms for CAN.	PRDC	2004	DBLP DOI BibTeX RDF
12	François Abel, Cyriel Minkenberg, Ronald P. Luijten, Mitchell Gusat, Ilias Iliadis	10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times.	IEEE Micro	2003	DBLP DOI BibTeX RDF
12	Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao	Concurrent fault detection for a multiple-plane packet switch.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	parallel planes, fault detection, packet switch, concurrent testing, single fault
12	Scott Hamilton	Intel Research Extends Moore's Law.	Computer	2003	DBLP DOI BibTeX RDF
12	José Flich, Pedro López 0001, Manuel P. Malumbres, José Duato, Tomas Rokicki	Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Networks of workstations, wormhole switching, irregular topologies, source routing, minimal routing
12	Krishna V. Palem	Energy Aware Algorithm Design via Probabilistic Computing: From Algorithms and Models to Moore?s Law and Novel (Semiconductor) Devices.	HiPC	2003	DBLP DOI BibTeX RDF
12	María Engracia Gómez, José Flich, Antonio Robles, Pedro López 0001, José Duato	VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks.	IPDPS	2003	DBLP DOI BibTeX RDF	InfiniBand network, virtual lanes, irregular topologies, head-of-line blocking
12	Yi-Fang Lin, Pangfeng Liu	Efficient Agent-Based Multicast on Wormhole Switch-Based Irregular Networks.	IPDPS	2003	DBLP DOI BibTeX RDF
12	Yuanyuan Yang 0001, Jianchao Wang	Sparse WDM Optical Interconnects under Wavelength-Based Model.	IPDPS	2003	DBLP DOI BibTeX RDF	multicast, Interconnection networks, permutation, optical interconnects, wavelength-division-multiplexing (WDM), wavelength conversion, multistage networks, sparse crossbars
12	Hyunseung Choo, Youngsong Mun	Improving the Performance of Multistage Interconnection Networks under Nonuniform Traffic Pattern on Shorter Cycles.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
12	Ali Mohammad Zareh Bidoki, Nasser Yazdani, Sayed Vahid Azhari, Siavash Samadian-Barzoki	A High Speed ATM/IP Switch Fabric Using Distributed Scheduler.	ICOIN	2003	DBLP DOI BibTeX RDF
12	Ahmad Rostami, Seyed Mostafa Safavi	Performance Analysis of a VC Merger Capable of Supporting Differentiated Services in an MPLS over ATM Switch.	ICOIN	2003	DBLP DOI BibTeX RDF
12	Wenjie Li, Yiping Gong, Bin Liu 0001	Performance Evaluation of Crossbar Switch Fabrics in Core Routers.	AINA	2003	DBLP DOI BibTeX RDF	CIOQ, OPRR, VOQ, Single Queue, Speedup