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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4401 occurrences of 2030 keywords
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Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
25 | Hyunyoung Lee, Jennifer L. Welch |
Randomized registers and iterative algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 17(3), pp. 209-221, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
probabilistic quorums, randomization, distributed shared memory, iterative algorithms, registers |
25 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
Integrated On-Chip Storage Evaluation in ASIP Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 274-279, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Vlad Petric, Tingting Sha, Amir Roth |
RENO - A Rename-Based Instruction Optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 98-109, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
Exploring Storage Organization in ASIP Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 120-127, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Ilhyun Kim, Mikko H. Lipasti |
Half-Price Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 28-38, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh |
A Comparison of Asymptotically Scalable Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 35(2), pp. 129-150, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | T. N. Vijaykumar, Irith Pomeranz, Karl Cheng |
Transient-Fault Recovery Using Simultaneous Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 87-98, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi |
A new approach to built-in self-testable datapath synthesis based on integer linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 594-605, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik |
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 111-128, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Hyunyoung Lee, Jennifer L. Welch |
Specification, implementation and application of randomized regular registers (brief announcement). ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Nineteenth Annual ACM Symposium on Principles of Distributed Computing, July 16-19, 2000, Portland, Oregon, USA., pp. 338, 2000, ACM, 1-58113-183-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Fidel Muradali, Takao Nishida, Tsuguo Shimizu |
A structure and technique for pseudorandom-based testing of sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 107-115, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
distributed generator, Built-in self-test, design for test, pseudorandom generation, sequential test, weighted random patterns |
25 | Marina Papatriantafilou, Philippas Tsigas |
How a Rainbow Coloring Function Can Simulate Wait-Free Handshaking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 1994, 19th International Symposium, MFCS'94, Kosice, Slovakia, August 22 - 26, 1994, Proceedings, pp. 546-555, 1994, Springer, 3-540-58338-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Soma Chaudhuri, Mark R. Tuttle |
Fast Increment Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WDAG ![In: Distributed Algorithms, 8th International Workshop, WDAG '94, Terschelling, The Netherlands, September 29 - October 1, 1994, Proceedings, pp. 74-88, 1994, Springer, 3-540-58449-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé |
Using Sacks to Organize Registers in VLIW Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 628-639, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Yonghua Hu, Xin Zhang, Shuying Wang, Wei Liang 0005, Kuan-Ching Li |
Research on global register allocation for code containing array-unit dual-usage register names. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 35(19), 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Yahia Idriss Benalioua, Nathan Lhote, Pierre-Alain Reynier |
Register Minimization of Cost Register Automata over a Field. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2307.13505, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Xianhua Liu 0001, Qinghong Yang, Miao Tao, Qinshu Chen, Xu Cheng |
An Efficient Register Renaming Technique with Delayed Allocation and Register Packing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, Scotland, UK, November 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6044-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa |
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 101-D(6), pp. 1521-1531, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Ryoma Senda, Yoshiaki Takata, Hiroyuki Seki |
Complexity Results on Register Context-Free Grammars and Register Tree Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAC ![In: Theoretical Aspects of Computing - ICTAC 2018 - 15th International Colloquium, Stellenbosch, South Africa, October 16-19, 2018, Proceedings, pp. 415-434, 2018, Springer, 978-3-030-02507-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Mohammad Sadrosadati, Amirhossein Mirhosseini, Seyed Borna Ehsani, Hamid Sarbazi-Azad, Mario Drumond, Babak Falsafi, Rachata Ausavarungnirun, Onur Mutlu |
LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018, pp. 489-502, 2018, ACM, 978-1-4503-4911-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Mohammad Abdel-Majeed, Alireza Shafaei, Hyeran Jeon, Massoud Pedram, Murali Annavaram |
Pilot Register File: Energy Efficient Partitioned Register File for GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017, pp. 589-600, 2017, IEEE Computer Society, 978-1-5090-4985-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Abdulaziz Eker, Yakup Murat Mert, Oguz Ergin |
URFA-Update based register file architecture with partial register write for energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 47, pp. 445-453, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Suranjan Ganguly, Debotosh Bhattacharjee, Mita Nasipuri |
Register-My-Face: a tool to register three-dimensional face images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electronic Imaging ![In: J. Electronic Imaging 24(4), pp. 043007, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Hiroaki Kawashima, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo |
Register Port Prediction for a Banked Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDAR ![In: Third International Symposium on Computing and Networking, CANDAR 2015, Sapporo, Hokkaido, Japan, December 8-11, 2015, pp. 551-555, 2015, IEEE Computer Society, 978-1-4673-9797-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Chia-Han Lu, Wen-Li Shih, Chung-Ju Wu, Jenq Kuen Lee |
Achieving spilling-friendly register file assignment for highly distributed register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 69(3), pp. 1342-1362, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Yiqun Wang, Hongyang Jia, Yongpan Liu, Qing'an Li, Chun Jason Xue, Huazhong Yang |
Register allocation for hybrid register architecture in nonvolatile processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 1050-1053, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Mohammad Abdel-Majeed, Murali Annavaram |
Warped register file: A power efficient register file for GPGPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 412-423, 2013, IEEE Computer Society, 978-1-4673-5585-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Wann-Yun Shieh, Bo-Syun Wang |
Power-aware register assignment for large register file design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 61(3), pp. 719-742, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Hai Lin, Tiansi Hu, Yunsi Fei |
A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 17(4), pp. 40:1-40:19, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Ming-Yen Homh, Jen-Ming Wu |
Vector Register Design with Register Bypassing for Embedded DSP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC-ICESS ![In: 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, HPCC-ICESS 2012, Liverpool, United Kingdom, June 25-27, 2012, pp. 1033-1038, 2012, IEEE Computer Society, 978-1-4673-2164-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Eva Thors Adolfsson, Andreas Rosenblad |
Reporting systems, reporting rates and completeness of data reported from primary healthcare to a Swedish quality register - The National Diabetes Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Medical Informatics ![In: Int. J. Medical Informatics 80(9), pp. 663-668, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Xuan Guan, Yunsi Fei |
Register file partitioning and recompilation for register file power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 15(3), pp. 24:1-24:30, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Fakhar Anjam, Stephan Wong, Faisal Nadeem |
A multiported register file with register renaming for configurable softcore VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, pp. 403-408, 2010, IEEE, 978-1-4244-8981-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Wann-Yun Shieh, Shu-Yi Hsu |
Power-Aware Register Assignment for Multi-Banked Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 25(6), pp. 1901-1920, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
23 | Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee |
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 21(1), pp. 101-114, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Hui Zeng, Kanad Ghose, Dmitry Ponomarev 0001 |
Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: ICPP 2009, International Conference on Parallel Processing, Vienna, Austria, 22-25 September 2009, pp. 453-461, 2009, IEEE Computer Society, 978-0-7695-3802-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Zhihang Yu, Yong Yu 0001, Feilong Tang, Minyi Guo |
A Register Framework for Network Processors with Banked Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISIS ![In: 2009 International Conference on Complex, Intelligent and Software Intensive Systems, CISIS 2009, Fukuoka, Japan, March 16-19, 2009, pp. 607-613, 2009, IEEE Computer Society, 978-0-7695-3575-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Wann-Yun Shieh, Chien-Chen Chen |
Saving Register-File Leakage Energy by Register-usage Exploiting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 24(5), pp. 1429-1444, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
23 | Wann-Yun Shieh, Shu-Yi Hsu |
Low Power Register File Design by Power Aware Register Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2008 International Conference on Computer Design, CDES 2008, Las Vegas, Nevada, USA, July 14-17, 2008, pp. 63-69, 2008, CSREA Press, 1-60132-056-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
23 | Wann-Yun Shieh, Chang-Yi Lee |
Power-aware Register Renaming for Multi-banked Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2007 International Conference on Embedded Systems & Applications, USA 2007, June 25-28, 2007, Las Vegas, Nevada, USA, pp. 184-187, 2007, CSREA Press, 1-60132-052-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
23 | Thomas Zeitlhofer, Bernhard Wess |
List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Signal Process. ![In: Signal Process. 83(7), pp. 1411-1425, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Jinpyo Park, Je-Hyung Lee, Soo-Mook Moon |
Register Allocation for Banked Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OM@PLDI ![In: Proceedings of the 2001 ACM SIGPLAN Workshop on Optimization of Middleware and Distributed Systems, OM '01, Snow Bird, Utah, USA, pp. 39-47, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Guido Araujo, Sharad Malik, Mike Tien-Chien Lee |
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 591-596, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Josep Llosa, Mateo Valero, Eduard Ayguadé |
Non-Consistent Dual Register Files to Reduce Register Pressure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), Raleigh, North Carolina, USA, January 22-25, 1995, pp. 22-31, 1995, IEEE Computer Society, 0-8186-6445-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | K. Vidyasankar |
Converting Lamport's Regular Register to Atomic Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Lett. ![In: Inf. Process. Lett. 28(6), pp. 287-290, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
23 | Ingrid Y. Bucher, Margaret L. Simmons |
A Close Look at Vector Performance of Register-to-Register Vector Computers and a New Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Banff, Alberta, Canada, May 11-14, 1987, pp. 39-45, 1987, ACM, 0-89791-225-X. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
23 | Tomás Lang, Miquel Huguet |
Reduced register saving/restoring in single-window register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 14(3), pp. 17-26, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
23 | Manfred Weber, Susan L. Bernstein |
Global register allocation for non-equivalent register sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 15(2), pp. 74-81, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
22 | Ivan D. Baev |
Techniques for Region-Based Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2009, The Seventh International Symposium on Code Generation and Optimization, Seattle, Washington, USA, March 22-25, 2009, pp. 147-156, 2009, IEEE Computer Society, 978-0-7695-3576-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
register allocation, region-based compilation |
22 | S. Subha |
A Modified Linear Scan Register Allocation Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 825-827, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Live range, Register allocation |
22 | Guilin Chen, Mahmut T. Kandemir, Mary Jane Irwin, J. Ramanujam |
Reducing code size through address register assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(1), pp. 225-258, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Software compilation, address registers, DSP, register assignment |
22 | Dennis K. Y. Tong, Evangeline F. Y. Young |
Performance-driven register insertion in placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 53-60, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
post-retiming, register insertion, placement |
22 | Yumin Zhang, Xiaobo Hu 0001, Danny Z. Chen |
Efficient global register allocation for minimizing energy consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 37(4), pp. 42-53, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
register allocation, low energy |
22 | Glenn Altemose, Cindy Norris |
Register pressure responsive software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), March 11-14, 2001, Las Vegas, NV, USA, pp. 626-631, 2001, ACM, 1-58113-287-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining |
22 | Gang Chen, Michael D. Smith 0001 |
Reorganizing global schedules for register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999, pp. 408-416, 1999, ACM, 1-58113-164-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
superblock scheduling, instruction-level parallelism, register allocation |
22 | Christine Makowski, Lori L. Pollock |
Achieving efficient register allocation via parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1995 ACM symposium on applied computing, SAC'95, Nashville, TN, USA, February 26-28, 1995, pp. 123-129, 1995, ACM, 0-89791-658-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cique separators, parallel register allocation, graph coloring |
22 | Alexandre E. Eichenberger, Edward S. Davidson |
Register allocation for predicated code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995, pp. 180-191, 1995, ACM / IEEE Computer Society, 0-8186-7349-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hyperblocks, interference, register allocation, software pipelining, predicated execution |
22 | Albrecht P. Stroele, Hans-Joachim Wunderlich |
Test register insertion with minimum hardware cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 95-101, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
test register insertion, BILBO, CBILBO, Built-in self-test |
22 | Eric Sprangle, Yale N. Patt |
Facilitating superscalar processing via a combined static/dynamic register renaming scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 143-147, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
superscalar processors, out-of-order execution, register renaming, predicated execution |
22 | Nazar S. Haider, Nick Kanopoulos |
Efficient board interconnect testing using the split boundary scan register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(2), pp. 181-189, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan |
22 | Yehuda Afek, Gideon Stupp |
Synchronization power depends on the register size (Preliminary Version) ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 34th Annual Symposium on Foundations of Computer Science, Palo Alto, California, USA, 3-5 November 1993, pp. 196-205, 1993, IEEE Computer Society, 0-8186-4370-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
synchronization registers, register size, machine instructions, multiprocessors, space complexity, multiprocessor architectures, compare and swap, synchronization primitives, complexity hierarchy |
22 | Jacob Savir, William H. McAnney |
A Multiple Seed Linear Feedback Shift Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(2), pp. 250-252, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
multiple seed linear feedback shift register, change-of-seeds, clock pulses, built-in self test, feedback, LFSR, shift registers |
22 | Randy Allen, Ken Kennedy |
Vector Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(10), pp. 1290-1317, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
vector register allocation, compiling vector languages, aggressive program transformations, parallel processing, program compilers, data dependence, supercomputers |
22 | Wei-Chung Hsu, Charles N. Fischer, James R. Goodman |
On the Minimization of Loads/Stores in Local Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 15(10), pp. 1252-1260, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
local register allocation, program esptimization, Computer architecture |
22 | Vijay Pitchumani, Edward P. Stabler |
Verification of Register Transfer Level Parallel Control Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(8), pp. 761-765, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
critical region, parallel control sequence, Assertion, register transfer level, shared resource, clock cycle, auxiliary variable, verification condition |
22 | Bella Bose, T. R. N. Rao |
Unidirectional Error Codes for Shift-Register Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(6), pp. 575-578, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
Arithmetic residue check, unidirectional errors, parity check, shift register memories, information rate, asymmetric errors, symmetric errors |
22 | Yuval Tamir, Carlo H. Séquin |
Strategies for Managing the Register File in RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(11), pp. 977-989, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
VLSI processor, Cache fetch strategies, register file management, computer architecture, RISC, procedure calls |
22 | Vijay Pitchumani, Edward P. Stabler |
An Inductive Assertion Method for Register Transfer Level Design Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(12), pp. 1073-1080, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
inductive assertion method, synchronous logic, theorem proving, Assertions, predicate calculus, register transfer level design, verification condition |
22 | Gerhard Wustmann |
Comments on "Autocorrelation Function of Sequential M-Bit Words Taken from an N-Bit Shift Register (PN) Sequence". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(3), pp. 241, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
shift register sequence, autocovariance function, Autocorrelation function, PN sequence |
22 | Francis Y. L. Chin, K. Samson Fok |
Fast Sorting Algorithms on Uniform Ladders (Multiple Shift-Register Loops). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(7), pp. 618-631, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
uniform ladder, Bubble sort, Demuth's Algorithm, magnetic bubbles, odd-even transposition sort, shift-register loops, sorting, switches, merging, period, loading |
22 | Svetlana P. Kartashev, Steven I. Kartashev |
On Modular Networks Satisfying the Shift-Register Rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(12), pp. 1153-1176, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
modular network, Augnentation of original program, interconnections satisfying shift-register rule, modular decomposition of programs, computer-aided design |
22 | Farhad Hemmati, Daniel J. Costello Jr. |
An Algebraic Construction for q-ary Shift Register Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(12), pp. 1192-1195, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
shift register sequence, maximal length cycle, Euclidean Algorithm, Hamming weight |
22 | Werner E. Kluge |
Traversing Binary Tree Structures with Shift-Register Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(11), pp. 1112-1122, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
Data permutations, traversal control, tree structures, shift-register memories, tree traversals |
22 | Harold Hoehne, Robert Piloty |
Design Verification at the Register Transfer Language Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(9), pp. 861-867, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Compiler-interpreter system, computer description language, hardware design automation, register transfer language (RTL), simulation, error detection, design verification |
22 | Johannes Mykkeltveit |
Generating and Counting the Double Adjacencies in a Pure Circulating Shift Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(3), pp. 299-304, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Adjacency diagram, adjacent cycles, binary cycle, de Bruijn graph, feedback shift register |
22 | Mario Barbacci |
A Comparison of Register Transfer Languages for Describing Computers and Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(2), pp. 137-150, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
language properties, design automation, register transfer level, design languages, structural description, behavioral description, Asynchronous control |
21 | Matthias Braun 0003, Sebastian Hack |
Register Spilling and Live-Range Splitting for SSA-Form Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 18th International Conference, CC 2009, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009, York, UK, March 22-29, 2009. Proceedings, pp. 174-189, 2009, Springer, 978-3-642-00721-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose |
Selective Writeback: Reducing Register File Pressure and Energy Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(6), pp. 650-661, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Activity and register placement aware gated clock network design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 182-189, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
gated clock tree, low power, placement |
21 | Hassan A. Salamy, J. Ramanujam |
Optimal address register allocation for arrays in DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2008, Atlanta, Georgia, USA, 23-24 October 2008, pp. 67-72, 2008, IEEE Computer Society, 978-1-4244-2612-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Shuo Wang, Fan Zhang 0010, Jianwei Dai, Lei Wang 0003, Zhijie Jerry Shi |
Making register file resistant to power analysis attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 577-582, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Weibo Xie, Fu Ting |
Design and Implementation of the Virtual Machine Constructing on Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (2) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 2: Software Engineering, December 12-14, 2008, Wuhan, China, pp. 424-430, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Tzi-cker Chiueh |
Fast Bounds Checking Using Debug Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 99-113, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton |
Scalable min-register retiming under timing and initializability constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 534-539, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
min-area, retiming, initial state, sequential optimization |
21 | Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek |
Automatic Design Space Exploration of Register Bypasses in Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12), pp. 2102-2115, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Youcef Bouchebaba, Bruno Girodias, Fabien Coelho, Gabriela Nicolescu, El Mostapha Aboulhamid |
Buffer and Register Allocation for Memory Space Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 49(1), pp. 123-138, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
program transformation, memory hierarchy, data locality, memory optimization |
21 | Zeming Zhang, Wenjian Luo, Xufa Wang |
Immune genetic programming based on register-stack structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 3751-3758, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang 0009, Huimin Cui, Dongrui Fan |
Optimized Register Renaming Scheme for Stack-Based x86 Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2007, 20th International Conference, Zurich, Switzerland, March 12-15, 2007, Proceedings, pp. 43-56, 2007, Springer, 978-3-540-71267-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Slavisa Jovanovic, Camel Tanougast, Serge Weber |
A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 358-364, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha |
Design Exploration With Imprecise Latency and Register Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2650-2662, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Jianping Hu, Hong Li, Yangbo Wu |
Low-Power Register File Based on Adiabatic Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 382-392, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny |
Fast Asynchronous Shift Register for Bit-Serial Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 117-127, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Hiroshi Yamauchi, Jan Vitek |
Combining Offline and Online Optimizations: Register Allocation and Method Inlining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APLAS ![In: Programming Languages and Systems, 4th Asian Symposium, APLAS 2006, Sydney, Australia, November 8-10, 2006, Proceedings, pp. 307-322, 2006, Springer, 3-540-48937-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Lang Hames, Bernhard Scholz |
Nearly Optimal Register Allocation with PBQP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JMLC ![In: Modular Programming Languages, 7th Joint Modular Languages Conference, JMLC 2006, Oxford, UK, September 13-15, 2006, Proceedings, pp. 346-361, 2006, Springer, 3-540-40927-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Li Shen 0002 |
VFSim: Concurrent Fault Simulation at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 175-186, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling |
21 | Joep L. W. Kessels |
Register Communication between Mutually Asynchronous Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 66-75, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu |
Register placement for low power clock network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 588-593, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Il-Sun Hwang, Gi Sung Yoo, Jin-Wook Chung |
Efficient Mobility Management Using Dynamic Location Register in IMT-2000 Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (3) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part III, pp. 649-654, 2005, Springer, 3-540-28896-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Siddhartha Shivshankar, Sunil Vangara, Alexander G. Dean |
Balancing register pressure and context-switching delays in ASTI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 286-294, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous software thread integration, software-implemented-communication protocols, hardware to software migration, fine-grain concurrency |
21 | Keith D. Cooper, Anshuman Dasgupta, Jason Eckhardt |
Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers, pp. 1-16, 2005, Springer, 978-3-540-69329-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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