Search results for "jitter"

Hits ?▲	Authors	Title	Venue	Year	Link
12	Dries Vercaemer, Johan Raman, Pieter Rombouts	Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Ian Galton, Colin Weltin-Wu	Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng 0001, Jian Liu 0021, Nanjian Wu	An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Yong Chen 0005, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, Rui Paulo Martins	A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Frank Herzel, Silvio Waldmann, Dietmar Kissinger	Numerical Jitter Minimization for PLL-Based FMCW Radar Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Fernando Cardes, Victor Medina, Susana Patón, Luis Hernández 0003	Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Pei-Yuan Chou, Jinn-Shyan Wang	An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
12	Danilo Tardioli, Ramviyas Parasuraman, Petter Ögren	Pound: A multi-master ROS node for reducing delay and jitter in wireless multi-robot networks.	Robotics Auton. Syst.	2019	DBLP DOI BibTeX RDF
12	Kiichi Niitsu, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi 0001	Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
12	Lorenzo Piazzo	Image Estimation in the Presence of Irregular Sampling, Noise, and Pointing Jitter.	IEEE Trans. Image Process.	2019	DBLP DOI BibTeX RDF
12	Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz	Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter.	DDECS	2019	DBLP DOI BibTeX RDF
12	Ahtisham Ali Ansari, Sri Pramodh Rachuri, Arzad Alam Kherani, Deepaknath Tandur	An SD-WAN Controller for Delay Jitter Minimization in Coded Multi-access Systems.	ANTS	2019	DBLP DOI BibTeX RDF
12	Julian Camilo Gomez Diaz, Shiva Kiran, Samuel Palermo, Sebastian Hoyos	Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper).	MWSCAS	2019	DBLP DOI BibTeX RDF
12	Jean Schoentgen, Philipp Aichinger	Analysis and Synthesis of Vocal Flutter and Vocal Jitter.	INTERSPEECH	2019	DBLP DOI BibTeX RDF
12	Malek Souilem, Jai Narayan Tripathi, Wael Dghais, Belgacem Hamdi	I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO).	VLSI-SoC	2019	DBLP DOI BibTeX RDF
12	Yanhua Ma, Xian Du, Jianqin Mao, Yuqi Jin	Active Optical Axis Jitter Control by a Magnetostrictive Fast Steering Mirror under Disturbances.	ICCA	2019	DBLP DOI BibTeX RDF
12	Gehan Anthonys, Michael J. Cree, Lee V. Streeter	Jitter Measurement in Digital Signals by Using Software Defined Radio Technology.	I2MTC	2019	DBLP DOI BibTeX RDF
12	Megha Sahu, Snigdha Damle, Arzad Alam Kherani	Traffic Splitting for End-to-End Delay Jitter Control in Uplink Multi-Access Systems.	COMSNETS	2019	DBLP DOI BibTeX RDF
12	Megha Sahu	Delay Jitter Analysis for Uplink Traffic in LTE Systems.	COMSNETS	2019	DBLP DOI BibTeX RDF
12	Jan Schat, Ulrich Möhlmann	Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random Jitter.	ETS	2019	DBLP DOI BibTeX RDF
12	Arman Rezaee, Vincent W. S. Chan	Diversity Routing to Improve Delay-Jitter Tradeoff in Uncertain Network Environments.	ICC	2019	DBLP DOI BibTeX RDF
12	Robert Raad, Elie Inaty, Martin Maier 0001	Improving Latency and Jitter Performance in CDMA-Based Next-Generation Ethernet Passive Optical Networks for 5G Applications.	IPCCC	2019	DBLP DOI BibTeX RDF
12	Pierre Lemaire 0003, Carlos Fernando Crispim Junior, Lionel Robinault, Laure Tougne	Jitter-Free Registration for Unmanned Aerial Vehicle Videos.	ISVC (1)	2019	DBLP DOI BibTeX RDF
12	Dario Russo, Stefano Ricci	FPGA-based Trigger-Synchronizer for low Frame-Jitter Signal Generation.	ICECS	2019	DBLP DOI BibTeX RDF
12	Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li 0021, Jian Pang, Teruki Someya, Atsushi Shirane	A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO.	ESSCIRC	2019	DBLP DOI BibTeX RDF
12	Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq	A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter.	ESSCIRC	2019	DBLP DOI BibTeX RDF
12	Dario Russo, Stefano Ricci	FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction.	ApplePies	2019	DBLP DOI BibTeX RDF
12	Long Wang, Xirong Que, Xiangyang Gong, Ye Tian 0008, Tongtong Wang, Xinyuan Wang 0006	A Scheduling Algorithm for Low Jitter in Ethernet-Based Fronthaul.	ISCC	2019	DBLP DOI BibTeX RDF
12	Anil Ufuk Batmaz, Wolfgang Stuerzlinger	The Effect of Rotational Jitter on 3D Pointing Tasks.	CHI Extended Abstracts	2019	DBLP DOI BibTeX RDF
12	Yuki Nagai, Taro Watanabe, Tomohiro Sato, Ryohei Nakamura, Hisaya Hadama	An Evaluation of a State-Predictive Controller and a Jitter Buffer for Remote Controlled Autonomous Vehicles via the Internet.	ICTC	2019	DBLP DOI BibTeX RDF
12	Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina	All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping.	NEWCAS	2019	DBLP DOI BibTeX RDF
12	Akihiro Toya, Takamaro Kikkawa, Yoshihiro Masui, Mitsutoshi Sugawara, Hiroyuki Ito, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Atsushi Iwata	Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection.	BioCAS	2019	DBLP DOI BibTeX RDF
12	Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin	A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.	CICC	2019	DBLP DOI BibTeX RDF
12	Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino	A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power.	CICC	2019	DBLP DOI BibTeX RDF
12	Dihang Yang, Asad A. Abidi, Hooman Darabi, Hao Xu 0005, David Murphy, Hao Wu 0026, Zhaowen Wang	A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi	A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi	A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Fei Song, Yu Zhao, Bart Wu, Litian Tang, Leon Lin, Behzad Razavi	A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Zhao Zhang, Guang Zhu, C. Patrick Yue	A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Szu-Yao Hung, Sudhakar Pamarti	A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Zunsong Yang, Yong Chen 0005, Shiheng Yang, Pui-In Mak, Rui Paulo Martins	A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Luigi Grimaldi, Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers, Kuan-Yueh James Shen, Andrey Mezhiba	Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology.	ISSCC	2019	DBLP DOI BibTeX RDF
12	Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001	A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
12	Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Yun Wang 0008, Atsushi Shirane, Kenichi Okada	0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
12	Yi-An Li, Ali M. Niknejad	A 138Fsrms-Integrated-Jitter and -249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
12	Thibault Louis, Jocelyne Troccaz, Amélie Rochet-Capellan, François Bérard	Is it Real? Measuring the Effect of Resolution, Latency, Frame rate and Jitter on the Presence of Virtual Entities.	ISS	2019	DBLP DOI BibTeX RDF
12	Siva Kumar Govindan, Huan Hu, Chung-Ching Lin, Subhanshu Gupta	A 25.6μW 8.97ps Period Jitter Phase-Locked Relaxation Oscillator with sub-1µS Start-Up for Low-Power IoT.	ISCAS	2019	DBLP DOI BibTeX RDF
12	Franz Marcus Schüffny, Sebastian Höppner, Alexander Oefelein, Christian Mayr 0001	A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration.	ISCAS	2019	DBLP DOI BibTeX RDF
12	Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal	A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems.	IntelliSys (1)	2019	DBLP DOI BibTeX RDF
12	Rui Zhang 0048, Wen-Jr Jiang, Konstantin Kuzmin, Reggie Juluri, Gee-Kung Chang, Winston I. Way	Laser Frequency Jitter Tolerance and Linewidth Requirement for ≥ 64Gbaud DP-16QAM Coherent Systems.	OFC	2019	DBLP BibTeX RDF
12	Youxin Mao, Jiaren Liu, Zhenguo Lu, Chunying Song, Philip J. Poole	Femtosecond Timing Jitter of Quantum Dot Semiconductor Comb Lasers with Self-Injection Feedback Locking.	OFC	2019	DBLP BibTeX RDF
12	Stefan Reif, Luis Gerhorst, Kilian Bender, Timo Hönig	Towards Low-Jitter and Energy-Efficient Data Processing in Cyber-Physical Information Systems.	HICSS	2019	DBLP BibTeX RDF
12	Jianfu Zhang 0001, Azrif Manut, Rui Gao, Mehzabeen Mehedi, Zhigang Ji, Weidong Zhang 0002, John S. Marsland	An assessment of RTN-induced threshold voltage jitter.	ASICON	2019	DBLP DOI BibTeX RDF
12	Sophie Jörg, Andrew T. Duchowski, Krzysztof Krejtz, Anna Niedzielska	Perceptual Comparison of Procedural and Data-Driven Eye Motion Jitter.	SAP	2019	DBLP DOI BibTeX RDF
12	Xiang Gao	Low Jitter and Low Power PLL：Towards The Utopia.	ISOCC	2019	DBLP DOI BibTeX RDF
12	Igor Kartashevskiy, Marina Buranova	Calculation of Packet Jitter for Correlated Traffic.	NEW2AN	2019	DBLP DOI BibTeX RDF
12	Karel Hynek, Tomás Benes, Matej Bartik, Pavel Kubalík	Ultra High Resolution Jitter Measurement Method for Ethernet Based Networks.	CCWC	2019	DBLP DOI BibTeX RDF
12	Yi Liu 0011, Makoto Ikeda, Keita Matsuo, Leonard Barolli, Makoto Takizawa 0001	Improving Peer Reliability Considering Jitter Parameter: A Fuzzy-Based System for JXTA-Overlay P2P System.	AINA Workshops	2019	DBLP DOI BibTeX RDF
12	Kiyotaka Ichiyama, Takashi Kusaka, Masahiro Ishida	A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces.	ITC	2019	DBLP DOI BibTeX RDF
12	Zhaoxiang Zhang 0002, Akira Iwasaki, Guodong Xu	Remote Sensing Satellite Jitter Detection Based on Image Registration and Convolutional Neural Network Fusion.	IGARSS	2019	DBLP DOI BibTeX RDF
12	Harry Muljono, Kathy Peng, Linda Sun, Isaac Abraham, Charlie Lin, Yanjie Zhu, Chunrong Song	A 2.666GT/s 128GB/s 14nm Memory I/O with Jitter and Crosstalk Cancellation.	A-SSCC	2019	DBLP DOI BibTeX RDF
12	Zunsong Yang, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins	A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.	A-SSCC	2019	DBLP DOI BibTeX RDF
12	Sangdon Jung, Jaehong Jung, Byungki Han, Seunghyun Oh, Jongwoo Lee	A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology.	A-SSCC	2019	DBLP DOI BibTeX RDF
12	Chun-Yu Lin 0002, Yu-Ting Hung, Tsung-Hsien Lin	A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS.	A-SSCC	2019	DBLP DOI BibTeX RDF
12	Ioannis Ioannidis, Hammadi Nait-Charif	Over Time RF Fitting for Jitter Free 3D Vertebra Reconstruction from Video Fluoroscopy.	CAIP (2)	2019	DBLP DOI BibTeX RDF
12	Zaher Kakehbra, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi	A Fast-Lock, Low Jitter, High-Speed Half-Rate CDR Architecture with a Composite Phase Detector (CPD).	MIXDES	2019	DBLP DOI BibTeX RDF
12	Anil Ufuk Batmaz, Wolfgang Stuerzlinger	Effects of 3D Rotational Jitter and Selection Methods on 3D Pointing Tasks.	VR	2019	DBLP DOI BibTeX RDF
12	Nima Najaflou, Ahmet Aris, Berk Canberk, Zeynep Gürkas Aydin	The Nearest Origin-Shield (NOS): A Jitter-Free Overlay Routing Framework for Content Delivery Networks.	ISNCC	2019	DBLP DOI BibTeX RDF
12	Wei Zhang, Xiaofeng Shi, Tao Jin, Shengke Chen, Yunjiong Xu, Wei Sun, Yang Xue, Zhicheng Yu	A Moving Object Detection Algorithm of Jitter Video.	ACIRS	2019	DBLP DOI BibTeX RDF
12	Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
12	Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi	Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
12	Shravan S. Nagam, Peter R. Kinget	A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
12	Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu	Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
12	Staffan Ek, Tony Påhlsson, Christian Elgaard, Anders Carlsson, Andreas Axholt, Anna-Karin Stenman, Lars Sundström, Henrik Sjöland	A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
12	Chengming Li, Yong Yin, Pengda Wu, Xiaoli Liu 0007, Peipei Guo	Improved Jitter Elimination and Topology Correction Method for the Split Line of Narrow and Long Patches.	ISPRS Int. J. Geo Inf.	2018	DBLP DOI BibTeX RDF
12	Karim Hammad, Abdallah Moubayed, Serguei Primak, Abdallah Shami	QoS-Aware Energy and Jitter-Efficient Downlink Predictive Scheduler for Heterogeneous Traffic LTE Networks.	IEEE Trans. Mob. Comput.	2018	DBLP DOI BibTeX RDF
12	Muhammad Waqar, Ajung Kim, Peter K. Cho	A Transport Scheme for Reducing Delays and Jitter in Ethernet-Based 5G Fronthaul Networks.	IEEE Access	2018	DBLP DOI BibTeX RDF
12	Debdeep Banerjee, Kevin Yu, Garima Aggarwal	Hand Jitter Reduction Algorithm Software Test Automation Using Robotic Arm.	IEEE Access	2018	DBLP DOI BibTeX RDF
12	Jorge Muñoz-Minjares, Yuriy S. Shmaliy, Luis J. Morales-Mendoza, Miguel Vazquez-Olguin, Carlos Lastre-Dominguez	Accurate Jitter Computation in CNA Breakpoints Using Hybrid Confidence Masks With Applications to SNP Array Probing.	IEEE Access	2018	DBLP DOI BibTeX RDF
12	Pasquale Daponte, Luca De Vito, Francesco Picariello, Sergio Rapuano	A Cyclostationarity-Based Method for Jitter Measurement in Waveform Recorders.	IEEE Trans. Instrum. Meas.	2018	DBLP DOI BibTeX RDF
12	Nobutaro Shibata, Mitsuo Nakamura	An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
12	Yusong Qiu, Lei Zhao, Feng Zhang	Design of 0.35-ps RMS Jitter 4.4-5.6-GHz Frequency Synthesizer with Adaptive Frequency Calibration Using 55-nm CMOS Technology.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
12	Shamim Sadrafshari, Razieh Eskandari, Khayrollah Hadidi, Abdollah Khoei	Low-jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
12	Jin Wu, Youzhi Zhang 0003, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun	Low-jitter DLL applied for two-segment TDC.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
12	Mike R. Jeffrey, Georgios Kafanas, David J. W. Simpson	Jitter in Piecewise-Smooth Dynamical Systems with Intersecting Discontinuity Surfaces.	Int. J. Bifurc. Chaos	2018	DBLP DOI BibTeX RDF
12	Salim Kalla, Riadh Hocine, Hamoudi Kalla, Abderrezak Chouki	Graceful degradation for reducing jitter of battery life in fault-tolerant embedded systems.	Int. J. Syst. Sci.	2018	DBLP DOI BibTeX RDF
12	Keonsoo Lee, Chanki Moon, Yunyoung Nam	Diagnosing Vocal Disorders using Cobweb Clustering of the Jitter, Shimmer, and Harmonics-to-Noise Ratio.	KSII Trans. Internet Inf. Syst.	2018	DBLP DOI BibTeX RDF
12	Anna Minaeva, Benny Akesson, Zdenek Hanzálek, Dakshina Dasari	Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
12	Krzysztof Krejtz, Andrew T. Duchowski, Heng Zhou, Sophie Jörg, Anna Niedzielska	Perceptual evaluation of synthetic gaze jitter.	Comput. Animat. Virtual Worlds	2018	DBLP DOI BibTeX RDF
12	Klodjan Bidaj, Jean-Baptiste Bégueret, Jerome Deroo	Jitter definition, measurement, generation, analysis, and decomposition.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
12	Motahhareh Estebsari, Mohammad Gholami, Mohammad Javad Ghahramanpour	A wide range delay locked loop for low power and low jitter applications.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
12	Dominique Dehay, Anna E. Dudek, Mohamed El Badaoui	Bootstrap for almost cyclostationary processes with jitter effect.	Digit. Signal Process.	2018	DBLP DOI BibTeX RDF
12	Sophie Jörg, Andrew T. Duchowski, Krzysztof Krejtz, Anna Niedzielska	Perceptual Adjustment of Eyeball Rotation and Pupil Size Jitter for Virtual Characters.	ACM Trans. Appl. Percept.	2018	DBLP DOI BibTeX RDF
12	Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma	Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
12	Zhan Shi, Lan Luo, Menglei Lei, Tao Su	A model for the jitter of a ring oscillator under sinusoidal interference on the power supply.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
12	Divya Chitimalla, Koteswararao Kondepu, Luca Valcarenghi, Massimo Tornatore, Biswanath Mukherjee	5G fronthaul-latency and jitter studies of CPRI over ethernet.	CoRR	2018	DBLP BibTeX RDF
12	Federico Terraneo, Fabiano Riccardi, Alberto Leva	Jitter-compensated VHT and its application to WSN clock synchronization.	CoRR	2018	DBLP BibTeX RDF
12	Shahbaz Rezaei, Ali Mohammad Afshin Hemmatyar	Study of Uniform Jitter Mechanism for Metric-based Wireless Routing.	CoRR	2018	DBLP BibTeX RDF
12	Shuilong He, Binqiang Chen, Zhansi Jiang, Yanxue Wang, Fuyun Liu	Control of steering wheel idle jitter based on optimization of engine suspension system with verifications using multi-sensor measurement.	Int. J. Distributed Sens. Networks	2018	DBLP DOI BibTeX RDF