Search results for "crossbar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Daniel C. Fielder, Cecil O. Alford	Counting Broadcast Conversations on a Completely Utilized Crossbar System.	Applied Informatics	1994	DBLP BibTeX RDF
15	Mohammed Atiquzzaman, Mohammad M. Banat	Effect of Hot-Spots on the Performance of Crossbar Multiprocessor Systems.	Parallel Comput.	1993	DBLP DOI BibTeX RDF
15	Steve W. Fuhrmann	Performance of a packet switch with crossbar architecture.	IEEE Trans. Commun.	1993	DBLP DOI BibTeX RDF
15	A. J. Field, Peter G. Harrison	Transmission Times in Buffered Full-Crossbar Communication Networks With Cyclic Arbitration.	ICPP (1)	1993	DBLP DOI BibTeX RDF
15	Joydeep Ghosh, Nari Krishnamurthy	Fault-Tolerant Arbitration in Multichip Crossbar Switches.	VLSI Design	1993	DBLP DOI BibTeX RDF
15	Barry Wilkinson	On Crossbar Switch and Multiple Bus Interconnection Networks with Overlapping Connectivity.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	multiple bus interconnection networks, overlapping connectivity, overlapping connectivity networks, multiprocessor interconnection networks, neural computers, dataflow computers
15	Ora E. Percus, Susan R. Dickey	Performance Analysis of Clock-Regulated Queues with Output Multiplexing in Three Different 2 x 2 Crossbar Switch Architectures.	J. Parallel Distributed Comput.	1992	DBLP DOI BibTeX RDF
15	Bernhard Quatember	Concept of a crossbar switch for large-scale multiple processor systems in the field of process control.	Parallel Comput.	1992	DBLP DOI BibTeX RDF
15	K. T. Sun, Hsin-Chia Fu	A Neural Network Implementation for the Traffic Control Problem on Crossbar Switch Networks.	Int. J. Neural Syst.	1992	DBLP DOI BibTeX RDF
15	Paul A. Stirpe, Eugene Pinsky	Performance Analysis of an Asynchronous Multi-Rate Crossbar with Bursty Traffic.	SIGCOMM	1992	DBLP DOI BibTeX RDF
15	Kyusun Choi, William S. Adams	VLSI Implementation of a 256 x 256 Crossbar Interconnection Network.	IPPS	1992	DBLP DOI BibTeX RDF
15	Andrew J. DuBois, John Rasure	Design and evaluation of a distributed asynchronous VLSI crossbar switch controller for a packet switched supercomputer network.	SIGARCH Comput. Archit. News	1991	DBLP DOI BibTeX RDF
15	Thomas Beth, Volker Hatz	A restricted crossbar implementation and its applications.	SIGARCH Comput. Archit. News	1991	DBLP DOI BibTeX RDF
15	K. T. Sun, Hsin-Chia Fu	An O(n) Parallel Algorithm for Solving the traffic control Problem on Crossbar Switch Networks.	Parallel Process. Lett.	1991	DBLP DOI BibTeX RDF
15	Eugene Pinsky, Paul A. Stirpe	Modeling and Analysis of "Hot Spots" in an Asynchronous NxN Crossbar Switch.	ICPP (1)	1991	DBLP BibTeX RDF
15	Barry Wilkinson	Cascaded Rhombic Crossbar Interconnection Networks.	J. Parallel Distributed Comput.	1990	DBLP DOI BibTeX RDF
15	Abdou Youssef, Bruce W. Arden	A New Approach to Fast Control of r2 x r2 3-Stage Benes Networks of r x r Crossbar Switches.	ISCA	1990	DBLP DOI BibTeX RDF
15	Daniel Litaize, Omar Hammami, Mustapha Lalam, Abdelaziz Mzoughi, Pascal Sainrat	Multiprocessors with a serial multiport memory and a pseudo crossbar of serial links used s a processor-memeory switch.	SIGARCH Comput. Archit. News	1989	DBLP DOI BibTeX RDF
15	Alastair D. McAulay	Conjugate Gradients on Optical Crossbar Interconnected Multiprocessor.	J. Parallel Distributed Comput.	1989	DBLP DOI BibTeX RDF
15	Yu-cheng Liu, Chungching Wang	Analysis of Prioritized Crossbar Multiprocessor Systems.	J. Parallel Distributed Comput.	1989	DBLP DOI BibTeX RDF
15	Randy Hoebelheinrich, Richard Thomsen	Multiple crossbar network integrated supercomputing framework.	SC	1989	DBLP DOI BibTeX RDF
15	William F. Hedberg	The multiple crossbar network interface.	LCN	1989	DBLP DOI BibTeX RDF
15	Randy Hoebelheinrich, Richard Thomsen	Multiple crossbar network-a switched high speed local network.	LCN	1989	DBLP DOI BibTeX RDF
15	Robert F. Miracky, A. Hartmann, L. N. Smith, S. Redfield, U. Ghoshal, B. Weigler	Design of a 64-processor by 128-memory crossbar switching network.	ICCD	1988	DBLP DOI BibTeX RDF
15	Alexander A. Sawchuk, Bob K. Jenkins, Cauligi S. Raghavendra, Anujan Varma	Optical Crossbar Networks.	Computer	1987	DBLP DOI BibTeX RDF
15	Alexander A. Sawchuk, Bob K. Jenkins, Anujan Varma, Cauligi S. Raghavendra	Optical Matrix-Vector Implementation of Crossbar Interconnection Networks.	ICPP	1986	DBLP BibTeX RDF
15	Ted H. Szymanski	A VLSI Comparison of Switch-Recursive Banyan and Crossbar Interconnection Networks.	ICPP	1986	DBLP BibTeX RDF
15	Manoj Kumar, J. Robert Jump	Performance enhancement in buffered delta networks using crossbar switches and multiple links.	J. Parallel Distributed Comput.	1984	DBLP DOI BibTeX RDF
15	Clifford L. Hall	A microcoded multiprocessor crossbar network communications controller.	MICRO	1984	DBLP BibTeX RDF
15	George Broomell, J. Robert Heath	An Integrated-Circuit Crossbar Switching System Design.	ICDCS	1984	DBLP BibTeX RDF
15	Sanjay Dhar, Mark A. Franklin, Donald F. Wann	Timing Control of VLSI Based NlogN and Crossbar Networks.	ICPP	1983	DBLP BibTeX RDF
15	Tomás Lang, Mateo Valero, Ignacio Alegre	Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	multiprocessors, shared memory, memory bandwidth, Bus arbitration, multiple buses
15	Tian-Pong Chang, Yung-Ming Yu	A Comparative Study of Crossbar-Structured Multiprocessor Systems.	IMACS World Congress	1982	DBLP BibTeX RDF
15	Angelo C. Hung, Miroslaw Malek	A 4x4 Modular Crossbar Design for the Multistage Interconnection Networks.	RTSS	1981	DBLP BibTeX RDF
15	Anne A. Robrock	Increasing the Capacity of the No. 4A Crossbar.	IEEE Trans. Commun.	1979	DBLP DOI BibTeX RDF
15	Nicholas Pippenger	On Crossbar Switching Networks.	IEEE Trans. Commun.	1975	DBLP DOI BibTeX RDF
15	Harry A. Guess	The effect of frame load and balance on dial-tone dealy in no. 5 crossbar.	Bell Syst. Tech. J.	1975	DBLP DOI BibTeX RDF
10	Ken-ichi Kawarabayashi, Bruce A. Reed	Odd cycle packing.	STOC	2010	DBLP DOI BibTeX RDF	odd cycle, packing
10	Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy	Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.	ISCA	2010	DBLP DOI BibTeX RDF	interconnection networks, nanophotonics
10	Yiyuan Xie, Mahdi Nikdast, Jiang Xu 0001, Wei Zhang 0012, Qi Li 0013, Xiaowen Wu, Yaoyao Ye, Xuan Wang 0001, Weichen Liu	Crosstalk noise and bit error rate analysis for optical network-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	optical network-on-chip, crosstalk, BER, SNR
10	Kai Zhang 0025, Xinming Huang 0001, Zhongfeng Wang	High-throughput layered decoder implementation for quasi-cyclic LDPC codes.	IEEE J. Sel. Areas Commun.	2009	DBLP DOI BibTeX RDF
10	Ken-ichi Kawarabayashi, Bruce A. Reed	A nearly linear time algorithm for the half integral parity disjoint paths packing problem.	SODA	2009	DBLP DOI BibTeX RDF
10	John Kim	Low-cost router microarchitecture for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	router microarchitecture, complexity, on-chip network
10	Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha	GARNET: A detailed on-chip network model inside a full-system simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
10	Gagan Raj Gupta, Sujay Sanghavi, Ness B. Shroff	Node weighted scheduling.	SIGMETRICS/Performance	2009	DBLP DOI BibTeX RDF	scheduling, switch, bipartite matching, fluid limits
10	Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi	A Novel Local Interconnect Architecture for Variable Grain Logic Cell.	ARC	2009	DBLP DOI BibTeX RDF
10	Pinaki Mazumder	Disruptive technologies and neurally-inspired architectures.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	glsvlsi 2009 invited talk
10	Hamid Hajabdolali Bazzaz, Marjan Sirjani, Ramtin Khosravi, Shamim Taheri	Modeling networking issues of network-on-chip: a coloured petri nets approach.	SimuTools	2009	DBLP DOI BibTeX RDF	modeling, network-on-chip, coloured petri nets
10	Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi	Phastlane: a rapid transit optical routing network.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, multicore, optical interconnects, nanophotonics
10	David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester	Vicis: a reliable network for unreliable silicon.	DAC	2009	DBLP DOI BibTeX RDF	hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy
10	Juan José Jaramillo, Fabio Milan, R. Srikant 0001	Padded frames: a novel algorithm for stable scheduling in load-balanced switches.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	Birkhoff-von Neumann switch, load-balanced switch, scheduling
10	Ilias Iliadis, Cyriel Minkenberg	Performance of a speculative transmission scheme for scheduling-latency reduction.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	electrooptic switches, scheduling, modeling, packet switching, arbiters
10	Yariv Aridor, Tamar Domany, Oleg Goldshmidt, Yevgeny Kliteynik, Edi Shmueli, José E. Moreira	Multitoroidal Interconnects For Tightly Coupled Supercomputers.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF	parallel architectures, network topology, scheduling and task partitioning
10	Jay Cheng	Constructions of Optical 2-to-1 FIFO Multiplexers With a Limited Number of Recirculations.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
10	Paolo Giaccone, Emilio Leonardi	Asymptotic Performance Limits of Switches With Buffered Crossbars Supporting Multicast Traffic.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
10	Xike Li, Itamar Elhanany	Stability of a frame-based oldest-cell-first maximal weight matching algorithm.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
10	Abbas Eslami Kiasari, Dara Rahmati, Hamid Sarbazi-Azad, Shaahin Hessabi	A Markovian Performance Model for Networks-on-Chip.	PDP	2008	DBLP DOI BibTeX RDF
10	Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley	Efficient tiling patterns for reconfigurable gate arrays.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA hexagonal octagonal, tiling interconnect
10	Christian Fensch, Marcelo Cintra	An OS-based alternative to full hardware coherence on tiled CMPs.	HPCA	2008	DBLP DOI BibTeX RDF
10	Xiangjie Ma, Lei He 0008, Xiaozhuo Gu, Julong Lan, Baisheng Zhang	Study on a Novel Scheduling Algorithm ofthe Multiple-Plane and Multiple-Stage Switching Fabric.	HPCC	2008	DBLP DOI BibTeX RDF
10	Ricardo S. Ferreira 0001, Marcone Laure, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro	Reducing interconnection cost in coarse-grained dynamic computing through multistage network.	FPL	2008	DBLP DOI BibTeX RDF
10	Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Lei Zhang 0014, Yulu Yang, Enyue Lu, Xiao-chun Yun	Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs.	ITNG	2008	DBLP DOI BibTeX RDF	PRDT, router, NoC
10	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	DiCo-CMP: Efficient cache coherency in tiled CMP architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
10	Huaxi Gu, Jiang Xu 0001, Zheng Wang	ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	microresonator, low power, network on chip, optical interconnect, router architecture, loss
10	Theodore W. Manikas, Dale Teeters	Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells.	ISMVL	2008	DBLP DOI BibTeX RDF	electrochemical cells, memory, nanotechnology, multiple-valued logic
10	Valeriu Beiu, Walid Ibrahim	Does the brain really outperform Rent's rule?	ISCAS	2008	DBLP DOI BibTeX RDF
10	Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy 0001, Ranjani Narayan	RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.	ASAP	2008	DBLP DOI BibTeX RDF
10	Narayan Desai, Pavan Balaji, P. Sadayappan, Mohammad Islam	Are nonblocking networks really needed for high-end-computing workloads?	CLUSTER	2008	DBLP DOI BibTeX RDF
10	Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi	Impact of topology and link aggregation on a PC cluster with Ethernet.	CLUSTER	2008	DBLP DOI BibTeX RDF
10	Paolo Giaccone, Emilio Leonardi, Devavrat Shah	Throughput Region of Finite-Buffered Networks.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	flow-controlled networks, scheduling, packet switching, Queuing theory, buffered crossbars
10	Reza M. Rad, Mohammad Tehranipoor	Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	performance, FPGA, reliability, CMOS, Nanotechnology
10	Alexander Kesselman, Kirill Kogan	Nonpreemptive Scheduling of Optical Switches.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
10	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.	DSN	2007	DBLP DOI BibTeX RDF
10	Elisabeth Pelz, Dietmar Tutsch	Formal Models for Multicast Traffic in Network on Chip Architectures with Compositional High-Level Petri Nets.	ICATPN	2007	DBLP DOI BibTeX RDF
10	Luciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli	NoC Topologies Exploration based on Mapping and Simulation Models.	DSD	2007	DBLP DOI BibTeX RDF
10	Andrew Lines	The Vortex: A Superscalar Asynchronous Processor.	ASYNC	2007	DBLP DOI BibTeX RDF
10	Mitsuhisa Sato	Bandwidth-Aware Design of Large-Scale Clusters for Scientific Computations.	HPCC	2007	DBLP DOI BibTeX RDF
10	Yi Dai, Jinshu Su, Zhigang Sun, Jianbo Guan	A Uniform Fine-Grain Frame Spreading Algorithm for Avoiding Packet Reordering in Load-Balanced Switches.	APSCC	2007	DBLP DOI BibTeX RDF
10	Michele Favalli	Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth.	DFT	2007	DBLP DOI BibTeX RDF
10	Nikolaos Chrysos	Congestion management for non-blocking clos networks.	ANCS	2007	DBLP DOI BibTeX RDF
10	Bill Lin 0001, Isaac Keslassy	Frame-aggregated concurrent matching switch.	ANCS	2007	DBLP DOI BibTeX RDF	100% throughput, concurrent matching switch, frame scheduling, load-balanced router, packet switching
10	Hiroshi Wakuya, Mari Miyazaki	A Study on Scheduling Function of a Magnetic Parameter in a Virtual Magnetic Diminuendo Method.	ICONIP (2)	2007	DBLP DOI BibTeX RDF
10	Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	Low-power network-on-chip for high-performance SoC design.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	Wai Hong Ho, Timothy Mark Pinkston	A Design Methodology for Efficient Application-Specific On-Chip Interconnects.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	low-contention communication, network partitioning, communication model, On-chip interconnects, irregular topology
10	Cheng-Shang Chang, Duan-Shin Lee, Chao-Kai Tu	Using switched delay lines for exact emulation of FIFO multiplexers with variable length bursts.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
10	John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, Yue Wu	Radial addressing of nanowires.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Addressing schemes, core-shell nanowires, nanowire crossbars, nanotechnology
10	Eryk Laskowski, Marek Tudruj	Assessment of Dynamic Look-Ahead Inter-Processor Connection Reconfiguration for Different Control Paradigms.	ISPDC	2006	DBLP DOI BibTeX RDF
10	Mohammad Tehranipoor, Reza M. Rad	Fine-grained island style architecture for molecular electronic devices.	FPGA	2006	DBLP DOI BibTeX RDF
10	Dmitri B. Strukov, Konstantin K. Likharev	A reconfigurable architecture for hybrid CMOS/Nanodevice circuits.	FPGA	2006	DBLP DOI BibTeX RDF	integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect
10	Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo	Contrasting a NoC and a traditional interconnect fabric with layout awareness.	DATE	2006	DBLP DOI BibTeX RDF
10	Hongyun Zheng, Yongxiang Zhao, Changjia Chen	Design and Implementation of Switches in Network Simulator (ns2).	ICICIC (1)	2006	DBLP DOI BibTeX RDF
10	Rick Janda, Wolfgang E. Nagel, Bernd Trenkler	Analyzing the Interaction of OpenMP Programs Within Multiprogramming Environments on a Sun Fire E25K System with PARbench.	Euro-Par	2006	DBLP DOI BibTeX RDF
10	Wolfgang Heenes, Rolf Hoffmann, Johannes Jendrsczok	A multiprocessor architecture for the massively parallel model GCA.	IPDPS	2006	DBLP DOI BibTeX RDF
10	Hubert Ritzdorf, Jesper Larsson Träff	Collective operations in NEC's high-performance MPI libraries.	IPDPS	2006	DBLP DOI BibTeX RDF
10	Charles L. Cathey, Jason D. Bakos, Duncan A. Buell	A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism.	FCCM	2006	DBLP DOI BibTeX RDF
10	Igor Radusinovic, Zoran Veljovic	Performance analysis of Exhaustive Limited Service Round Robin Matching Algorithm.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
10	Eric Rachlin, John E. Savage	Nanowire addressing with randomized-contact decoders.	ICCAD	2006	DBLP DOI BibTeX RDF
10	Deng Pan, Yuanyuan Yang 0001	Hardware Efficient Two Step Iterative Matching Algorithms for VOQ Switches.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
10	Taisuke Boku, Mitsuhisa Sato, Akira Ukawa, Daisuke Takahashi, Shinji Sumimoto, Kouichi Kumon, Takashi Moriyama, Masaaki Shimizu	PACS-CS: A Large-Scale Bandwidth-Aware PC Cluster for Scientific Computations.	CCGRID	2006	DBLP DOI BibTeX RDF
10	Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano	Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet.	ICPP	2006	DBLP DOI BibTeX RDF