Search results for "crossbar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi	Architecture - The potential energy efficiency of vector acceleration.	SC	2006	DBLP DOI BibTeX RDF
10	Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa	Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Reza M. Rad, Mohammad Tehranipoor	A new hybrid FPGA with nanoscale clusters and CMOS routing.	DAC	2006	DBLP DOI BibTeX RDF	reconfigurable nanoscale devices, FPGA, molecular electronics
10	Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun	Niagara: A 32-Way Multithreaded Sparc Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Microprocessors and microcomputers, Shared memory, Multithreaded processors
10	Aneesh Aggarwal, Manoj Franklin	Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Clustered processor architecture, pipeline processors, interconnection architectures, load balancing and task assignment
10	Junzhou Luo, Yong Lee 0003, Jun Wu 0002	DRR A Fast High-Throughput Scheduling Algorithm for Combined Input Crosspoint-Queued CICQ Switches.	MASCOTS	2005	DBLP DOI BibTeX RDF
10	Eric Rachlin, John E. Savage, Benjamin Gojman	Analysis of a Mask-Based Nanowire Decoder.	ISVLSI	2005	DBLP DOI BibTeX RDF
10	Yanfeng Zheng, Simin He 0001, Shutao Sun, Wen Gao 0001	Parallelized scheduling algorithm for input queued switches using local search technique.	IPCCC	2005	DBLP DOI BibTeX RDF
10	Siu-Cheung Chau, Tiehong Xiao, Ada Wai-Chee Fu	Routing and Scheduling for a Novel Optical Multistage Interconnection Network.	Euro-Par	2005	DBLP DOI BibTeX RDF
10	Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen	The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.	FCCM	2005	DBLP DOI BibTeX RDF
10	Igor Radusinovic, Zoran Veljovic	New Round-Robin Scheduling Algorithm for Combined Input-Crosspoint Buffered Switch.	ICN (1)	2005	DBLP DOI BibTeX RDF
10	Paolo Giaccone, Emilio Leonardi, Devavrat Shah	On the maximal throughput of networks with finite buffers and its application to buffered crossbars.	INFOCOM	2005	DBLP DOI BibTeX RDF
10	Jing Qu, Ximing Hu, Peng Yi, Xingming Zhang 0002, Binqiang Wang	A High-Performance Scheduling Algorithm Based on Packet Sto.	SKG	2005	DBLP DOI BibTeX RDF
10	Yanfeng Zheng, Chun Shao	An Efficient Round-Robin Algorithm for Combined Input-Crosspoint-Queued Switches.	ICAS/ICNS	2005	DBLP DOI BibTeX RDF
10	Bin Tang	On multicast scheduling and routing in multistage Clos networks.	AICCSA	2005	DBLP DOI BibTeX RDF
10	Rakesh Kumar 0002, Victor V. Zyuban, Dean M. Tullsen	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.	ISCA	2005	DBLP DOI BibTeX RDF
10	Roger Su, Raman Mittal, Vivek Garg	Synchronous Pipelined Relay Stations with Back-Pressure Tolerance.	IWSOC	2005	DBLP DOI BibTeX RDF
10	Andrew Lines	Asynchronous Interconnect for Synchronous SoC Design.	IEEE Micro	2004	DBLP DOI BibTeX RDF
10	Constantine Katsinis, Bahram Nabet	A Scalable Interconnection Network Architecture for Petaflops Computing.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	petaflops computing, performance analysis, interconnection networks, computer architecture
10	Yuanyuan Yang 0001, Jianchao Wang	Fault-Tolerant Rearrangeable Permutation Network.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	losing-contact fault, Fault tolerance, routing, cluster computing, fault model, permutation, switching networks, Clos networks, rearrangeable
10	Cheng-Shang Chang, Duan-Shin Lee, Chao-Kai Tu	Recursive construction of FIFO optical multiplexers with switched delay lines.	IEEE Trans. Inf. Theory	2004	DBLP DOI BibTeX RDF
10	Leonardo R. Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, T. J. Christopher Ward	A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design.	IEEE PACT	2004	DBLP DOI BibTeX RDF
10	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv	A Case Study in Networks-on-Chip Design for Embedded Video.	DATE	2004	DBLP DOI BibTeX RDF
10	Rakesh Kumar 0002, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
10	Constantine Katsinis	A Model of Distributed-Shared-Memory on the SOME-Bus Architecture.	IPDPS	2004	DBLP DOI BibTeX RDF
10	Eryk Laskowski	Program Scheduling in Look-Ahead Reconfigurable Parallel Systems with Multiple Communication Resources.	PARELEC	2004	DBLP DOI BibTeX RDF
10	Jih-Fu Tu, Chih-Yung Chen	An Effective Bus-Band Arbiter for Processors Communication.	AINA (2)	2004	DBLP DOI BibTeX RDF	Bus-based arbitration circuit, multistage bus network (MBN), M-to-B Arbiter and inter-processor communication
10	Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao	Concurrent fault detection for a multiple-plane packet switch.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	parallel planes, fault detection, packet switch, concurrent testing, single fault
10	Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung	On optimal hyperuniversal and rearrangeable switch box designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Wai Hong Ho, Timothy Mark Pinkston	A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns.	HPCA	2003	DBLP DOI BibTeX RDF	Low-Contention Communication, Network Partitioning, Communication Model, On-chip Interconnects, Irregular Topology
10	Rajendra V. Boppana, Rajesh Boppana, Suresh Chalasani	Designing SANs to Support Low-Fanout Multicasts.	HiPC	2003	DBLP DOI BibTeX RDF
10	Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, David A. B. Miller, Mark Horowitz, Olav Solgaard, Nick McKeown	Scaling internet routers using optics.	SIGCOMM	2003	DBLP DOI BibTeX RDF	load-balancing, packet-switch, internet router
10	Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens	A modular simulation framework for architectural exploration of on-chip interconnection networks.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	simulation, network-on-chip, SystemC, architecture exploration
10	Hiroto Kagotani, Herman Schmit	Asynchronous PipeRench: Architecture and Performance Estimations.	FCCM	2003	DBLP DOI BibTeX RDF
10	Sangman Moh, Jae-Hong Shim, Yang-Dong Lee, Jeong-A Lee, Beom-Joon Cho	Design and Evaluation of a Cache Coherence Adapter for the SMP Nodes Interconnected via Xcent-Net.	ISCIS	2003	DBLP DOI BibTeX RDF
10	Tetsuya Sato, Hitoshi Murai, Shigemune Kitawaki	How Can the Earth Simulator Impact on Human Activities.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
10	Naoyuki Fujita, Hirofumi Ookawa	The GSN Library and FORTRAN Level I/O Benchmarks on the NS-III HPC System.	ISHPC	2003	DBLP DOI BibTeX RDF	I/O Benchmark, Scheduled Transfer Facility, Memory Copy, GSN, File Sharing
10	Matthew M. Ziegler, Mircea R. Stan	The CMOS/nano interface from a circuits perspective.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Neil J. Gunther, Kenneth J. Christensen, Kenji Yoshigoe	Characterization of the Burst Stabilization Protocol for the RR/RR CICQ Switch.	LCN	2003	DBLP DOI BibTeX RDF
10	Phil May, Santithorn Bunchua, D. Scott Wills	HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	mad postman, flit-level retransmission, Networks, energy efficient, wormhole routing, router, error control, dimension-order routing
10	Pedro Javier García, M. D. Mora, Francisco José Alfaro, José L. Sánchez 0002, José Flich	Evaluation of Alternative Arbitration Policies for Myrinet Switches.	IPDPS	2002	DBLP DOI BibTeX RDF	Performance, Myrinet, Arbitration, NOWs
10	Aneesh Aggarwal, Manoj Franklin	Hierarchical Interconnects for On-Chip Clustering.	IPDPS	2002	DBLP DOI BibTeX RDF	on-chip clustering, instruction distribution algo-rithms, Scalability, on-chip interconnect, Instruction-level parallelism (ILP)
10	Tetsuya Sato	Can the earth simulator change the way humans think?	ICS	2002	DBLP DOI BibTeX RDF
10	Matthew M. Ziegler, Mircea R. Stan	A Case for CMOS/nano co-design.	ICCAD	2002	DBLP DOI BibTeX RDF
10	Nian-Feng Tzeng, Malcolm Mandviwalla	Cost-Effective Switching Fabrics with Distributed Control for Scalable Routers.	ICDCS	2002	DBLP DOI BibTeX RDF
10	Satoru Shingu, Hiroshi Takahara, Hiromitsu Fuchigami, Masayuki Yamada, Yoshinori Tsuda, Wataru Ohfuchi, Yuji Sasaki, Kazuo Kobayashi, Takashi Hagiwara, Shinichi Habata, Mitsuo Yokokawa, Hiroyuki Itoh, Kiyoshi Otsuka	A 26.58 Tflops global atmospheric simulation with the spectral transform method on the Earth Simulator.	SC	2002	DBLP DOI BibTeX RDF
10	Luciano Lavagno, Sujit Dey, Rajesh K. Gupta 0001	Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract).	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
10	François Abel, Cyriel Minkenberg, Ronald P. Luijten, Mitchell Gusat, Ilias Iliadis	A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
10	Jing Liu, Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui	Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
10	Guy G. Lemieux, David M. Lewis	Using sparse crossbars within LUT.	FPGA	2001	DBLP DOI BibTeX RDF
10	Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III	A Comparison of Five Different Multiprocessor SoC Bus Architectures.	DSD	2001	DBLP DOI BibTeX RDF
10	Li-Shiuan Peh, William J. Dally	A Delay Model and Speculative Architecture for Pipelined Routers.	HPCA	2001	DBLP DOI BibTeX RDF
10	Santiago V. Lombeyda, Laurent Moll, Mark Shand, David E. Breen, Alan Heirich	Scalable interactive volume rendering using off-the-shelf components.	IEEE Symposium on Parallel and Large-Data Visualization and Graphics	2001	DBLP BibTeX RDF	VolumePro, shear-warp, sort-last, cluster, parallel, volume rendering, CFD, ray-casting, OpenGL, shadow mapping, VIA, Clos
10	Marco Ottavi, Gian Carlo Cardarilli, Panfilo Marinucci, Salvatore Pontarelli, Adelio Salsano	Development of a dynamic routing system for a fault tolerant solid state mass memory.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Ronald P. Luijten, Antonius P. J. Engbersen, Cyriel Minkenberg	Shared memory switching + virtual output queuing: A robust and scalable switch.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Wenzhe Cui, Hanseok Ko, Sunshin An	A Threshold Based Scheduling Algorithm for Input Queue Switch.	ICOIN	2001	DBLP DOI BibTeX RDF
10	Dinesh Bhatia, James Haralambides	Resource requirements and layouts for field programmable interconnection chips.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
10	Matthias Brehm, Reinhold Bader, Helmut Heller, Ralf Ebner 0001	Pseudovectorization, SMP, and Message Passing on the Hitachi SR8000-F1.	Euro-Par	2000	DBLP DOI BibTeX RDF
10	Maurizio A. Bonuccelli, Susanna Pelagatti	Optimal on Demand Packet Scheduling in Single-Hop Multichannel Communication Systems.	IPDPS	2000	DBLP DOI BibTeX RDF
10	Ravi R. Iyer 0001, Laxmi N. Bhuyan, Ashwini K. Nanda	Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors.	IPDPS	2000	DBLP DOI BibTeX RDF
10	Philippe Millet, Jean-Claude Heudin	Comparison between Three Heuristic Algorithms to Repair a Large-Scale MIMD Computer.	ICES	2000	DBLP DOI BibTeX RDF
10	Keiji Tani	Earth Simulation Project in Japan - Seeking a Guide Line for the Symbiosis between the Earth and Human Beings - Visualizing an Aspect of the Future of the Earth by a Supercomputer.	ISHPC	2000	DBLP DOI BibTeX RDF
10	Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi	Design of OTA Based Field Programmable Analog Array.	VLSI Design	2000	DBLP DOI BibTeX RDF	Operational Transconductance Amplifier(OTA), Amplitude Modulation (AM), Frequency Modulation (FM)
10	Edward E. E. Frietman, Ramon J. Ernst, Roy E. Crosbie, Masao Shimoji	Prospects for Optical Interconnects in Distributed, Shared-Memory Organized MIMD Architectures.	J. Supercomput.	1999	DBLP DOI BibTeX RDF	free space data distributing system, fully connected topology, multi-stage interconnection scheme, opto electronic logic elements, photonic integrated circuits, distributed-shared memory systems
10	Hasan Cam, José A. B. Fortes	Work-Efficient Routing Algorithms for Rearrangeable Symmetrical Networks.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	Rearrangeable symmetrical network, parallel routing algorithm, work-efficient PRAM algorithm, balanced matrix, permutations, frame, Benes network
10	Rajendra V. Boppana, Suresh Chalasani	Fault-Tolerant Communication with Partitioned Dimension-Order Routers.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	Cray T3D router, dimension-order router, wormhole routing, fault-tolerant routing, message routing, torus networks, multicomputer networks
10	Wissam Hlayhel, Jacques Henri Collet, Laurent Fesquet	Implementing Snoop-Coherence Protocol for Future SMP Architectures.	Euro-Par	1999	DBLP DOI BibTeX RDF
10	David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow	The Transmogrifier-2: a 1 million gate rapid-prototyping system.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
10	Kimberly Keeton, David A. Patterson 0001, Joseph M. Hellerstein	A Case for Intelligent Disks (IDISKs).	SIGMOD Rec.	1998	DBLP DOI BibTeX RDF
10	Jesús Corbal, Roger Espasa, Mateo Valero	Command Vector Memory Systems: High Performance at Low Cost.	IEEE PACT	1998	DBLP DOI BibTeX RDF	memory systems, vector processors, SDRAM
10	Constantine Katsinis	Performance Analysis and Simulation of the SOME-Bus Architecture Using Message Passing.	ICCCN	1998	DBLP DOI BibTeX RDF	simulation, performance analysis, Interconnection networks
10	Hans Eberle, Erwin Oertli	Switcherland: A QoS Communication Architecture for Workstation Clusters.	ISCA	1998	DBLP DOI BibTeX RDF
10	Narayan Ranganathan, Manoj Franklin	An Empirical Study of Decentralized ILP Execution Models.	ASPLOS	1998	DBLP DOI BibTeX RDF	execution unit dependence, hardware window, instruction-level parallelism, data dependence, dynamic scheduling, speculative execution, control dependence, decentralization
10	Laxmi N. Bhuyan, Ravi R. Iyer 0001, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar	Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	routing, performance analysis, Interconnection network, packet-switching, queuing model, execution-driven simulation
10	Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang	Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
10	Yueming Hu	A Simulation Research on Multiprocessor Interconnection Networks With Wormhole Routing.	APDC	1997	DBLP DOI BibTeX RDF
10	Woo-Jong Hahn, Kee-Wook Rim, Soo-Won Kim	SPAX: A New Parallel Processing System for Commercial Application.	IPPS	1997	DBLP DOI BibTeX RDF	SPAX, commercial applications, Xcent-Net, 2.67 Gbyte/s, scalability, parallel architectures, bandwidth, SMP, hierarchical network, parallel processing system
10	Hiroaki Fujii, Yoshiko Yasuda, Hideya Akashi, Yasuhiro Inagami, Makoto Koga, Osamu Ishihara, Masamori Kashiyama, Hideo Wada, Tsutomu Sumimoto	Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System.	IPPS	1997	DBLP DOI BibTeX RDF
10	Edward E. E. Frietman, Ramon J. Ernst, Roy E. Crosbie, Masao Shimoji	Features of Optical Interconnects in Distributed-Shared Memory Organized MIMD Architectures: The Ultimate Goal.	ISPAN	1997	DBLP DOI BibTeX RDF	free space data distributing system, fully connect topology, multi-stage interconnection scheme, opto electronic logic elements, photonic integrated circuits, distributed-shared memory systems
10	Nader Mir-Fakhraei	ATM switching architectures for wafer-scale integration.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
10	Peter Steenkiste	Network-Based Multicomputers: A Practical Supercomputer Architecture.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	host-network interface, distributed programming, Multicomputer, high-speed network, workstation cluster, traffic characteristics
10	Mario Gerla, Prasasth Palnati, Simon Walton	Multicasting Protocols for High-Speed, Wormhole-Routing Local Area Networks.	SIGCOMM	1996	DBLP DOI BibTeX RDF
10	Thomas Garnatz, Ute Haack, Michael Sander, Wolfgang Schröder-Preikschat	Experiences Made with the Design and Development of a Message-Passing Kernel for a Dual-Processor-Node Parallel Computer.	HICSS (1)	1996	DBLP DOI BibTeX RDF
10	Vipul Gupta, Eugen Schenfeld	Annealed Embeddings of Communication Patterns in an Interconnection Cached Network.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	Interconnection cache, switching locality, latency reduction, reconfigurable parallel architectures, interconnection networks, simulated annealing, optical networks, process mapping
10	Friedhelm Meyer auf der Heide, Christian Scheideler, Volker Stemann	Exploiting Storage Redundancy to Speed Up Randomized Shared Memory Simulations.	STACS	1995	DBLP DOI BibTeX RDF
10	Ganesh Gopalakrishnan	Developing Micropipeline Wavefront Arbiters.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
10	Montse Peiron, Mateo Valero, Eduard Ayguadé	Synchronized access to streams in SIMD vector multiprocessors.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF	SIMD vector multiprocessors, multi-module memories, vectors with constant stride, interconnection networks, conflict-free access
10	Makoto Nakanishi, Hiroshi Ina, Ken'ichi Miura	A high performance linear equation solver on the VPP500 parallel supercomputer.	SC	1994	DBLP BibTeX RDF
10	Joseph Varghese, Michael Butts, Jon Batcheller	An efficient logic emulation system.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
10	Alok N. Choudhary, Janak H. Patel, Narendra Ahuja	NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	NETRA, partitionable architecture, tree-type control hierarchy, broadcast capability, block-level control, memorymanagement, scheduling, performance, computer vision, computer vision, load balancing, topology, SIMD, data flow, MIMD, multiprocessor architecture, CVS, hierarchical architecture, parallelarchitectures, Systolic, flexible architecture
10	Amnon Barak, Eugen Schenfeld	Embedding classical communication topologies in the OPAM architecture.	SPDP	1991	DBLP DOI BibTeX RDF
10	Thomas L. Rodeheffer, Michael D. Schroeder	Automatic Reconfiguration in Autonet.	SOSP	1991	DBLP DOI BibTeX RDF	ARPANET
10	John D. Garofalakis, Paul G. Spirakis	The Performance of Multistage Interconnection Networks with Finite Buffers.	SIGMETRICS	1990	DBLP DOI BibTeX RDF
10	Calvin Ching-Yuen Chen, Hee Yong Youn	A comprehensive modeling for performance evaluation of regular interconnection network.	SPDP	1990	DBLP DOI BibTeX RDF
10	Jürgen Sauermann	A Parallel APL Machine.	APL	1990	DBLP DOI BibTeX RDF	APL
10	Daniel Litaize, Fatimazhra Elkhlifi, Omar Hammami, Mustapha Lalam, Abdelaziz Mzoughi, Pascal Sainrat, Jean-Claude Salinier	Serial Multiport Memory Multiprocessors.	PARLE (1)	1989	DBLP DOI BibTeX RDF
10	Tomoo Fukazawa, Takashi Kimura, Masaaki Tomizawa, Kazumitsu Takeda, Yoshitaka Itoh	R256: A Research Parallel Processor for Scientific Computation.	ISCA	1989	DBLP DOI BibTeX RDF
10	James T. Blake, Andrew L. Reibman, Kishor S. Trivedi	Sensitivity Analysis of Reliability and Performability Measures for Multiprocessor Systems.	SIGMETRICS	1988	DBLP DOI BibTeX RDF
10	Naresh M. Patel, Peter G. Harrison	On Hot-Spot; Contention in Interconnection Networks.	SIGMETRICS	1988	DBLP DOI BibTeX RDF
10	Tam M. Nguyen, Vason P. Srini, Alvin M. Despain	A two-tier memory architecture for high-performance multiprocessor systems.	ICS	1988	DBLP DOI BibTeX RDF	Prolog, Prolog, CRAY X-MP