Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Hyunyoung Lee, Jennifer L. Welch	Randomized registers and iterative algorithms.	Distributed Comput.	2005	DBLP DOI BibTeX RDF	probabilistic quorums, randomization, distributed shared memory, iterative algorithms, registers
25	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Integrated On-Chip Storage Evaluation in ASIP Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
25	Vlad Petric, Tingting Sha, Amir Roth	RENO - A Rename-Based Instruction Optimizer.	ISCA	2005	DBLP DOI BibTeX RDF
25	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Exploring Storage Organization in ASIP Synthesis.	DSD	2003	DBLP DOI BibTeX RDF
25	Ilhyun Kim, Mikko H. Lipasti	Half-Price Architecture.	ISCA	2003	DBLP DOI BibTeX RDF
25	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Asymptotically Scalable Superscalar Processors.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
25	T. N. Vijaykumar, Irith Pomeranz, Karl Cheng	Transient-Fault Recovery Using Simultaneous Multithreading.	ISCA	2002	DBLP DOI BibTeX RDF
25	Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi	A new approach to built-in self-testable datapath synthesis based on integer linear programming.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
25	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
25	Hyunyoung Lee, Jennifer L. Welch	Specification, implementation and application of randomized regular registers (brief announcement).	PODC	2000	DBLP DOI BibTeX RDF
25	Fidel Muradali, Takao Nishida, Tsuguo Shimizu	A structure and technique for pseudorandom-based testing of sequential circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	distributed generator, Built-in self-test, design for test, pseudorandom generation, sequential test, weighted random patterns
25	Marina Papatriantafilou, Philippas Tsigas	How a Rainbow Coloring Function Can Simulate Wait-Free Handshaking.	MFCS	1994	DBLP DOI BibTeX RDF
25	Soma Chaudhuri, Mark R. Tuttle	Fast Increment Registers.	WDAG	1994	DBLP DOI BibTeX RDF
25	Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé	Using Sacks to Organize Registers in VLIW Machines.	CONPAR	1994	DBLP DOI BibTeX RDF
23	Yonghua Hu, Xin Zhang, Shuying Wang, Wei Liang 0005, Kuan-Ching Li	Research on global register allocation for code containing array-unit dual-usage register names.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
23	Yahia Idriss Benalioua, Nathan Lhote, Pierre-Alain Reynier	Register Minimization of Cost Register Automata over a Field.	CoRR	2023	DBLP DOI BibTeX RDF
23	Xianhua Liu 0001, Qinghong Yang, Miao Tao, Qinshu Chen, Xu Cheng	An Efficient Register Renaming Technique with Delayed Allocation and Register Packing.	ICECS	2020	DBLP DOI BibTeX RDF
23	Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa	Evaluation of Register Number Abstraction for Enhanced Instruction Register Files.	IEICE Trans. Inf. Syst.	2018	DBLP DOI BibTeX RDF
23	Ryoma Senda, Yoshiaki Takata, Hiroyuki Seki	Complexity Results on Register Context-Free Grammars and Register Tree Automata.	ICTAC	2018	DBLP DOI BibTeX RDF
23	Mohammad Sadrosadati, Amirhossein Mirhosseini, Seyed Borna Ehsani, Hamid Sarbazi-Azad, Mario Drumond, Babak Falsafi, Rachata Ausavarungnirun, Onur Mutlu	LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching.	ASPLOS	2018	DBLP DOI BibTeX RDF
23	Mohammad Abdel-Majeed, Alireza Shafaei, Hyeran Jeon, Massoud Pedram, Murali Annavaram	Pilot Register File: Energy Efficient Partitioned Register File for GPUs.	HPCA	2017	DBLP DOI BibTeX RDF
23	Abdulaziz Eker, Yakup Murat Mert, Oguz Ergin	URFA-Update based register file architecture with partial register write for energy efficiency.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
23	Suranjan Ganguly, Debotosh Bhattacharjee, Mita Nasipuri	Register-My-Face: a tool to register three-dimensional face images.	J. Electronic Imaging	2015	DBLP DOI BibTeX RDF
23	Hiroaki Kawashima, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo	Register Port Prediction for a Banked Register File.	CANDAR	2015	DBLP DOI BibTeX RDF
23	Chia-Han Lu, Wen-Li Shih, Chung-Ju Wu, Jenq Kuen Lee	Achieving spilling-friendly register file assignment for highly distributed register files.	J. Supercomput.	2014	DBLP DOI BibTeX RDF
23	Yiqun Wang, Hongyang Jia, Yongpan Liu, Qing'an Li, Chun Jason Xue, Huazhong Yang	Register allocation for hybrid register architecture in nonvolatile processors.	ISCAS	2014	DBLP DOI BibTeX RDF
23	Mohammad Abdel-Majeed, Murali Annavaram	Warped register file: A power efficient register file for GPGPUs.	HPCA	2013	DBLP DOI BibTeX RDF
23	Wann-Yun Shieh, Bo-Syun Wang	Power-aware register assignment for large register file design.	J. Supercomput.	2012	DBLP DOI BibTeX RDF
23	Hai Lin, Tiansi Hu, Yunsi Fei	A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
23	Ming-Yen Homh, Jen-Ming Wu	Vector Register Design with Register Bypassing for Embedded DSP Core.	HPCC-ICESS	2012	DBLP DOI BibTeX RDF
23	Eva Thors Adolfsson, Andreas Rosenblad	Reporting systems, reporting rates and completeness of data reported from primary healthcare to a Swedish quality register - The National Diabetes Register.	Int. J. Medical Informatics	2011	DBLP DOI BibTeX RDF
23	Xuan Guan, Yunsi Fei	Register file partitioning and recompilation for register file power reduction.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
23	Fakhar Anjam, Stephan Wong, Faisal Nadeem	A multiported register file with register renaming for configurable softcore VLIW processors.	FPT	2010	DBLP DOI BibTeX RDF
23	Wann-Yun Shieh, Shu-Yi Hsu	Power-Aware Register Assignment for Multi-Banked Register Files.	J. Inf. Sci. Eng.	2009	DBLP BibTeX RDF
23	Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee	LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files.	Concurr. Comput. Pract. Exp.	2009	DBLP DOI BibTeX RDF
23	Hui Zeng, Kanad Ghose, Dmitry Ponomarev 0001	Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures.	ICPP	2009	DBLP DOI BibTeX RDF
23	Zhihang Yu, Yong Yu 0001, Feilong Tang, Minyi Guo	A Register Framework for Network Processors with Banked Register File.	CISIS	2009	DBLP DOI BibTeX RDF
23	Wann-Yun Shieh, Chien-Chen Chen	Saving Register-File Leakage Energy by Register-usage Exploiting.	J. Inf. Sci. Eng.	2008	DBLP BibTeX RDF
23	Wann-Yun Shieh, Shu-Yi Hsu	Low Power Register File Design by Power Aware Register Assignment.	CDES	2008	DBLP BibTeX RDF
23	Wann-Yun Shieh, Chang-Yi Lee	Power-aware Register Renaming for Multi-banked Register Files.	ESA	2007	DBLP BibTeX RDF
23	Thomas Zeitlhofer, Bernhard Wess	List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures.	Signal Process.	2003	DBLP DOI BibTeX RDF
23	Jinpyo Park, Je-Hyung Lee, Soo-Mook Moon	Register Allocation for Banked Register File.	OM@PLDI	2001	DBLP DOI BibTeX RDF
23	Guido Araujo, Sharad Malik, Mike Tien-Chien Lee	Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures.	DAC	1996	DBLP DOI BibTeX RDF
23	Josep Llosa, Mateo Valero, Eduard Ayguadé	Non-Consistent Dual Register Files to Reduce Register Pressure.	HPCA	1995	DBLP DOI BibTeX RDF
23	K. Vidyasankar	Converting Lamport's Regular Register to Atomic Register.	Inf. Process. Lett.	1988	DBLP DOI BibTeX RDF
23	Ingrid Y. Bucher, Margaret L. Simmons	A Close Look at Vector Performance of Register-to-Register Vector Computers and a New Model.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
23	Tomás Lang, Miquel Huguet	Reduced register saving/restoring in single-window register files.	SIGARCH Comput. Archit. News	1986	DBLP DOI BibTeX RDF
23	Manfred Weber, Susan L. Bernstein	Global register allocation for non-equivalent register sets.	ACM SIGPLAN Notices	1980	DBLP DOI BibTeX RDF
22	Ivan D. Baev	Techniques for Region-Based Register Allocation.	CGO	2009	DBLP DOI BibTeX RDF	register allocation, region-based compilation
22	S. Subha	A Modified Linear Scan Register Allocation Algorithm.	ITNG	2009	DBLP DOI BibTeX RDF	Live range, Register allocation
22	Guilin Chen, Mahmut T. Kandemir, Mary Jane Irwin, J. Ramanujam	Reducing code size through address register assignment.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Software compilation, address registers, DSP, register assignment
22	Dennis K. Y. Tong, Evangeline F. Y. Young	Performance-driven register insertion in placement.	ISPD	2004	DBLP DOI BibTeX RDF	post-retiming, register insertion, placement
22	Yumin Zhang, Xiaobo Hu 0001, Danny Z. Chen	Efficient global register allocation for minimizing energy consumption.	ACM SIGPLAN Notices	2002	DBLP DOI BibTeX RDF	register allocation, low energy
22	Glenn Altemose, Cindy Norris	Register pressure responsive software pipelining.	SAC	2001	DBLP DOI BibTeX RDF	register allocation, software pipelining
22	Gang Chen, Michael D. Smith 0001	Reorganizing global schedules for register allocation.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF	superblock scheduling, instruction-level parallelism, register allocation
22	Christine Makowski, Lori L. Pollock	Achieving efficient register allocation via parallelism.	SAC	1995	DBLP DOI BibTeX RDF	cique separators, parallel register allocation, graph coloring
22	Alexandre E. Eichenberger, Edward S. Davidson	Register allocation for predicated code.	MICRO	1995	DBLP DOI BibTeX RDF	hyperblocks, interference, register allocation, software pipelining, predicated execution
22	Albrecht P. Stroele, Hans-Joachim Wunderlich	Test register insertion with minimum hardware cost.	ICCAD	1995	DBLP DOI BibTeX RDF	test register insertion, BILBO, CBILBO, Built-in self-test
22	Eric Sprangle, Yale N. Patt	Facilitating superscalar processing via a combined static/dynamic register renaming scheme.	MICRO	1994	DBLP DOI BibTeX RDF	superscalar processors, out-of-order execution, register renaming, predicated execution
22	Nazar S. Haider, Nick Kanopoulos	Efficient board interconnect testing using the split boundary scan register.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan
22	Yehuda Afek, Gideon Stupp	Synchronization power depends on the register size (Preliminary Version)	FOCS	1993	DBLP DOI BibTeX RDF	synchronization registers, register size, machine instructions, multiprocessors, space complexity, multiprocessor architectures, compare and swap, synchronization primitives, complexity hierarchy
22	Jacob Savir, William H. McAnney	A Multiple Seed Linear Feedback Shift Register.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	multiple seed linear feedback shift register, change-of-seeds, clock pulses, built-in self test, feedback, LFSR, shift registers
22	Randy Allen, Ken Kennedy	Vector Register Allocation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	vector register allocation, compiling vector languages, aggressive program transformations, parallel processing, program compilers, data dependence, supercomputers
22	Wei-Chung Hsu, Charles N. Fischer, James R. Goodman	On the Minimization of Loads/Stores in Local Register Allocation.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	local register allocation, program esptimization, Computer architecture
22	Vijay Pitchumani, Edward P. Stabler	Verification of Register Transfer Level Parallel Control Sequences.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	critical region, parallel control sequence, Assertion, register transfer level, shared resource, clock cycle, auxiliary variable, verification condition
22	Bella Bose, T. R. N. Rao	Unidirectional Error Codes for Shift-Register Memories.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Arithmetic residue check, unidirectional errors, parity check, shift register memories, information rate, asymmetric errors, symmetric errors
22	Yuval Tamir, Carlo H. Séquin	Strategies for Managing the Register File in RISC.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	VLSI processor, Cache fetch strategies, register file management, computer architecture, RISC, procedure calls
22	Vijay Pitchumani, Edward P. Stabler	An Inductive Assertion Method for Register Transfer Level Design Verification.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	inductive assertion method, synchronous logic, theorem proving, Assertions, predicate calculus, register transfer level design, verification condition
22	Gerhard Wustmann	Comments on "Autocorrelation Function of Sequential M-Bit Words Taken from an N-Bit Shift Register (PN) Sequence".	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	shift register sequence, autocovariance function, Autocorrelation function, PN sequence
22	Francis Y. L. Chin, K. Samson Fok	Fast Sorting Algorithms on Uniform Ladders (Multiple Shift-Register Loops).	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	uniform ladder, Bubble sort, Demuth's Algorithm, magnetic bubbles, odd-even transposition sort, shift-register loops, sorting, switches, merging, period, loading
22	Svetlana P. Kartashev, Steven I. Kartashev	On Modular Networks Satisfying the Shift-Register Rule.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	modular network, Augnentation of original program, interconnections satisfying shift-register rule, modular decomposition of programs, computer-aided design
22	Farhad Hemmati, Daniel J. Costello Jr.	An Algebraic Construction for q-ary Shift Register Sequences.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	shift register sequence, maximal length cycle, Euclidean Algorithm, Hamming weight
22	Werner E. Kluge	Traversing Binary Tree Structures with Shift-Register Memories.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Data permutations, traversal control, tree structures, shift-register memories, tree traversals
22	Harold Hoehne, Robert Piloty	Design Verification at the Register Transfer Language Level.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Compiler-interpreter system, computer description language, hardware design automation, register transfer language (RTL), simulation, error detection, design verification
22	Johannes Mykkeltveit	Generating and Counting the Double Adjacencies in a Pure Circulating Shift Register.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Adjacency diagram, adjacent cycles, binary cycle, de Bruijn graph, feedback shift register
22	Mario Barbacci	A Comparison of Register Transfer Languages for Describing Computers and Digital Systems.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	language properties, design automation, register transfer level, design languages, structural description, behavioral description, Asynchronous control
21	Matthias Braun 0003, Sebastian Hack	Register Spilling and Live-Range Splitting for SSA-Form Programs.	CC	2009	DBLP DOI BibTeX RDF
21	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose	Selective Writeback: Reducing Register File Pressure and Energy Consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
21	Hassan A. Salamy, J. Ramanujam	Optimal address register allocation for arrays in DSP applications.	ESTIMedia	2008	DBLP DOI BibTeX RDF
21	Shuo Wang, Fan Zhang 0010, Jianwei Dai, Lei Wang 0003, Zhijie Jerry Shi	Making register file resistant to power analysis attacks.	ICCD	2008	DBLP DOI BibTeX RDF
21	Weibo Xie, Fu Ting	Design and Implementation of the Virtual Machine Constructing on Register.	CSSE (2)	2008	DBLP DOI BibTeX RDF
21	Tzi-cker Chiueh	Fast Bounds Checking Using Debug Register.	HiPEAC	2008	DBLP DOI BibTeX RDF
21	Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton	Scalable min-register retiming under timing and initializability constraints.	DAC	2008	DBLP DOI BibTeX RDF	min-area, retiming, initial state, sequential optimization
21	Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek	Automatic Design Space Exploration of Register Bypasses in Embedded Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Youcef Bouchebaba, Bruno Girodias, Fabien Coelho, Gabriela Nicolescu, El Mostapha Aboulhamid	Buffer and Register Allocation for Memory Space Optimization.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	program transformation, memory hierarchy, data locality, memory optimization
21	Zeming Zhang, Wenjian Luo, Xufa Wang	Immune genetic programming based on register-stack structure.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
21	Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang 0009, Huimin Cui, Dongrui Fan	Optimized Register Renaming Scheme for Stack-Based x86 Operations.	ARCS	2007	DBLP DOI BibTeX RDF
21	Slavisa Jovanovic, Camel Tanougast, Serge Weber	A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems.	AHS	2007	DBLP DOI BibTeX RDF
21	Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha	Design Exploration With Imprecise Latency and Register Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Jianping Hu, Hong Li, Yangbo Wu	Low-Power Register File Based on Adiabatic Logic Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
21	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
21	Hiroshi Yamauchi, Jan Vitek	Combining Offline and Online Optimizations: Register Allocation and Method Inlining.	APLAS	2006	DBLP DOI BibTeX RDF
21	Lang Hames, Bernhard Scholz	Nearly Optimal Register Allocation with PBQP.	JMLC	2006	DBLP DOI BibTeX RDF
21	Li Shen 0002	VFSim: Concurrent Fault Simulation at Register Transfer Level.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling
21	Joep L. W. Kessels	Register Communication between Mutually Asynchronous Domains.	ASYNC	2005	DBLP DOI BibTeX RDF
21	Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu	Register placement for low power clock network.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	Il-Sun Hwang, Gi Sung Yoo, Jin-Wook Chung	Efficient Mobility Management Using Dynamic Location Register in IMT-2000 Networks.	KES (3)	2005	DBLP DOI BibTeX RDF
21	Siddhartha Shivshankar, Sunil Vangara, Alexander G. Dean	Balancing register pressure and context-switching delays in ASTI systems.	CASES	2005	DBLP DOI BibTeX RDF	asynchronous software thread integration, software-implemented-communication protocols, hardware to software migration, fine-grain concurrency
21	Keith D. Cooper, Anshuman Dasgupta, Jason Eckhardt	Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms.	LCPC	2005	DBLP DOI BibTeX RDF