Search results for "3DIC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Ephraim Suhir, Sung Yi	Predicted thermal stresses in a TSV design.	3DIC	2016	DBLP DOI BibTeX RDF
1	S. E. Kucuk Eroglu, W. Y. Choo, Yusuf Leblebici	Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique.	3DIC	2016	DBLP DOI BibTeX RDF
1	C. Hemanth Kumar, Asisa Kumar Panigrahi, Om Krishan Singh, Shiv Govind Singh	Noise performance improvement through optimized stacked layer of liner structure around the TSV in 3D IC.	3DIC	2016	DBLP DOI BibTeX RDF
1	Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne, Mohand Brouri, Praveen Nalla, Sanjay Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu	Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module.	3DIC	2016	DBLP DOI BibTeX RDF
1	Guillaume Berhault, Melanie Brocard, Sébastien Thuries, François Galea, Lilia Zaourar	3DIP: An iterative partitioning tool for monolithic 3D IC.	3DIC	2016	DBLP DOI BibTeX RDF
1	Kentaro Akiyama, Yusuke Oike, Yoshiaki Kitano, Junichiro Fjimagari, Wakiyama Satoru, Yorito Sakano, Takayuki Toyama, Hayato Iwamoto, Takayuki Ezaki, Takuya Nakamura, Tetsunori Imaizumi, Nonaka Yasuhiro	A front-illuminated stacked global-shutter CMOS image sensor with multiple chip-on-chip integration.	3DIC	2016	DBLP DOI BibTeX RDF
1	Hao-Wen Liang, Hsiu-Chi Chen, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen	The influence of device morphology on wafer-level bonding with polymer-coated layer.	3DIC	2016	DBLP DOI BibTeX RDF
1	Brian Mattis, Lovelace Soirez, Catherine Bullock, Dave Martini, Sara Jensen, James Levy, Adam Jones	Front-side mid-level Tungsten TSV integration for high-density 3D applications.	3DIC	2016	DBLP DOI BibTeX RDF
1	Suraj Patil, Asisa Kumar Panigrahi, Satish Bonam, C. Hemanth Kumar, Om Krishan Singh, Shiv Govind Singh	Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integration.	3DIC	2016	DBLP DOI BibTeX RDF
1	C. Roda Neve, Mikael Detalle, Philip Nolmans, Yunlong Li, Joeri De Vos, Geert Van der Plas, Gerald Beyer, Eric Beyne	High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.	3DIC	2016	DBLP DOI BibTeX RDF
1	Jaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey, Geraldine Jamieson, Fumihiro Inoue, Tomas Webers, Pieter Bex, Giovanni Capuz, Eric Beyne, John Slabbekoorn, Teng Wang, Anne Jourdain, Gerald Beyer, Kenneth June Rebibis, Andy Miller	Die to wafer 3D stacking for below 10um pitch microbumps.	3DIC	2016	DBLP DOI BibTeX RDF
1	Gerald Cibrario, Nour Ben Salem, Joris Lacord, Karim Azizi-Mourier, Olivier Rozeau, Etienne Maurin, Olivier Billoint, Sébastien Thuries, Alexandre Valentian	From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose.	3DIC	2016	DBLP DOI BibTeX RDF
1	Cristiano Santos, Pascal Vivet, Sébastien Thuries, Olivier Billoint, Jean-Philippe Colonna, Perceval Coudrain, Lee Wang	Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes.	3DIC	2016	DBLP DOI BibTeX RDF
1	Montserrat Fernandez-Bolaños, Wolfgang A. Vitale, Mariazel Maqueda Lopez, Adrian M. Ionescu, Armin Klumpp, Karl-Reinhard Merkel, Josef Weber, Peter Ramm, Ilja Ocket, Walter De Raedt, Amin Enayati	3D TSV based high frequency components for RF IC and RF MEMS applications.	3DIC	2016	DBLP DOI BibTeX RDF
1	Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi	3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions.	3DIC	2016	DBLP DOI BibTeX RDF
1	Kumail Khurram, Asisa Kumar Panigrahi, Satish Bonam, Om Krishan Singh, Shiv Govind Singh	Novel inter layer dielectric and thermal TSV material for enhanced heat mitigation in 3-D IC.	3DIC	2016	DBLP DOI BibTeX RDF
1	Gilad Yahalom, Stacy Ho, Alice Wang, Uming Ko, Anantha P. Chandrakasan	Analog-digital partitioning and coupling in 3D-IC for RF applications.	3DIC	2016	DBLP DOI BibTeX RDF
1	Suraj Singh, Asisa Kumar Panigrahi, Om Krishan Singh, Shiv Govind Singh	Analysis of graphene and CNT based finned TTSV and spreaders for thermal management in 3D IC.	3DIC	2016	DBLP DOI BibTeX RDF
1	Subin Kim, Youngwoo Kim, Kyungjun Cho, Jinwook Song, Joungho Kim	Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC.	3DIC	2016	DBLP DOI BibTeX RDF
1	Séverine Cheramy, Amadine Jouve, Lucile Arnaud, Claire Fenouillet-Béranger, Perrine Batude, Maud Vinet	Towards high density 3D interconnections.	3DIC	2016	DBLP DOI BibTeX RDF
1	Muhammad Waqas Chaudhary, Andy Heinig, Michael Dittrich	Interposer based integration to achieve high speed interfaces for ADC application.	3DIC	2016	DBLP DOI BibTeX RDF
1	Hantao Huang, Leibin Ni, Yuhao Wang 0002, Hao Yu 0001, Zongwei Wang, Yimao Cai, Ru Huang	A 3D multi-layer CMOS-RRAM accelerator for neural network.	3DIC	2016	DBLP DOI BibTeX RDF
1	Mariappan Murugesan, Jichel Bea, Takafumi Fukushima, Makoto Motoyoshi, Tetsu Tanaka, Mitsumasa Koyanagi	Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology.	3DIC	2016	DBLP DOI BibTeX RDF
1	William Wahby, Thomas E. Sarvey, Hardik Sharma, Hadi Esmaeilzadeh, Muhannad S. Bakir	The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study.	3DIC	2016	DBLP DOI BibTeX RDF
1	Yang Zhang, Xuchen Zhang, William Wahby, Muhannad S. Bakir	Design considerations for 2.5-D and 3-D integration accounting for thermal constraints.	3DIC	2016	DBLP DOI BibTeX RDF
1	Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura	Wet cleaning process for high-yield via-last TSV formation.	3DIC	2016	DBLP DOI BibTeX RDF
1	Yangyang Yan, Ziyue Zhang, Zhiqiang Cheng, Lingfeng Zhou, Zhiming Chen 0001, Yingtao Ding	Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias.	3DIC	2016	DBLP DOI BibTeX RDF
1	Rosa R. Lahiji, Timothy T. Lee, Warren P. Snapp	3D integration and challenges for advanced RF and microwave systems: EDA perspective.	3DIC	2016	DBLP DOI BibTeX RDF
1	Anne Jourdain, Joeri De Vos, Fumihiro Inoue, Kenneth J. Rebibis, Andy Miller, Gerald Beyer, Eric Beyne, Edward Walsby, Jash Patel, Oliver Ansell, Janet Hopkins, Huma Ashraf, Dave Thomas	Extreme wafer thinning optimization for via-last applications.	3DIC	2016	DBLP DOI BibTeX RDF
1	Reynard Blasa, Brian Mattis, Dave Martini, Sidi Lanee, Carl Petteway, Sangki Hong, Kangsoo Yi	High density backside tungsten TSV for 3D stacked ICs.	3DIC	2016	DBLP DOI BibTeX RDF
1	Fang Qiao, Ilgweon Kang, Daniel Kane 0001, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham	3D floorplan representations: Corner links and partial order.	3DIC	2016	DBLP DOI BibTeX RDF
1	Ye Lin, Chuan Seng Tan	Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage element.	3DIC	2016	DBLP DOI BibTeX RDF
1	Didier Lattard, Lucile Arnaud, Arnaud Garnier, Nicolas Bresson, Franck Bana, R. Segaud, Amadine Jouve, H. Jacquinot, Stéphane Moreau, Karim Azizi-Mourier, C. Chantre, Pascal Vivet, Gaël Pillonnet, F. Casset, F. Ponthenier, Alexis Farcy, S. Lhostis, Jean Michailos, Alexandre Arriordaz, Séverine Cheramy	ITAC: A complete 3D integration test platform.	3DIC	2016	DBLP DOI BibTeX RDF
1	Michael Scheuermann, Shurong Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip J. Restle, Joel Silberman, Christy Tyberg	Thermal analysis of multi-layer functional 3D logic stacks.	3DIC	2016	DBLP DOI BibTeX RDF
1	Kang Wook Lee 0002, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi	Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications.	3DIC	2016	DBLP DOI BibTeX RDF
1	Rafael Prieto, Perceval Coudrain, Jean-Philippe Colonna, Y. Hallez, Christian Chancel, V. Rat, Sylvain Dumas, G. Romano, R. Franiatte, C. Brunet-Manquiat, Séverine Cheramy, Alexis Farcy	Heat spreading packaging solutions for hybrid bonded 3D-ICs.	3DIC	2016	DBLP DOI BibTeX RDF
1	Luke England, Sukeshwar Kannan, Rahul Agarwal, Daniel Smith	Impact of TSV integration on 14nm FinFET device performance.	3DIC	2016	DBLP DOI BibTeX RDF
1	Joeri De Vos, Lan Peng, Alain Phommahaxay, Joost Van Ongeval, Andy Miller, Eric Beyne, Florian Kurz, Thomas Wagenleiter, Markus Wimplinger, Thomas Uhrmann	Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects.	3DIC	2016	DBLP DOI BibTeX RDF
1	Makoto Suwada, Kazuhiro Kanai	Considerations of TSV effects on next-generation super-high-speed transmission and power integrity design for 300A-class 2.5D and 3D package integration.	3DIC	2016	DBLP DOI BibTeX RDF
1	Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka	Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler.	3DIC	2016	DBLP DOI BibTeX RDF
1	Asisa Kumar Panigrahi, Satish Bonam, Tamal Ghosh, Siva Rama Krishna Vanjari, Shiv Govind Singh	Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integration.	3DIC	2016	DBLP DOI BibTeX RDF
1	Rosa R. Lahiji, Timothy T. Lee, Warren P. Snapp	3D integration and challenges for advanced RF and microwave systems: EDA perspective.	3DIC	2016	DBLP DOI BibTeX RDF
1	Yu-Tao Yang, Yu-Chen Hu, Kuan-Neng Chen	Reliability investigation and mechanism analysis for a novel bonding method of flexible substrate in 3D integration.	3DIC	2016	DBLP DOI BibTeX RDF
1	Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon	Physical design of a 3D-stacked heterogeneous multi-core processor.	3DIC	2016	DBLP DOI BibTeX RDF
1	Ryusuke Egawa, Wataru Uno, Masayuki Sato 0001, Hiroaki Kobayashi, Jubee Tada	A power-aware LLC control mechanism for the 3D-stacked memory system.	3DIC	2016	DBLP DOI BibTeX RDF
1	Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang Wook Lee 0002, Tetsu Tanaka, Mitsumasa Koyanagi	New concept of TSV formation methodology using Directed Self-Assembly (DSA).	3DIC	2016	DBLP DOI BibTeX RDF
1	Séverine Cheramy, Amandine Jouve, Lucile Arnaud, Claire Fenouillet-Béranger, Perrine Batude, Maud Vinet	Towards high density 3D interconnections.	3DIC	2016	DBLP DOI BibTeX RDF
1	Hideki Kitada, Hiroko Tashiro, Shoichi Miyahara, Takeshi Ishitsuka, Aki Dote, Shinji Tadaki, Tatsumi Nakada, Seiki Sakuyama	Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis.	3DIC	2016	DBLP DOI BibTeX RDF
1		2016 IEEE International 3D Systems Integration Conference, 3DIC 2016, San Francisco, CA, USA, November 8-11, 2016	3DIC	2016	DBLP BibTeX RDF
1	Tomoji Nakamura, Yoriko Mizushima, Young-Suk Kim, Ryuichi Sugie, Takayuki Ohba	Characterization of stress distribution in ultra-thinned DRAM wafer.	3DIC	2015	DBLP DOI BibTeX RDF
1	Cristiano Santos, Rafael Prieto, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Reis 0001	Graphite-based heat spreaders for hotspot mitigation in 3D ICs.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hyunsuk Lee, Kyungjun Cho, Heegon Kim, Sumin Choi, Jaemin Lim, Joungho Kim	Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module.	3DIC	2015	DBLP DOI BibTeX RDF
1	Subramanian S. Iyer	Invited talk: Some challenges in scaling 3D ICs to a broader application set.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Deprat, Alexandre Ayres De Sousa, Perrine Batude, Claire Fenouillet-Béranger, Fabien Clermidy	Intermediate BEOL process influence on power and performance for 3DVLSI.	3DIC	2015	DBLP DOI BibTeX RDF
1	Takahide Murayama, Yasuhiro Morikawa	TSV etching and VDP process integration for high reliability.	3DIC	2015	DBLP DOI BibTeX RDF
1	Armin Grünewald, Michael G. Wahl, Rainer Brück 0001	Cost modeling and analysis for the design, manufacturing and test of 3D-ICs.	3DIC	2015	DBLP DOI BibTeX RDF
1	Tung Thanh Bui 0001, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi	Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner.	3DIC	2015	DBLP DOI BibTeX RDF
1	Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy	3D advanced integration technology for heterogeneous systems.	3DIC	2015	DBLP DOI BibTeX RDF
1	Chuan-An Cheng, Ryuichi Sugie, Tomoyuki Uchida, Kou-Hua Chen, Chi-Tsung Chiu, Kuan-Neng Chen	Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration.	3DIC	2015	DBLP DOI BibTeX RDF
1	Noboru Asahi, Yoshinori Miyamoto, Masatsugu Nimura, Yoshihito Mizutani, Yoshiyuki Arai	High productivity thermal compression bonding for 3D-IC.	3DIC	2015	DBLP DOI BibTeX RDF
1	Rozalia Beica	3D integration: Applications and market trends.	3DIC	2015	DBLP DOI BibTeX RDF
1	Xin Wu	3D-IC technologies and 3D FPGA.	3DIC	2015	DBLP DOI BibTeX RDF
1	Gopi Neela, Jeffrey Draper	Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC.	3DIC	2015	DBLP DOI BibTeX RDF
1	Insu Hwang, Jihye Kim, Youngwoo Kim, Jonghyun Cho, Joungho Kim	Noise coupling modeling and analysis of through glass via(TGV).	3DIC	2015	DBLP DOI BibTeX RDF
1	Andy Heinig, Robert Fischbach	Enabling automatic system design optimization through Assembly Design Kits.	3DIC	2015	DBLP DOI BibTeX RDF
1	Robert Patti	Invited talk: Progress in 3D integrated circuits.	3DIC	2015	DBLP DOI BibTeX RDF
1	Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu	Electrical interconnect test method of 3D ICs by injected charge volume.	3DIC	2015	DBLP DOI BibTeX RDF
1	T. Robert Harris, Eric J. Wyers, Lee Wang, Samuel Graham, Georges Pavlidis, Paul D. Franzon, W. Rhett Davis	Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks.	3DIC	2015	DBLP DOI BibTeX RDF
1	Daniel H. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi	Modeling and analysis of defects in through silicon via channel for non-invasive fault isolation.	3DIC	2015	DBLP DOI BibTeX RDF
1	Andy Heinig, Muhammad Waqas Chaudhary, Peter Schneider, Peter Ramm, Josef Weber	Current and future 3D activities at Fraunhofer.	3DIC	2015	DBLP DOI BibTeX RDF
1	Tsung-Yen Tsai, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen	An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration.	3DIC	2015	DBLP DOI BibTeX RDF
1	Jiatong Liu, Ken Suzuki, Hideo Miura	Variation of thermal stress in TSV structures caused by crystallinity of electroplated copper interconnections.	3DIC	2015	DBLP DOI BibTeX RDF
1	Ryouya Shirahama, Sethavut Duangchan, Yusuke Koishikawa, Akiyoshi Baba	Influential factors in low-temperature direct bonding of silicon dioxide.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Akihiro Fujiwara, Masaki Hashizume	On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs.	3DIC	2015	DBLP DOI BibTeX RDF
1	Kazuo Kondo, Shingo Mukahara, Masayuki Yokoi, Jin Onuki	No pumping at 450°C with electrodeposited copper TSV.	3DIC	2015	DBLP DOI BibTeX RDF
1	Daniel S. Green, Carl L. Dohrman, Jeffrey Demmin, Tsu-Hsi Chang	Path to 3D heterogeneous integration.	3DIC	2015	DBLP DOI BibTeX RDF
1	Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang Wook Lee 0002, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi	Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding.	3DIC	2015	DBLP DOI BibTeX RDF
1	Jin Kawakita, Barbara Horváth, Toyohiro Chikyow	Fast filling of through-silicon via (TSV) with conductive polymer/metal composites.	3DIC	2015	DBLP DOI BibTeX RDF
1	Sumin Choi, Heegon Kim, Daniel H. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yong-Ju Kim, Yunsaing Kim	Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC.	3DIC	2015	DBLP DOI BibTeX RDF
1	Samson Melamed, Katsuya Kikuchi, Masahiro Aoyagi	Investigation of effects of metalization on heat spreading in bump-bonded 3D systems.	3DIC	2015	DBLP DOI BibTeX RDF
1	Eric J. Wyers, T. Robert Harris, Wallace Shep Pitts, Jordan E. Massad, Paul D. Franzon	Characterization of the mechanical stress impact on device electrical performance in the CMOS and III-V HEMT/HBT heterogeneous integration environment.	3DIC	2015	DBLP DOI BibTeX RDF
1	Kosuke Yamashita, Shunji Kurooka, Koji Shirakawa, Yoshinori Hotta, Hirofumi Abe	Copper-filled anodized aluminum oxide a potential material for chip to chip bonding.	3DIC	2015	DBLP DOI BibTeX RDF
1	Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi	Design of a 3-D stacked floating-point Goldschmidt divider.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hanju Oh, Gary S. May, Muhannad S. Bakir	Silicon interposer platform with low-loss through-silicon vias using air.	3DIC	2015	DBLP DOI BibTeX RDF
1	Kuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii	Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration.	3DIC	2015	DBLP DOI BibTeX RDF
1	Sayuri Kohara, Keishi Okamoto, Hirokazu Noma, Kazushige Toriyama, Hiroyuki Mori	Warpage analysis of organic substrates for 2.1D packaging.	3DIC	2015	DBLP DOI BibTeX RDF
1	Mariappan Murugesan, Jichoel Bea, Hiroyuki Hashimoto, K. W. Lee, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka	Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study.	3DIC	2015	DBLP DOI BibTeX RDF
1	Soon-Wook Kim, Lan Peng, Andy Miller, Gerald Beyer, Eric Beyne, Chung-Sun Lee	Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics.	3DIC	2015	DBLP DOI BibTeX RDF
1	Kohei Ohta, Atsushi Hirate, Yuto Miyachi, Tomohiro Shimizu, Shoso Shingubara	All-wet TSV filling with highly adhesive displacement plated Cu seed layer.	3DIC	2015	DBLP DOI BibTeX RDF
1	Paul D. Franzon, Eric Rotenberg, James Tuck 0001, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa	Computing in 3D.	3DIC	2015	DBLP DOI BibTeX RDF
1	Vempati Srinivasa Rao	IME's capabilities and programs in 2.5D/3DIC.	3DIC	2015	DBLP DOI BibTeX RDF
1	Mohamed N. ElBahey, DiaaEldin S. Khalil, Hani Fikry Ragai	Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA).	3DIC	2015	DBLP DOI BibTeX RDF
1	Keiichiro Iwanabe, Tanemasa Asano	Room-temperature bonding mechanism of compliant bump with ultrasonic assist.	3DIC	2015	DBLP DOI BibTeX RDF
1	Yangyang Yan, Yingtao Ding, Qianwen Chen, Kang Wook Lee 0002, Takafumi Fukushima, Mitsumasa Koyanagi	Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications.	3DIC	2015	DBLP DOI BibTeX RDF
1	Amadine Jouve, Y. Sinquin, Arnaud Garnier, M. Daval, Pascal Chausse, M. Argoud, N. Allouti, Laurence Baud, Jérôme Dechamp, R. Franiatte, Séverine Cheramy, H. Kato, K. Kondo	Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement.	3DIC	2015	DBLP DOI BibTeX RDF
1		2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015	3DIC	2015	DBLP BibTeX RDF
1	Chuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Chang, En-Hsiang Yeh, Feng-Wei Kuo, Hsu-Hsien Chen, Chih-Hua Chen, Huan-Neng Ron Chen, Ying-Ta Lu, Chewnpu Jou, Hao-Yi Tsai, C. S. Liu, Doug C. H. Yu	Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology.	3DIC	2015	DBLP DOI BibTeX RDF
1	Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu	Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit.	3DIC	2015	DBLP DOI BibTeX RDF
1	K. W. Lee, Ji Chel Bea, Mitsu Koyanagi, Takafumi Fukushima, Tetsu Tanaka	Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University.	3DIC	2015	DBLP DOI BibTeX RDF
1	Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou	Temperature-aware online testing of power-delivery TSVs.	3DIC	2015	DBLP DOI BibTeX RDF

Publications at "3DIC"( http://dblp.L3S.de/Venues/3DIC )