Search results for "CPU"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Seung Woo Son 0001, Konrad Malkowski, Guilin Chen, Mahmut T. Kandemir, Padma Raghavan	Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Parallel sparse matrix, Computation, Dynamic voltage scaling, Communication networks, Energy consumption
24	Mohammad Atique, Sadique S. Ali	A Novel Adaptive Neuro Fuzzy Inference System Based CPU Scheduler for Multimedia Operating System.	IJCNN	2007	DBLP DOI BibTeX RDF
24	Ahmed Ayad, Jeffrey F. Naughton, Stephen J. Wright 0001, Utkarsh Srivastava	Approximating StreamingWindow Joins Under CPU Limitations.	ICDE	2006	DBLP DOI BibTeX RDF
24	Giovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo	Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information.	DSD	2006	DBLP DOI BibTeX RDF
24	Giovanni Pacifici, Wolfgang Segmuller, Mike Spreitzer, Asser N. Tantawi	Dynamic estimation of CPU demand of web traffic.	VALUETOOLS	2006	DBLP DOI BibTeX RDF
24	Seung Woo Son 0001, Konrad Malkowski, Guilin Chen, Mahmut T. Kandemir, Padma Raghavan	Integrated link/CPU voltage scaling for reducing energy consumption of parallel sparse matrix applications.	IPDPS	2006	DBLP DOI BibTeX RDF
24	Yuanyuan Zhang, Wei Sun 0004, Yasushi Inoguchi	Predicting Running Time of Grid Tasks based on CPU Load Predictions.	GRID	2006	DBLP DOI BibTeX RDF
24	Mais Nijim, Tao Xie 0004, Xiao Qin 0001	Performance analysis of an admission controller for CPU- and I/O-intensive applications in self-managing computer systems.	ACM SIGOPS Oper. Syst. Rev.	2005	DBLP DOI BibTeX RDF
24	Andy Georges, Lieven Eeckhout, Koen De Bosschere	Comparing Low-Level Behavior of SPEC CPU and Java Workloads.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
24	Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin	Communication breakdown: analyzing CPU usage in commercial Web workloads.	ISPASS	2004	DBLP DOI BibTeX RDF
24	Haisang Wu, Binoy Ravindran, E. Douglas Jensen, Peng Li 0020	CPU scheduling for statistically-assured real-time performance and improved energy efficiency.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	real-time systems, energy-efficient scheduling, time/utility functions, utility accrual scheduling
24	Wanghong Yuan, Klara Nahrstedt	Energy-efficient soft real-time CPU scheduling for mobile multimedia systems.	SOSP	2003	DBLP DOI BibTeX RDF	mobile computing, multimedia, power management
24	Piyush Shivam, Pete Wyckoff, Dhabaleswar K. Panda 0001	Can User-Level Protocols Take Advantage of Multi-CPU NICs?.	IPDPS	2002	DBLP DOI BibTeX RDF	OS bypass, user-level network protocol, parallel protocol design, message passing, gigabit ethernet
24	Richard Tran Mills, Andreas Stathopoulos, Evgenia Smirni	Algorithmic modifications to the Jacobi-Davidson parallel eigensolver to dynamically balance external CPU and memory load.	ICS	2001	DBLP DOI BibTeX RDF
24	John L. Henning	SPEC CPU2000: Measuring CPU Performance in the New Millennium.	Computer	2000	DBLP DOI BibTeX RDF
24	Peter Schneider	CPU-utilization and secondary-storage performance: the demand for a new secondary-storage technology.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
24	Changkyu Kim, Jatin Chhugani, Nadathur Satish, Eric Sedlar, Anthony D. Nguyen, Tim Kaldewey, Victor W. Lee, Scott A. Brandt, Pradeep Dubey	FAST: fast architecture sensitive tree search on modern CPUs and GPUs.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	compression, thread-level parallelism, cpu, gpu, tree search, data-level parallelism
24	J. Stanley Warford, Ryan Okelberry	Pep8CPU: a programmable simulator for a central processing unit.	SIGCSE	2007	DBLP DOI BibTeX RDF	Pep/8, data section, micropro-gramming, simulation, virtual machine, CPU, MIPS, assembly language
24	Songnian Zhou	A Trace-Driven Simulation Study of Dynamic Load Balancing.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	homogeneous distributed systems, job transfer, job response times, scheduling, scheduling, broadcasting, distributed databases, dynamic load balancing, trace-driven simulation, CPU, input/output, input-output programs, message exchange
23	Minsu Shin, Song Chong, Injong Rhee	Dual-resource TCP/AQM for processing-constrained networks.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	CPU capacity, TCP-AQM, proportional, transmission link capacity, fairness, efficiency
23	John H. Kelm, Steven S. Lumetta	HybridOS: runtime support for reconfigurable accelerators.	FPGA	2008	DBLP DOI BibTeX RDF	CPU/accelerator architecture, operating system, reconfigurable computing
23	Karthikeyan Vaidyanathan, Dhabaleswar K. Panda 0001	Benefits of I/O Acceleration Technology (I/OAT) in Clusters.	ISPASS	2007	DBLP DOI BibTeX RDF	concurrent thread, I/O acceleration technology, TCP/IP stack, multigigabit data rate, packet processing overhead, multitier data center, CPU utilization, central processing unit, network bandwidth performance, transmission control protocol, transport protocol, Internet protocol, parallel virtual file system
23	Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum	Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	SPEC CPU benchmarks, performance evaluation, caches, branch prediction
23	Daniel G. Chavarría-Miranda, Andrès Márquez	Assessing the potential of hybrid hpc systems for scientific applications: a case study.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	hybrid CPU/FPGA systems, data-intensive applications
23	Ashish Mehra, Atri Indiresan, Kang G. Shin	Structuring Communication Software for Quality-of-Service Guarantees.	IEEE Trans. Software Eng.	1997	DBLP DOI BibTeX RDF	traffic enforcement, QoS-sensitive resource management, CPU and link scheduling, Real-time communication
23	Greet Bilsen, Rudy Lauwereins, J. A. Peperstraete	Compile-time scheduling with resource-constraints.	HICSS (2)	1995	DBLP DOI BibTeX RDF	multiple execution, CPU-usage, run-time performance, nonCPU resource requirements, performance evaluation, resource allocation, signal processing, digital signal processing, program compilers, processor scheduling, resource-constraints, static schedule, compile-time scheduling, scheduling method, DSP-applications
23	Asit Dan, Philip S. Yu	Performance Analysis of Buffer Coherency Policies in a Multisystem Data Sharing Environment.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	integrated analytic models, buffer coherency policies, multisystem data sharing environment, multisystem transaction processing environment, propagation oriented approaches, coherency messages, buffer hit probability, independent reference model, CPU overhead, performance evaluation, performance analysis, transaction processing, detection, shared memory systems, response time, simulation models, notification, maximum throughput
23	Joseph L. Hellerstein	Achieving Service Rate Objectives with Decay Usage Scheduling.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	usage-based approach, CPU allocation, decay usage schedulers, compute-bound workloads, scientific environments, Unix system, fine granularity, process priorities, low overhead algorithms, service rate objectives, scheduling, resource allocation, Unix, analytic model, feedback loop
23	Wei-lun Kao, Ravishankar K. Iyer, Dong Tang	FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior under Faults.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	FINE, fault injection and monitoring environment, UNIX system behavior, hardware-induced software errors, fault injector, analysis utilities, SunOS 4.1.2, transient Markov reward analysis, bus faults, CPU faults, pointer faults, software tools, Unix, program testing, system monitoring, software faults, software monitor, workload generator
23	Murthy V. Devarakonda, Ravishankar K. Iyer	Predictability of Process Resource Usage: A Measurement-Based Study on UNIX.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	measurement-based study, file I/O, statistical clustering, high-density regions, process resource usage, VAX 11/780, BSD Unix, scheduling, performance evaluation, statistical analysis, Unix, correlation, program testing, memory requirements, statistical approach, CPU time, prediction scheme, state-transition model
23	Sung-Min Lee 0004, Sang-Bum Suh, Bokdeuk Jeong, Sangdok Mo, Brian Myungjune Jung, Jung-Hyun Yoo, Jae-Min Ryu, Dong-Hyuk Lee	Fine-grained I/O access control of the mobile devices based on the Xen architecture.	MobiCom	2009	DBLP DOI BibTeX RDF	I/O access control, smart phone security, virtual machine, virtual machine monitor
23	Wenbin Fang, Mian Lu, Xiangye Xiao, Bingsheng He, Qiong Luo 0001	Frequent itemset mining on graphics processors.	DaMoN	2009	DBLP DOI BibTeX RDF
23	Xia Zhao, Yao Guo 0001, Xiangqun Chen	Transaction-based adaptive dynamic voltage scaling for interactive applications.	ISLPED	2009	DBLP DOI BibTeX RDF	scheduling, interaction, dynamic voltage and frequency scaling
23	Ying-Wen Bai, Chun-Yang Tsai	Design and implementation of a low-power workstation.	CCECE	2009	DBLP DOI BibTeX RDF
23	David Andrews 0001, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp	Achieving Programming Model Abstractions for Reconfigurable Computing.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
23	Jianli Zhuo, Chaitali Chakrabarti	Energy-efficient dynamic task scheduling algorithms for DVS systems.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	DVS system, Dynamic task scheduling, optimal scaling factor, real time, energy minimization
23	Lanier A. Watkins, Raheem A. Beyah, Cherita L. Corbett	Passive Identification of Under-Utilized CPUs in High Performance Cluster Grid Networks.	ICC	2008	DBLP DOI BibTeX RDF
23	Hui-Chin Yang, Li-Ming Wang, Chung-Ping Chung	iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability.	ICYCS	2008	DBLP DOI BibTeX RDF
23	Yang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin	A helper thread based EDP reduction scheme for adapting application execution in CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
23	Shiben Bhattacharjee, Suryakant Patidar, P. J. Narayanan	Real-Time Rendering and Manipulation of Large Terrains.	ICVGIP	2008	DBLP DOI BibTeX RDF
23	Honghoon Jang, Anjin Park, Keechul Jung	Neural Network Implementation Using CUDA and OpenMP.	DICTA	2008	DBLP DOI BibTeX RDF
23	Nikolaos D. Doulamis, Emmanouel A. Varvarigos, Theodora A. Varvarigou	Fair Scheduling Algorithms in Grids.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Fair Grid Scheduling, Grid Computing
23	Bren Mochocki, Dinesh Rajan, Xiaobo Sharon Hu, Christian Poellabauer, Kathleen Otten, Thidapat Chantem	Network-Aware Dynamic Voltage and Frequency Scaling.	IEEE Real-Time and Embedded Technology and Applications Symposium	2007	DBLP DOI BibTeX RDF
23	Kihwan Choi, Ramakrishna Soma, Massoud Pedram	Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
23	Geuntae Bae, Daewon Kim, Daeyeon Park	Low-Power Multimedia Scheduling Using Output Pre-buffering.	MASCOTS	2005	DBLP DOI BibTeX RDF
23	Jayanth Gummaraju, Mendel Rosenblum	Stream Programming on General-Purpose Processors.	MICRO	2005	DBLP DOI BibTeX RDF	stream architectures/programming, hyper-threading, prefetching
23	Kihwan Choi, Ramakrishna Soma, Massoud Pedram	Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times.	DATE	2004	DBLP DOI BibTeX RDF
23	Aqeel Mahesri, Vibhore Vardhan	Power Consumption Breakdown on a Modern Laptop.	PACS	2004	DBLP DOI BibTeX RDF
23	Soo-Cheol Oh, Hankook Jang, Sang-Hwa Chung	Analysis of TCP/IP Protocol Stack for a Hybrid TCP/IP Offload Engine.	PDCAT	2004	DBLP DOI BibTeX RDF
23	Murray Pearson, Dean Armstrong, Tony McGregor	Design of a Processor to Support the Teaching of Computer Systems.	DELTA	2002	DBLP DOI BibTeX RDF
23	Jacob R. Lorch, Alan Jay Smith	Scheduling techniques for reducing processor energy use in MacOS.	Wirel. Networks	1997	DBLP DOI BibTeX RDF
23	Lionel C. Mitchell	Performance Analysis of a Fault Tolerant Computer System.	SIGMETRICS	1990	DBLP DOI BibTeX RDF
22	Bengisu Elis, Olga Pearce, David Böhme, Jason Burmark, Martin Schulz 0001	Non-Blocking GPU-CPU Notifications to Enable More GPU-CPU Parallelism.	HPC Asia	2024	DBLP DOI BibTeX RDF
22	Andrés F. Ocampo, Mah-Rukh Fida, Juan Felipe Botero, Ahmed Elmokashfi, Haakon Bryhni	PRINCIPIA: Opportunistic CPU and CPU-shares Allocation for Containerized Virtualization in Mobile Edge Computing.	NOMS	2023	DBLP DOI BibTeX RDF
22	Soohyeong Kim, Seyoung Ahn, Joohan Park, Jiseung Youn, Yongseok Kwon, Sunghyun Cho	Revisiting the Coverage Boundary of Multi-CPU Cell-Free Massive MIMO: CPU Cooperation Aspect.	ICC	2023	DBLP DOI BibTeX RDF
22	Yuhao Ju, Yijie Wei, Xi Chen, Jie Gu	A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
22	Sunjun Hwang, Jin Choi, Seohwan Yoo, Hayeon Park, Chang-Gun Lee	Hardware Interrupt and CPU Contention aware CPU/GPU Co-Scheduling on Multi-Cluster System.	ICICT	2022	DBLP DOI BibTeX RDF
22	Nicolas Tollenaere	Decoupling the optimization space of tensor computation for a better understanding of performance on Intel CPU. (Découpler l'espace d'optimisation des calculs de tenseurs pour une meilleure compréhension de la performance sur CPU).		2022	RDF
22	Guanlin He	Parallel algorithms for clustering large datasets on CPU-GPU heterogeneous architectures. (Algorithmes parallèles de clustering de grands ensembles de données pour architectures hétérogènes CPU-GPU).		2022	RDF
22	Mikhail Asiatici, Damian Maiorano, Paolo Ienne	How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System.	J. Signal Process. Syst.	2021	DBLP DOI BibTeX RDF
22	Youssef Elmougy, Weiwei Jia 0001, Xiaoning Ding, Jianchen Shan	Diagnosing the Interference on CPU-GPU Synchronization Caused by CPU Sharing in Multi-Tenant GPU Clouds.	IPCCC	2021	DBLP DOI BibTeX RDF
22	Tiago Knorst, Michael Guilherme Jordan, Arthur Francisco Lorenzon, Mateus Beck Rutzig, Antonio Carlos Schneider Beck	ETCF - Energy-Aware CPU Thread Throttling and Workload Balancing Framework for CPU-FPGA Collaborative Environments.	SBESC	2021	DBLP DOI BibTeX RDF
22	Hao Wen 0002, Wei Zhang 0002	Reducing CPU-GPU Interferences to Improve CPU Performance in Heterogeneous Architectures.	J. Comput. Sci. Eng.	2020	DBLP DOI BibTeX RDF
22	Muhamad Dwisnanto Putro, Kang-Hyun Jo	Fast Face-CPU: A Real-time Fast Face Detector on CPU Using Deep Learning.	ISIE	2020	DBLP DOI BibTeX RDF
22	Lhoussein Mabrouk	Contribution à l'implémentation des algorithmes de vision avec parallélisme massif de données sur les architectures hétérogènes CPU/GPU. (Contribution to the implementation of vision algorithms with massive parallelism of data on heterogeneous CPU/GPU architectures).		2020	RDF
22	Jason Lowe-Power, Christopher Nitta	The Davis In-Order (DINO) CPU: A Teaching-focused RISC-V CPU Design.	WCAE@ISCA	2019	DBLP DOI BibTeX RDF
22	Maxime Martelli	Approche haut niveau pour l'accélération d'algorithmes sur des architectures hétérogènes CPU/GPU/FPGA. Application à la qualification des radars et des systèmes d'écoute électromagnétique. (High-Level Approach for the Acceleration of Algorithms on CPU/GPU/FPGA Heterogeneous Architectures. Application to Radar Qualification and Electromagnetic Listening Systems).		2019	RDF
22	Juan Chen 0001, Li Shen 0007	Design of paper CPU project to improve student understanding of CPU working principle.	TURC	2018	DBLP DOI BibTeX RDF
22	Bain Syrowik, Blair Fort, Stephen Dean Brown	Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems.	HEART	2018	DBLP DOI BibTeX RDF
22	M. S. Komar	Data Rate Assessment on L2-L3 CPU Bus and Bus between CPU and RAM in Modern CPUs.	Autom. Control. Comput. Sci.	2017	DBLP DOI BibTeX RDF
22	Ali Narimani, Seyed Saeed Changiz Rezaei, Arman Zaribafiyan	Combinatorial Optimization by Decomposition on Hybrid CPU-non-CPU Solver Architectures.	CoRR	2017	DBLP BibTeX RDF
22	Siddharth Rai, Mainak Chaudhuri	Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors.	IPDPS Workshops	2017	DBLP DOI BibTeX RDF
22	Xin Wang 0056, Wei Zhang 0002	A Sample-Based Dynamic CPU and GPU LLC Bypassing Method for Heterogeneous CPU-GPU Architectures.	TrustCom/BigDataSE/ICESS	2017	DBLP DOI BibTeX RDF
22	Fadel Abdallah	Optimization and Scheduling on Heterogeneous CPU/FPGA Architecture with Communication Delays. (Optimisation et ordonnancement sur une architecture hétérogène CPU/FPGA avec délais de communication).		2017	RDF
22	Hugo Lewi Hammer, Anis Yazidi, Alfred Bratterud, Hårek Haugerud, Boning Feng	Recovering Request Patterns to a CPU Processor from Observed CPU Consumption Data.	INISCOM	2016	DBLP DOI BibTeX RDF
22	Matthew Halpern, Yuhao Zhu 0001, Vijay Janapa Reddi	Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction.	HPCA	2016	DBLP DOI BibTeX RDF
22	Supriya Raheja, Reena Dadhich, Smita Rajpal	Designing of Vague Logic Based Fair-Share CPU Scheduler: VFS CPU Scheduler.	Int. J. Fuzzy Syst. Appl.	2015	DBLP DOI BibTeX RDF
22	Wei Zhou, Zongyou Dai, Guangling Yuan, Ping Chen	CPU-GPU协同计算的并行奇异值分解方法 (Parallelized Singular Value Decomposition Method with Collaborative Computing of CPU-GPU).	计算机科学	2015	DBLP BibTeX RDF
22	Chandra Mohan Velpula, Jayant, Vishal Shahi	CPU temperature aware scheduler a study on incorporating temperature data for CPU scheduling decisions.	ICACCI	2015	DBLP DOI BibTeX RDF
22	Andrej Podzimek, Lubomír Bulej, Lydia Y. Chen, Walter Binder, Petr Tuma 0001	Analyzing the Impact of CPU Pinning and Partial CPU Loads on Performance and Energy Efficiency.	CCGRID	2015	DBLP DOI BibTeX RDF
22	Issam Said	Contributions of hybrid architectures to depth imaging: a CPU, APU and GPU comparative study. (Apports des architectures hybrides à l'imagerie profondeur : étude comparative entre CPU, APU et GPU).		2015	RDF
22	Jean-François Dollinger	A framework for efficient execution on GPU and CPU+GPU systems. (Un framework pour l'exécution efficace d'applications sur GPU et CPU+GPU).		2015	RDF
22	Mohamed Amine Bergach	Adaptation du calcul de la Transformée de Fourier Rapide sur une architecture mixte CPU/GPU intégrée. (Adaptation of the Fast Fourier Transform processing on hybride integrated CPU/GPU architecture).		2015	RDF
22	Omar Souissi	Path planning on a high performance heterogeneous CPU/FPGA architecture. (Planification de chemin d'hélicoptères sur une architecture hétérogène CPU FPGA haute performance).		2015	RDF
22	Kishore Kothapalli, Dip Sankar Banerjee, P. J. Narayanan, Surinder Sood, Aman Kumar Bahl, Shashank Sharma, Shrenik Lad, Krishna Kumar Singh, Kiran Kumar Matam, Sivaramakrishna Bharadwaj, Rohit Nigam, Parikshit Sakurikar, Aditya Deshpande, Ishan Misra, Siddharth Choudhary, Shubham Gupta	CPU and/or GPU: Revisiting the GPU Vs. CPU Myth	CoRR	2013	DBLP BibTeX RDF
22	Manish Arora, Siddhartha Nath, Subhra Mazumdar 0003, Scott B. Baden, Dean M. Tullsen	Redefining the Role of the CPU in the Era of CPU-GPU Integration.	IEEE Micro	2012	DBLP DOI BibTeX RDF
22	Yi Yang 0018, Ping Xiang, Mike Mantor, Huiyang Zhou	CPU-assisted GPGPU on fused CPU-GPU architectures.	HPCA	2012	DBLP DOI BibTeX RDF
22	Gorik De Samblanx, Floris De Smedt, Lars Struyf, Sander Beckers, Joost Vennekens, Toon Goedemé	CPCPU: Coreful Programming on the CPU - Why a CPU can Benefit from Massive Multithreading.	PECCS	2012	DBLP BibTeX RDF
22	Peter Trapp, Christian Facchi	How to Handle CPU Bound Systems: A Spezialization of Dynamic Performance Stubs to CPU Stubs.	Int. CMG Conference	2008	DBLP BibTeX RDF
20	Jose Ricardo da Silva Jr., Esteban Walter Gonzalez Clua, Paulo A. Pagliosa, Anselmo Antunes Montenegro	Fluid simulation with rigid body triangle accuracy collision using an heterogeneous GPU/CPU hardware system.	SI3D	2010	DBLP DOI BibTeX RDF	particle collision, fluid simulation, SPH
20	Evangelia Kalyvianaki, Themistoklis Charalambous, Steven Hand 0001	Self-adaptive and self-configured CPU resource provisioning for virtualized servers using Kalman filters.	ICAC	2009	DBLP DOI BibTeX RDF	virtualized servers, kalman filters
20	Nicolas Robidoux, Minglun Gong, John Cupitt, Adam Turcotte, Kirk Martinez	CPU, SMP and GPU implementations of Nohalo level 1, a fast co-convex antialiasing image resampler.	C3S2E	2009	DBLP DOI BibTeX RDF	GEGL, HLSL, abyss policy, arithmetic branching, co-convex interpolation, fast image resampling, minmod limiter, natural and not-a-knot boundary conditions, nonlinear image filtering, quantitative comparison of image enlargement methods, video upsampling, benchmark, GPU, SMP, antialiasing, zooming, edge enhancement, VIPS
20	Jiuxing Liu, Bülent Abali	Virtualization polling engine (VPE): using dedicated CPU cores to accelerate I/O virtualization.	ICS	2009	DBLP DOI BibTeX RDF	networking, virtual machine, ethernet
20	Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan	CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA accelerators, c-to-gates, FPGA, high-performance computing, reconfigurable computing
20	Fadi N. Sibai	Gauging the OpenSourceMark Benchmark in Measuring CPU Performance.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	computer benchmarking, OpenSourceMark, performance analysis
20	Qian Diao, Justin J. Song	Prediction of CPU idle-busy activity pattern.	HPCA	2008	DBLP DOI BibTeX RDF
20	Chris Schläger	Keynote: The Impact of Operating Systems on Modern CPU Designs (and Vice Versa).	ARCS	2008	DBLP DOI BibTeX RDF
20	Marcin Zukowski, Niels Nes, Peter A. Boncz	DSM vs. NSM: CPU performance tradeoffs in block-oriented query processing.	DaMoN	2008	DBLP DOI BibTeX RDF
20	Christophe Cérin, Hazem Fkaier, Mohamed Jemni	Experimental Study of Thread Scheduling Libraries on Degraded CPU.	ICPADS	2008	DBLP DOI BibTeX RDF
20	Ludmila Cherkasova, Diwaker Gupta, Amin Vahdat	Comparison of the three CPU schedulers in Xen.	SIGMETRICS Perform. Evaluation Rev.	2007	DBLP DOI BibTeX RDF