Search results for "Fan-in"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Yuanyuan Yang 0001	A New Conference Network for Group Communication.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	conference networks, point-to-point connections, many-to-many connections, routing, multicast, group communication, telecommunication, real-time applications, collaborative applications, multistage networks, all-to-all communication, self-routing, telephony, Conferencing
18	Nathan Segerlind, Samuel R. Buss, Russell Impagliazzo	A Switching Lemma for Small Restrictions and Lower Bounds for k - DNF Resolution.	FOCS	2002	DBLP DOI BibTeX RDF
18	Yuanyuan Yang 0001, Jianchao Wang	A Class of Multistage Conference Switching Networks for Group Communication.	ICPP	2002	DBLP DOI BibTeX RDF
18	Frederic Green	The Correlation Between Parity and Quadratic Polynomials Mod 3.	CCC	2002	DBLP DOI BibTeX RDF
18	Yuanyuan Yang 0001	A New Conference Network for Group Communication.	ICPP	2001	DBLP DOI BibTeX RDF
18	Ketan Mulmuley, Pradyut Shah	A Lower Bound for the Shortest Path Problem.	CCC	2000	DBLP DOI BibTeX RDF	parallel, lower bound, shortest path problem
18	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò	Gate-level power and current simulation of CMOS integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
18	Philip D. MacKenzie, Vijaya Ramachandran	ERCW PRAMs and Optical Communication.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
18	V. Vinay	Hierarchies of Circuit Classes that are Closed under Complement.	CCC	1996	DBLP DOI BibTeX RDF	Circuits, Complexity Theory, Complementation
18	Cristina Versino, Luca Maria Gambardella	Learning the Visuomotor Coordination of a Mobile Robot by Using the Invertible Kohonen Map.	IWANN	1995	DBLP DOI BibTeX RDF
18	Valeriu Beiu, John G. Taylor	Optimal Mapping of Neural Networks onto FPGA's - A New Constructive Algorithm -.	IWANN	1995	DBLP DOI BibTeX RDF
18	Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha	Design of robustly testable combinational logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	Brian D. Lee, Vojin G. Oklobdzija	Improved CLA scheme with optimized delay.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
18	Miklos Santha, Christopher B. Wilson	Polynomial Size Constant Depth Circuits with a Limited Number of Negations.	STACS	1991	DBLP DOI BibTeX RDF
18	Inga Niepel, Peter Rossmanith	Uniform Circuits and Exclusive Read PRAMs.	FSTTCS	1991	DBLP DOI BibTeX RDF
18	Ingo Wegener, Norbert Wurm, Sang-Zin Yi	Symmetric Functions in AC0A Can Be Computed in Constant Depth With Very Small Size.	MFCS	1990	DBLP DOI BibTeX RDF
18	Hans-Jörg Mathony, Utz G. Baitinger	CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
18	Vivek Sarkar	Synchronization using counting semaphores.	ICS	1988	DBLP DOI BibTeX RDF
18	Tsutomu Sasao	MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators.	DAC	1986	DBLP DOI BibTeX RDF
18	Stephen S. Yau, Calvin K. Tang	Universal logic circuits and their modular realizations.	AFIPS Spring Joint Computing Conference	1968	DBLP DOI BibTeX RDF
18	Kenneth E. Batcher	Sorting Networks and Their Applications.	AFIPS Spring Joint Computing Conference	1968	DBLP DOI BibTeX RDF
18	Richard Beigel, Jun Tarui	On ACC	FOCS	1991	DBLP DOI BibTeX RDF	modulus-amplifying polynomials, ACC, depth-2 probabilistic circuits, symmetric gate, depth-2 deterministic circuits, language, root, fan-in, AND gates, leaves
18	A. Yavuz Oruç, Ajai Thirumalai	A Systematic Design of Cellular Permutation Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	cellular permutation arrays, coset decompositions, permutation cell, coset generator, target network, multiprocessor interconnection networks, network topology, cellular arrays, cost function, propagation delay, fan-out, fan-in
18	Martin Charles Golumbic	Combinatorial Merging.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	integer weighted nodes, number of internal nodes, r-ary tree, switching circuit theory, weight of the root of the tree, parallel processing, Fan-in
17	Binay Sugla, David A. Carlson	Extreme Area-Time Tradeoffs in VLSI.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	bounded fan-in, fan-out prefix computation graphs, area requirements, constant factor reduction, area-time tradeoff, VLSI, lower bounds, digital arithmetic, layout, circuit layout CAD, carry look-ahead adder
17	Johan Håstad, Mikael Goldmann	On the Power of Small-Depth Threshold Circuits	FOCS	1990	DBLP DOI BibTeX RDF	monotone weighted threshold circuit, small-depth threshold circuits, bottom fan-in, AND, OR circuits, functions, monotone functions
17	Eric Allender	A Note on the Power of Threshold Circuits	FOCS	1989	DBLP DOI BibTeX RDF	unbounded-fan-in circuits, depth-three threshold circuits, polynomial hierarchy, threshold circuits, AND gates, OR gates
14	Yuqiang Cui, Weiwei Shan, Peng Cao 0002	Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS.	Integr.	2024	DBLP DOI BibTeX RDF
14	Ankur Kumar, Rajendra Kumar Nagaria	Reduction of variation and leakage in wide fan-in OR Logic domino gate.	Integr.	2023	DBLP DOI BibTeX RDF
14	Sina Faraji, Florian Kerschbaum	Trifecta: Faster High-Throughput Three-Party Computation over WAN Using Multi-Fan-In Logic Gates.	Proc. Priv. Enhancing Technol.	2023	DBLP DOI BibTeX RDF
14	Sherif M. Sharroush, Emad Badry	Proposed time-mode wide fan-in NAND and NOR gates.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
14	Libor Caha, Xavier Coiteux-Roy, Robert Koenig	A colossal advantage: 3D-local noisy shallow quantum circuits defeat unbounded fan-in classical circuits.	CoRR	2023	DBLP DOI BibTeX RDF
14	Xingyu Jia, Xi Zhang, Kui Guo, Xuehui Li	Effect of the Radial Velocity Distribution on the Loss Generation of a Contra-Rotating Fan in a Ventilation System.	Entropy	2023	DBLP DOI BibTeX RDF
14	Vijay Kumar Sharma	CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
14	Ankur Kumar, Rajendra Kumar Nagaria	A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
14	Ji Xu, Ying Sun, Jun Liu 0027, Yi-Ding Wei, Wen-Sheng Zhao, Da-Wei Wang 0003	Fabrication and high-frequency characterization of low-cost fan-in/out WLP technology with RDL for 2.5D/3D heterogeneous integration.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Gaurav Sinha	Efficient Reconstruction of Depth Three Arithmetic Circuits with Top Fan-In Two.	ITCS	2022	DBLP DOI BibTeX RDF
14	Tomoyuki Yamakami	Nondeterministic Auxiliary Depth-Bounded Storage Automata and Semi-Unbounded Fan-In Cascading Circuits - (Extended Abstract).	COCOON	2022	DBLP DOI BibTeX RDF
14	Bryce A. Primavera, Jeffrey M. Shainline	An active dendritic tree can mitigate fan-in limitations in superconducting neurons.	CoRR	2021	DBLP BibTeX RDF
14	Gaurav Sinha	Efficient reconstruction of depth three circuits with top fan-in two.	CoRR	2021	DBLP BibTeX RDF
14	Hind Dadoun, Hervé Delingette, Anne-Laure Rousseau, Eric de Kerviler, Nicholas Ayache	Combining Bayesian And Deep Learning Methods For The Delineation Of The Fan In Ultrasound Images.	ISBI	2021	DBLP DOI BibTeX RDF
14	Yuqiang Cui, Chengjun Wu, Ziyu Li, Weiwei Shan	Energy-Efficient Design of Large Fan-in Dynamic One-hot Multiplexer in 28nm CMOS Technology.	ICTA	2021	DBLP DOI BibTeX RDF
14	Gaurav Sinha	Efficient reconstruction of depth three circuits with top fan-in two.	Electron. Colloquium Comput. Complex.	2020	DBLP BibTeX RDF
14	Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan	Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations.	AICAS	2020	DBLP DOI BibTeX RDF
14	Sandeep Garg, Tarun Kumar Gupta	Low leakage domino logic circuit for wide fan-in gates using CNTFET.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
14	Adam Bene Watts, Robin Kothari, Luke Schaeffer, Avishay Tal	Exponential separation between shallow quantum circuits and unbounded fan-in shallow classical circuits.	Electron. Colloquium Comput. Complex.	2019	DBLP BibTeX RDF
14	Erica Tena-Sánchez, Antonio J. Acosta 0001	Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
14	Alexander S. Kulikov, Vladimir V. Podolskii	Computing Majority by Constant Depth Majority Circuits with Low Fan-in Gates.	Theory Comput. Syst.	2019	DBLP DOI BibTeX RDF
14	Adam Bene Watts, Robin Kothari, Luke Schaeffer, Avishay Tal	Exponential separation between shallow quantum circuits and unbounded fan-in shallow classical circuits.	CoRR	2019	DBLP BibTeX RDF
14	Adam Bene Watts, Robin Kothari, Luke Schaeffer, Avishay Tal	Exponential separation between shallow quantum circuits and unbounded fan-in shallow classical circuits.	STOC	2019	DBLP DOI BibTeX RDF
14	Mohammad Asyaei	A new low-power dynamic circuit for wide fan-in gates.	Integr.	2018	DBLP DOI BibTeX RDF
14	Ankur Kumar, Rajendra Kumar Nagaria	A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits.	Integr.	2018	DBLP DOI BibTeX RDF
14	Vikas Mahor, Manisha Pattanaik	A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
14	Mohammad Asyaei, Farshad Moradi	A Domino Circuit Technique for Noise-Immune High Fan-In Gates.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
14	Thomas Dowrick, Liam McDaid, Stephen Hall	Fan-in analysis of a leaky integrator circuit using charge transfer synapses.	Neurocomputing	2018	DBLP DOI BibTeX RDF
14	Mrinal Kumar 0001	On top fan-in vs formal degree for depth-3 arithmetic circuits.	Electron. Colloquium Comput. Complex.	2018	DBLP BibTeX RDF
14	Mrinal Kumar 0001	On top fan-in vs formal degree for depth-3 arithmetic circuits.	CoRR	2018	DBLP BibTeX RDF
14	Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi	Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics.	ICRC	2018	DBLP DOI BibTeX RDF
14	Gleb Posobin	Computing majority with low-fan-in majority queries.	CoRR	2017	DBLP BibTeX RDF
14	Christian Engels, B. V. Raghavendra Rao, Karteek Sreenivasaiah	On \varSigma \wedge \varSigma \wedge \varSigma Circuits: The Role of Middle \varSigma Fan-In, Homogeneity and Bottom Degree.	FCT	2017	DBLP DOI BibTeX RDF
14	Alexander S. Kulikov, Vladimir V. Podolskii	Computing Majority by Constant Depth Majority Circuits with Low Fan-in Gates.	STACS	2017	DBLP DOI BibTeX RDF
14	Mahshid Nasserian, Mohammad Kafi Kangi, Mohammad Maymandi-Nejad, Farshad Moradi	A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates.	Integr.	2016	DBLP DOI BibTeX RDF
14	Hisanao Akima, Yasuhiro Katayama, Masao Sakuraba, Koji Nakajima, Jordi Madrenas, Shigeo Sato	CMOS Majority Circuit with Large Fan-In.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
14	Alexander S. Kulikov, Vladimir V. Podolskii	Computing Majority by Constant Depth Majority Circuits with Low Fan-in Gates.	Electron. Colloquium Comput. Complex.	2016	DBLP BibTeX RDF
14	Alexander S. Kulikov, Vladimir V. Podolskii	Computing Majority by Constant Depth Majority Circuits with Low Fan-in Gates.	CoRR	2016	DBLP BibTeX RDF
14	Marshall Ball, Dana Dachman-Soled, Mukul Kulkarni, Tal Malkin	Non-Malleable Codes for Bounded Depth, Bounded Fan-in Circuits.	IACR Cryptol. ePrint Arch.	2016	DBLP BibTeX RDF
14	Marshall Ball, Dana Dachman-Soled, Mukul Kulkarni, Tal Malkin	Non-malleable Codes for Bounded Depth, Bounded Fan-In Circuits.	EUROCRYPT (2)	2016	DBLP DOI BibTeX RDF
14	Senthilkumar Jayapal, Janani Sainath Sigundey, Yipin Wu, EricT Tsai	Stack effect and logic restructuring on high Fan-in FinFETs logic gates.	ISIC	2016	DBLP DOI BibTeX RDF
14	Gaurav Sinha	Reconstruction of Real Depth-3 Circuits with Top Fan-In 2.	CCC	2016	DBLP DOI BibTeX RDF
14	Mohammad Asyaei	A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology.	Integr.	2015	DBLP DOI BibTeX RDF
14	Vikas Mahor, Manisha Pattanaik	Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
14	Gaurav Sinha	Reconstruction of Real depth-3 Circuits with top fan-in 2.	CoRR	2015	DBLP BibTeX RDF
14	Vikas Mahor, Manisha Pattanaik	Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
14	Mrinal Kumar 0001, Shubhangi Saraf	The Limits of Depth Reduction for Arithmetic Formulas: It's All About the Top Fan-In.	SIAM J. Comput.	2015	DBLP DOI BibTeX RDF
14	Chi-Ping Lin, Chuen-Fa Ni, I-Hsian Li, Chih-Heng Lu	Stochastic delineation of well capture zones in aquifers of Choushui River alluvial fan in central Taiwan.	ICCST	2015	DBLP DOI BibTeX RDF
14	Pavel Hrubes, Anup Rao 0001	Circuits with Medium Fan-In.	CCC	2015	DBLP DOI BibTeX RDF
14	M. Ohashi, H. Uemura, Katsuhiro Takenaga, S. Matsuo, Hirokazu Kubota, Y. Miyoshi	Simultaneous measurements of cores in multi-core fibre using OTDR and fan-in/out devices.	ECOC	2015	DBLP DOI BibTeX RDF
14	Pavel Hrubes, Anup Rao 0001	Circuits with Medium Fan-In.	Electron. Colloquium Comput. Complex.	2014	DBLP BibTeX RDF
14	Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello	Analyzing noise robustness of wide fan-in dynamic logic gates under process variations.	Int. J. Circuit Theory Appl.	2014	DBLP DOI BibTeX RDF
14	Alexander N. Tait, Paul R. Prucnal	Applications of wavelength-fan-in for high-performance distributed processing systems.	NANOARCH	2014	DBLP DOI BibTeX RDF
14	Hisanao Akima, Yasuhiro Katayama, Koji Nakajima, Masao Sakuraba, Shigeo Sato	Majority neuron circuit having large fan-in with non-volatile synaptic weight.	IJCNN	2014	DBLP DOI BibTeX RDF
14	Antriksh Goswami, Kiran Kumar Pattanaik, Amit Bharadwaj, Sourabh Bharti	Loss Rate Control Mechanism for Fan-in-burst Traffic in Data Center Network.	ANT/SEIT	2014	DBLP DOI BibTeX RDF
14	Mrinal Kumar 0001, Shubhangi Saraf	The limits of depth reduction for arithmetic formulas: it's all about the top fan-in.	STOC	2014	DBLP DOI BibTeX RDF
14	Ali Peiravi, Mohammad Asyaei	Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
14	Akira Suzuki, Kei Uchizawa, Xiao Zhou 0001	Energy and fan-in of logic circuits computing symmetric Boolean functions.	Theor. Comput. Sci.	2013	DBLP DOI BibTeX RDF
14	Mrinal Kumar 0001, Shubhangi Saraf	The Limits of Depth Reduction for Arithmetic Formulas: It's all about the top fan-in.	Electron. Colloquium Comput. Complex.	2013	DBLP BibTeX RDF
14	Mrinal Kumar 0001, Shubhangi Saraf	The Limits of Depth Reduction for Arithmetic Formulas: It's all about the top fan-in.	CoRR	2013	DBLP BibTeX RDF
14	Viswanath Annampedu, Meghanad D. Wagh	Decomposition of threshold functions into bounded fan-in threshold functions.	Inf. Comput.	2013	DBLP DOI BibTeX RDF
14	Zohar Shay Karnin, Partha Mukhopadhyay, Amir Shpilka, Ilya Volkovich	Deterministic Identity Testing of Depth-4 Multilinear Circuits with Bounded Top Fan-in.	SIAM J. Comput.	2013	DBLP DOI BibTeX RDF
14	Ali Peiravi, Mohammad Asyaei	Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates.	Integr.	2012	DBLP DOI BibTeX RDF
14	Rahul Singh, Gi-Moon Hong, Mino Kim, Jihwan Park, Woo-Yeol Shin, Suhwan Kim	Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers.	Integr.	2012	DBLP DOI BibTeX RDF
14	Vikas Mahor, Akanksha Chouhan, Manisha Pattanaik	A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate.	ISED	2012	DBLP DOI BibTeX RDF
14	Ankit Gupta 0001, Neeraj Kayal, Satyanarayana V. Lokam	Reconstruction of depth-4 multilinear circuits with top fan-in 2.	STOC	2012	DBLP DOI BibTeX RDF
14	Zohar Shay Karnin, Amir Shpilka	Black box polynomial identity testing of generalized depth-3 arithmetic circuits with bounded top fan-in.	Comb.	2011	DBLP DOI BibTeX RDF
14	Chung-Hsun Huang, Tzung-Lin Wu, Yi-Ming Wang	Adaptive Pseudo Dual Keeper for Wide Fan-In Dynamic Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
14	Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry	Novel Timing Yield Improvement Circuits for High-Performance Low-Power Wide Fan-In Dynamic OR Gates.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
14	Ye Yao, Wenming Zhang, BoQiang Shi, CaiZheng Wang	Experiment and simulation research of engine cooling fan in dump truck.	EMEIT	2011	DBLP DOI BibTeX RDF
14	Akira Suzuki, Kei Uchizawa, Xiao Zhou 0001	Energy and Fan-In of Threshold Circuits Computing Mod Functions.	TAMC	2011	DBLP DOI BibTeX RDF
14	Rahul Singh, Jae-Cheol Son, Ukrae Cho, Gunok Jung, Min-Su Kim, Hyoungwook Lee, Suhwan Kim	A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
14	William Matthews	A satisfiability algorithm for constant depth boolean circuits with unbounded fan-in gates.		2011	RDF