Search results for "Hardware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	John R. Koza, Martin A. Keane, Matthew J. Streeter	The Importance of Reuse and Development in Evolvable Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
28	Garrison W. Greenwood, Edward Ramsden, Saima Ahmed	An Empirical Comparison of Evolutionary Algorithms for Evolvable Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
28	John C. Gallagher	The Once and Future Analog Alternative: Evolvable Hardware and Analog Computation.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
28	A. P. Shanthi, Ranjani Parthasarathi	Exploring FPGA Structures for Evolving Fault Tolerant Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
28	Jeannette Plante, Harry C. Shaw, Lisa P. Mickens, Charles T. Johnson-Bey	Overview of Field Programmable Analog Arrays as Enabling Technology for Evolvable Hardware for High Reliability Systems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
28	Timothy G. W. Gordon, Peter J. Bentley	Towards Development in Evolvable Hardware.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
28	Daryl W. Bradley, Andrew M. Tyrrell	The Architecture For A Hardware Immune System.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
28	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum	Evolvable Hardware Solutions For Extreme Temperature Electronics.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
28	Jordan B. Pollack, Hod Lipson	The GOLEM Project: Evolving Hardware Bodies and Brains.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
28	Tatiana Kalganova	Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
28	Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara	Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
28	Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany, E. Cantó, Rafal Kielbik, Julio Faura, Josep Maria Insenser	Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
28	Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi	Opportunities and pitfalls in HDL-based system design.	ICCD	1996	DBLP DOI BibTeX RDF	textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems
28	Matthew F. Parkinson, Sri Parameswaran	Profiling in the ASP codesign environment.	ISSS	1995	DBLP DOI BibTeX RDF	Automated Synthesis and Partitioning system, Hardware/Software Codesign project, codesign environment, hardware/software codesign methodology, high-level profiling tools, virtual machines, software tools, C, computer architecture, profiling, systems analysis, circuit CAD, workstation, ASP, C code, dedicated hardware, execution profiling
28	Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seungjin Lee 0001, Hoi-Jun Yoo	A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains.	Graphics Hardware	2007	DBLP DOI BibTeX RDF	handheld systems, low-power, GPU, hardware architecture, 3D computer graphics
27	Geoffrey A. Frank, Bernard Clark, W. Bernard Schaming, William Kline	Hardware/Software Codesign from the RASSP Perspective.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
27	Masaya Iwata, Isamu Kajitani, Yong Liu 0012, Nobuki Kajihara, Tetsuya Higuchi	Implementation of a Gate-Level Evolvable Hardware Chip.	ICES	2001	DBLP DOI BibTeX RDF
27	Uwe Tangen, John S. McCaskill	Hardware Evolution with a Massively Parallel Dynamically Reconfigurable Computer: POLYP.	ICES	1998	DBLP DOI BibTeX RDF
27	Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl	System prototypes: virtual, hardware or hybrid?	DAC	2009	DBLP DOI BibTeX RDF	SystemC TLM, hardware/software co-verification, rapid prototype, embedded software, virtual prototype, virtual platform, system validation, FPGA prototype, system prototype
27	Lvdi Wang, Xi Wang, Peter-Pike J. Sloan, Li-Yi Wei, Xin Tong 0001, Baining Guo	Rendering from compressed high dynamic range textures on programmable graphics hardware.	SI3D	2007	DBLP DOI BibTeX RDF	games & GPUs, texturing techniques, graphics hardware, high dynamic range image, game programming, texture compression
27	Kekoa Proudfoot, William R. Mark, Svetoslav Tzvetkov, Pat Hanrahan	A real-time procedural shading system for programmable graphics hardware.	SIGGRAPH	2001	DBLP DOI BibTeX RDF	shading languages, rendering, graphics hardware, graphics systems
26	Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Galen C. Hunt, James R. Larus	Deconstructing process isolation.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	hardware isolated process (HIP), hardware protection domain, software isolated process (SIP), singularity
26	Patrick Rocke, Brian McGinley, John Maher, Fearghal Morgan, Jim Harkin	Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks.	ICES	2008	DBLP DOI BibTeX RDF	FPAA Hardware Evolution, Analogue Neural Networks, Spiking Neural Networks
26	Andrey Bogdanov, Thomas Eisenbarth 0001, Andy Rupp	A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations.	CHES	2007	DBLP DOI BibTeX RDF	A5/2, SMITH, cryptanalysis, GSM, Gaussian elimination, special-purpose hardware, linear systems of equations
26	Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto	Efficient Hardware for the Tate Pairing Calculation in Characteristic Three.	CHES	2005	DBLP DOI BibTeX RDF	tower fields, hardware accelerator, Tate pairing, characteristic three
26	Hyunuk Jung, Soonhoi Ha	Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	automatic hardware synthesis, VHDL, system level design, dataflow graph(DFG), HW/SW codesign
26	Stefan Fischer 0001, Jacek Wytrebowicz, Stanislaw Budkowski	Hardware/Software Co-Design of Communication Protocols.	EUROMICRO	1996	DBLP DOI BibTeX RDF	high performance distributed systems, system design techniques, standardized formal language Estelle, VHDL code, video-on-demand example, multimedia systems, multimedia systems, communication protocols, hardware/software codesign, C code
26	Tomas Akenine-Möller, Jacob Munkberg, Jon Hasselgren	Stochastic rasterization using time-continuous triangles.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
26	Saranyan A. Vigraham, John C. Gallagher	A Case for Using Minipop as the Evolutionary Engine in a CTRNN-EH Control Device: An Analysis of Area Requirements and Search Efficacy.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
26	Knut Arne Vinger, Jim Tørresen	Implementing Evolution of FIR-Filters Efficiently in an FPGA.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
26	Xin Yao 0001, Yong Liu 0012	Getting Most Out of Evolutionary Approaches.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
26	Adrian Stoica, Ricardo Salem Zebulum, Michael I. Ferguson, Didier Keymeulen, Vu Duong	Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
26	Pauline C. Haddow, Gunnar Tufte	Bridging The Genotype-Phenotype Mapping For Digital Fpgas.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
26	Hugo de Garis, Leo de Penning, Andrzej Buller, Derek Decesare	Early Experiments On The Cam-Brain Machine (Cbm).	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
26	Pauline C. Haddow, Piet van Remortel	From Here To There : Future Robust Ehw Technologies For Large Digital Designs.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
26	David A. Basin, Peter Del Vecchio	Verification Of Combinational Logic in Nuprl.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
26	Rajesh Sankaran, Brygg Ullmer, Jagannathan Ramanujam, Karun Kallakuri, Srikanth Jandhyala, Cornelius Toole, Christopher Laan	Decoupling interaction hardware design using libraries of reusable electronics.	TEI	2009	DBLP DOI BibTeX RDF	blades and tiles, decoupling TUI design, hardware toolkit, reusable hardware, modularity
26	Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo	PeaCE: A hardware-software codesign environment for multimedia embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	hardware-software cosimulation, embedded systems, design-space exploration, model-based design, Hardware-software codesign
26	Mahmoud Méribout, Mamoru Nakanishi	A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	real-time object segmentation, real-time object tracking, parallel hardware for video processing, hardware-software dessign, video processing
26	Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee	Formal hardware specification languages for protocol compliance verification.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Heterogeneous Hardware Logic, Hierarchical Annotated Action Diagrams, Lava, Objective VHDL, OpenVera, SpecC, Specification and Description Language, The Unified Modeling Language, Java, Statecharts, SystemC, Message Sequence Charts, Esterel, Live Sequence Charts, timing diagrams, hardware monitors, SystemVerilog, e, Property Specification Language
26	Katherine Compton, Scott Hauck	Flexibility measurement of domain-specific reconfigurable hardware.	FPGA	2004	DBLP DOI BibTeX RDF	programmable hardware, flexibility, reconfigurable hardware
26	Peter Groen, Panu Hämäläinen, Ben H. H. Juurlink, Timo Hämäläinen 0001	Accelerating the secure remote password protocol using reconfigurable hardware.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	secure remote password protocol, authentication, WLAN, hardware acceleration, reconfigurable hardware, modular exponentiation
26	Adam L. Young, Moti Yung	Bandwidth-Optimal Kleptographic Attacks.	CHES	2001	DBLP DOI BibTeX RDF	Leakage attacks, the Newton channel, design methodologies for asymmetric ciphers, kleptographic attacks, attack bandwidth, discrete logarithm based systems, tamper-proof hardware designs, public scrutiny, hardware technologies: EEPROM, ferroelectric, trust, DSA, ElGamal, subliminal channels, non-volatile memory
26	Valentina Salapura, Michael Gschwind	Hardware/Software Co-Design of a Fuzzy RISC Processor.	DATE	1998	DBLP DOI BibTeX RDF	hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism
26	Byung Kook Kim, Kang G. Shin	Scalable hardware earliest-deadline-first scheduler for ATM switching networks.	RTSS	1997	DBLP DOI BibTeX RDF	scalable hardware earliest deadline first link scheduler, ATM switching networks, fast hardware solution, switching speed, minimum size EDF priority queue, variable size FIFO queues, two port memory buffer, deadline folding technique, deadline resolution, asynchronous transfer mode, real time scheduler, simulation studies, EDF scheduler, clock cycles
26	Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr	Mapping multirate dataflow to complex RT level hardware models.	ASAP	1997	DBLP DOI BibTeX RDF	multirate dataflow mapping, complex RT level hardware models, digital signal processing systems, algorithm development phase, data flow specification, RTL target architecture, HDL code generation, cycle based timing model, ASIC design complexity, multirate dataflow graphs, signal processing, hardware architecture
26	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP DOI BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
26	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology.	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
26	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
26	Chen Liu 0013, Chengmo Yang	Defense Against Hardware Trojan Collusion in MPSoCs.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
26	Sheikh Ariful Islam, Srinivas Katkoori	Hardware Trojan Localization: Modeling and Empirical Approach.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
26	Anirban Sengupta, Mahendra Rathor	Hardware (IP) Watermarking During Behavioral Synthesis.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
26	Christian Pilato, Donatella Sciuto, Francesco Regazzoni 0001, Siddharth Garg, Ramesh Karri	Protecting Hardware IP Cores During High-Level Synthesis.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
26	Pranesh Santikellur, Rajat Subhra Chakraborty, Swarup Bhunia	Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
26	Farhath Zareen, Robert Karam	A Framework for Detecting Hardware Trojans in RTL Using Artificial Immune Systems.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
26	Fernando Herrera, Julio L. Medina, Eugenio Villar	Modeling Hardware/Software Embedded Systems with UML/MARTE: A Single-Source Design Approach.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
26	Grant Martin, Frank Schirrmeister, Yosinori Watanabe	Hardware/Software Codesign Across Many Cadence Technologies.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
26	Graziano Pravadelli, Davide Quaglia, Sara Vinco, Franco Fummi	Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
26	Wolfgang Ecker, Johannes Schreiner	Metamodeling and Code Generation in the Hardware/Software Interface Domain.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
26	Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, Shuvra S. Bhattacharyya	Introduction to Hardware/Software Codesign.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
26	Aviral Shrivastava, Jian Cai 0001	Hardware-Aware Compilation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
26	James Alfred Walker	Overcoming Variability Through Transistor Reconfiguration: Evolvable Hardware on the PAnDA Architecture.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
26	Alan F. T. Winfield, Jon Timmis	Evolvable Robot Hardware.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
26	Martin A. Trefzer, Andy M. Tyrrell	Devices and Architectures for Evolutionary Hardware.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
26	Andy M. Tyrrell, Martin A. Trefzer	Evolution, Development and Evolvable Hardware.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
26	Snaider Carrillo, Jim Harkin, Liam McDaid	Hierarchical Networks-on-Chip Architecture for Neuromorphic Hardware.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
26	Pauline C. Haddow	Developmental Evolvable Hardware.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
26	Michael A. Lones, Stephen L. Smith 0002	Medical Applications of Evolvable Hardware.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
26	Edward K. Blum	The Hardware Side.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
26	Yong Ki Lee, Lejla Batina, Dave Singelée, Bart Preneel, Ingrid Verbauwhede	Anti-counterfeiting, Untraceability and Other Security Challenges for RFID Systems: Public-Key-Based Protocols and Hardware.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
26	Helena Handschuh, Geert Jan Schrijen, Pim Tuyls	Hardware Intrinsic Security from Physically Unclonable Functions.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
26	Markus Ullmann, Matthias Vögeler	Contactless Security Token Enhanced Security by Using New Hardware Features in Cryptographic-Based Security Mechanisms.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
26	Kimmo Järvinen 0001, Vladimir Kolesnikov, Ahmad-Reza Sadeghi, Thomas Schneider 0003	Efficient Secure Two-Party Computation with Untrusted Hardware Tokens (Full Version).	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
26	Daniel Y. Deng, Andrew H. Chan, G. Edward Suh	Authentication of Processor Hardware Leveraging Performance Limits in Detailed Simulations and Emulations.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
26	Mohammad Tehranipoor, Berk Sunar	Hardware Trojan Horses.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
26	Nikolaj S. Bjørner, Robert Nieuwenhuis, Helmut Veith, Andrei Voronkov	10161 Executive Summary - Decision Procedures in Software, Hardware and Bioware.	Decision Procedures in Software, Hardware and Bioware	2010	DBLP BibTeX RDF
26	Nikolaj S. Bjørner, Robert Nieuwenhuis, Helmut Veith, Andrei Voronkov	10161 Abstracts Collection - Decision Procedures in Software, Hardware and Bioware.	Decision Procedures in Software, Hardware and Bioware	2010	DBLP BibTeX RDF
26	Hiroshi Yokoi, Kojiro Matsushita	Self-regulatory Hardware: Evolutionary Design for Mechanical Passivity on a Pseudo Passive Dynamic Walker.	Artificial Life Models in Hardware	2009	DBLP DOI BibTeX RDF
26	Jorge Guajardo, Bart Preneel, Pim Tuyls, Ahmad-Reza Sadeghi	09282 Abstracts Collection - Foundations for Forgery-Resilient Cryptographic Hardware.	Foundations for Forgery-Resilient Cryptographic Hardware	2009	DBLP BibTeX RDF
26	Jorge Guajardo, Bart Preneel, Ahmad-Reza Sadeghi, Pim Tuyls	09282 Executive Summary - Foundations for Forgery-Resilient Cryptographic Hardware.	Foundations for Forgery-Resilient Cryptographic Hardware	2009	DBLP BibTeX RDF
26	Annie A. M. Cuyt, Walter Krämer, Wolfram Luther, Peter W. Markstein	08021 Summary - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
26	Wolfram Luther, Annie A. M. Cuyt, Walter Krämer, Peter W. Markstein	08021 Abstracts Collection - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
26	Simon Heinzle, Gaël Guennebaud, Mario Botsch, Markus H. Gross	A Hardware Processing Unit for Point Sets.	Graphics Hardware	2008	DBLP DOI BibTeX RDF
26	Tetsuya Higuchi, Yong Liu 0012, Masaya Iwata, Xin Yao 0001	Introduction to Evolvable Hardware.	Evolvable Hardware	2006	DBLP DOI BibTeX RDF
26	Andy M. Tyrrell, Will Barker	The Poetic Hardware Device: Assistance for Evolution, Development and Learning.	Evolvable Hardware	2006	DBLP DOI BibTeX RDF
26	Didier Keymeulen, Michael I. Ferguson, Luke Breuer, Wolfgang Fink, Boris Oks, Chris Peay, Richard Terrile, Yen Cheng, Dennis Kim, Eric W. MacDonald, David Foor	Hardware Platforms for Electrostatic Tuning of Mems Gyroscope Using Nature-Inspired Computation.	Evolvable Hardware	2006	DBLP DOI BibTeX RDF
26	John R. Koza, Martin A. Keane, Matthew J. Streeter, Sameer H. Al-Sakran, Lee W. Jones	Human-Competitive Evolvable Hardware Created by Means of Genetic Programming.	Evolvable Hardware	2006	DBLP DOI BibTeX RDF
26	Isamu Kajitani, Masaya Iwata, Tetsuya Higuchi	A GA Hardware Engine and Its Applications.	Evolvable Hardware	2006	DBLP DOI BibTeX RDF
26	Jeremy W. Sheaffer, David P. Luebke, Kevin Skadron	The Visual Vulnerability Spectrum: Characterizing Architectural Vulnerability for Graphics Hardware.	Graphics Hardware	2006	DBLP DOI BibTeX RDF
26	Sven Woop, Gerd Marmitt, Philipp Slusallek	B-KD Trees for Hardware Accelerated Ray Tracing of Dynamic Scenes.	Graphics Hardware	2006	DBLP DOI BibTeX RDF
26	Marc Olano	Modified noise for evaluation on graphics hardware.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
26	John R. Koza, Martin A. Keane, Matthew J. Streeter	Routine High-Return Human-Competitive Evolvable Hardware.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
26	Jim Tørresen	Exploring Knowledge Schemes for Efficient Evolution of Hardware.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
26	Miguel Garvie, Adrian Thompson	Evolution of Combinatonial and Sequential On-Line Self-Diagnosing Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
26	Simon Harding, Julian F. Miller	A Scalable Platform for Intrinsic Hardware and in materio Ev olution.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
26	Koen Meinds, Bart Barenbrug	Resample Hardware for 3D Graphics.	Graphics Hardware	2002	DBLP DOI BibTeX RDF
26	Eric Chan, Ren Ng, Pradeep Sen, Kekoa Proudfoot, Pat Hanrahan	Efficient Partitioning of Fragment Shaders for Multipass Rendering on Programmable Graphics Hardware.	Graphics Hardware	2002	DBLP DOI BibTeX RDF
26	Jörg Schmittler, Ingo Wald, Philipp Slusallek	SaarCOR - A Hardware Architecture for Ray Tracing.	Graphics Hardware	2002	DBLP DOI BibTeX RDF
26	Yoshinori Dobashi, Tsuyoshi Yamamoto, Tomoyuki Nishita	Interactive Rendering of Atmospheric Scattering Effects Using Graphics Hardware.	Graphics Hardware	2002	DBLP DOI BibTeX RDF
26	Mark J. Harris, Greg Coombe, Thorsten Scheuermann, Anselmo Lastra	Physically-Based Visual Simulation on Graphics Hardware.	Graphics Hardware	2002	DBLP DOI BibTeX RDF