Search results for "PATMOS"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Rafailia-Eleni Karamani, Vasileios G. Ntinas, Ioannis Vourkas, Georgios Ch. Sirakoulis	1-D memristor-based cellular automaton for pseudo-random number generation.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Antonio Pullini, Davide Rossi, Germain Haugou, Luca Benini	μDMA: An autonomous I/O subsystem for IoT end-nodes.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Dominik Macko	Rapid power-management exploration using post-processing of the system-level simulation results.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Md Shahidul Alam, Alberto García Ortiz	An FPGA-based thermal emulation framework for multicore systems.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001	Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Savvas Sava	Fault-tolerant routing methodology for Networks-on-Chip.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Carol de Benito, Mohamad Moner Al Chawa, Josep L. Rosselló, Miquel Roca 0001, Rodrigo Picos, Ioannis Messaris, Spiridon Nikolaidis 0001	An analytical delay model for ReRAM memory cells.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Lennart Bamberg, Amir Najafi 0001, Alberto García Ortiz	Edge effect aware crosstalk avoidance technique for 3D integration.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach, Christopher Söll, Dietmar Fey	Prototyping memristors in digital system with an FPGA-based testing environment.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Sunil Malipatlolla, Ahmet Unutulmaz, Domenik Helms, Wolfgang Nebel	User dependent aging prediction model for automotive controllers with power electronics.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Islam A. K. M. Mahfuzul, Hidetoshi Onodera	Effect of supply voltage on random telegraph noise of transistors under switching condition.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Adrian Wheeldon, Jordan Morris, Danil Sokolov, Alex Yakovlev	Power proportional adder design for Internet of Things in a 65 nm process.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Moritz Weißbrich, Guillermo Payá Vayá, Lukas Gerlach 0001, Holger Blume, Ardalan Najafi, Alberto García Ortiz	FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza	High voltage recycling scheme to improve power consumption of regulated charge pumps.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Pasquale Davide Schiavone, Francesco Conti 0001, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini	Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Milan Babic, Milos Krstic	A substrate noise reduction methodology based on power domain separation of GALS subcomponents.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini	Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Dalibor Biolek, Zdenek Biolek, Viera Biolková	Memristive two-ports.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Stylianos-Georgios Papadopoulos, Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos	Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs.	PATMOS	2017	DBLP DOI BibTeX RDF
1	Dominik Macko	PMHLS 2.0: An automated optimization of power management during high-level synthesis.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Luca Larcher, Francesco Maria Puglisi, Andrea Padovani, Luca Vandelli, Paolo Pavan	Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee	TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Amir Najafi 0001, Lennart Bamberg, Ardalan Najafi, Alberto García Ortiz	Energy modeling of coupled interconnects including intrinsic misalignment effects.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira	Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Georgia Psychou, Tobias Gemmeke, Tobias G. Noll	A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir	Novel memristive logic architectures.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Hossein Aghababa, Mohammadreza Kolahdouz	A novel leakage power reduction technique for nano-scaled CMOS digital integrated circuits.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Malgorzata Michalska, J. J. Ahmad, Endri Bezati, Simone Casale Brunet, Marco Mattavelli	Performance estimation of program partitions on multi-core platforms.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Jason Xin Zheng, Teng Xu 0001, Miodrag Potkonjak	Securing embedded systems and their IPs with digital reconfigurable PUFs.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori	Hold-time violation analysis and fixing in near-threshold region.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Nasibeh Nasiri, Philip Colangelo, Oren Segal, Martin Margala, Wim Vanderbauwhede	Document classification systems in heterogeneous computing environments.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson 0001, Domenico Balsamo, Geoff V. Merrett, Bashir M. Al-Hashimi	Thermally-aware composite run-time CPU power models.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Pierre-Yves Peneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres, Sophiane Senni	Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Radi Husin Bin Ramlee, Mark Zwolinski	Using Iddt current degradation to monitor ageing in CMOS circuits.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Maria J. Avedillo, Juan Núñez 0002	Impact of pipeline in the power performance of tunnel transistor circuits.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Toufik Sadi, Liping Wang, Asen Asenov	Multi-scale electrothermal simulation and modelling of resistive random access memory devices.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Thomas Noulis	CMOS process transient noise simulation analysis and benchmarking.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Jie Liang, Liuyang Zhang, Nadine Azémard-Crestani, Pascal Nouet, Aida Todri-Sanial	Physical description and analysis of doped carbon nanotube interconnects.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Sebastian Volz, Haoxue Han	Optimized few layer graphene for heat spreading.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Peyman Pouyan, Esteve Amat, Said Hamdioui, Antonio Rubio 0001	RRAM variability and its mitigation schemes.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Matthias Jung 0001, Deepak M. Mathew, Éder F. Zulian, Christian Weis, Norbert Wehn	A new bank sensitive DRAMPower model for efficient design space exploration.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Parham Haririan, Alberto García Ortiz	Run-time schedulability check of real-time tasks for energy efficiency.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Klaus Hofmann, Tu Darmstadt	The long way to power efficient, high performance DRAMs.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Theodor Hillebrand, Timur Schafer, Nico Hellwege, Marco Erstling, Dagmar Peters-Drolshagen, Steffen Paul	Design and verification of analog CMOS circuits using the gm/ID-method with age-dependent degradation effects.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Vojtech Mrazek, Zdenek Vasícek	Automatic design of arbitrary-size approximate sorting networks with error guarantee.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Jia Guo, Teng Xu 0001, Theano Stavrinos, Miodrag Potkonjak	Enabling environmentally-powered indoor sensor networks with dynamic routing and operation.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Konstantinos Railis, Vasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris	Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detection.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Ahmad N. Abdulfattah, Charalampos C. Tsimenidis, Alex Yakovlev	Subthreshold-based m-sequence code generator for ultra low-power body sensor nodes.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar	Deduplication in resistive content addressable memory based solid state drive.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Erica Tena-Sánchez, Antonio J. Acosta 0001, Juan Núñez 0002	Secure cryptographic hardware implementation issues for high-performance applications.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Yahia Benmoussa, Eric Senn, Nicolas Derouineau, Nicolas Tizon, Jalil Boukhobza	Green metadata based adaptive DVFS for energy efficient video decoding.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Teng Xu 0001, Miodrag Potkonjak	Pipelining for dual supply voltages.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Jia Guo, Miodrag Potkonjak	Coarse-grained learning-based dynamic voltage frequency scaling for video decoding.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Alireza Rohani, Hassan Ebrahimi, Hans G. Kerkhoff	A software framework to calculate local temperatures in CMOS processors.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale	Energy efficiency of 2-step charging power-clock for adiabatic logic.	PATMOS	2016	DBLP DOI BibTeX RDF
1	James Myers, Pranay Prabhat, Anand Savanth, Sheng Yang, Rohan Gaddh	Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Sebastian Volz, Haoxue Han	Optimized few layer graphene for heat spreading.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera	Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano	Throughput balancing for energy efficient near-threshold manycores.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Philippe Dollfus, V. Hung Nguyen, V. Truong Tran, M. Chung Nguyen, Arnaud Bournel, Jerome Saint-Martin	Thermoelectric effects in graphene and graphene-based nanostructures using atomistic simulation.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Jorge L. Tonfat, Guilherme Flach, Ricardo Reis 0001	Leakage current analysis in static CMOS logic gates for a transistor network design approach.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Stephanie O. Ames, Vinicius Zanandrea, Ingrid F. V. Oliveira, Samuel P. Toledo, Cristina Meinhardt	Investigating PVT variability effects on full adders.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Aida Todri-Sanial	Investigation of electrical and thermal properties of carbon nanotube interconnects.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Hossein Aghababa, Mohammadreza Kolahdouz, Behjat Forouzandeh	Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Luca Larcher, Francesco Maria Puglisi, Andrea Padovani, Luca Vandelli, Paolo Pavan	Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials.	PATMOS	2016	DBLP DOI BibTeX RDF
1		26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016	PATMOS	2016	DBLP BibTeX RDF
1	Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Rodrigo Iga Jadue, Laurent Fesquet	Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits.	PATMOS	2016	DBLP DOI BibTeX RDF
1	Milan Babic, Xin Fan 0003, Milos Krstic	Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systems.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Soundous Chairat, Edith Beigné, Marc Belleville	Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Anca Mariana Molnos, Warody Lombardi, Diego Puschini, Julien Mottin, Suzanne Lesecq, Arnaud Tonda	Energy management via PI control for data parallel applications with throughput constraints.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Eduardo Valentin, Mario Salvatierra, Rosiane de Freitas, Raimundo S. Barreto	Response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platform.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Maurício Altieri, Suzanne Lesecq, Diego Puschini, Olivier Héron, Edith Beigné, Jorge Rodas	Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Krzysztof Kepa, Ritesh Soni, Peter M. Athanas	Inferring custom architectures from OpenCL.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter	Tejas: A java based versatile micro-architectural simulator.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Victor Lira, Eduardo Tavares	Energy-aware mapping for dependable virtual networks.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Vincent Canals, Antoni Morro, Antoni Oliver 0002, Miquel Lleo Alomar, Josep L. Rosselló	An unconventional computing technique for ultra-fast and ultra-low power data mining.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Nelson Alves Ferreira Neto, Joaquim Ranyere S. de Oliveira, Wagner Luiz Alves de Oliveira, João Carlos N. Bittencourt	VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Ron Diamant, Ran Ginosar, Christos P. Sotiriou	Asynchronous sub-threshold ultra-low power processor.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Fabio Frustaci, David T. Blaauw, Dennis Sylvester, Massimo Alioto	Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Rodrigo Fonseca Rocha Soares, Frank Sill Torres, Dirk Timmermann	Exploration of technology parameter values of integrated circuit technologies.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Lisa J. K. Durbeck, Joseph G. Tront, Nicholas J. Macias	Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architecture.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Jordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean-Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan	Dynamic current reduction of CMOS digital circuits through design and process optimization.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Ismael Seidel, André Beims Bräscher, José Luís Güntzel	Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Robert Najvirt, Andreas Steininger	A versatile and reliable glitch filter for clocks.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Emilie Garat, David Coriat, Edith Beigné, Leandro Stefanazzi	Unified Power Format (UPF) methodology in a vendor independent flow.	PATMOS	2015	DBLP DOI BibTeX RDF
1		25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2015, Salvador, Brazil, September 1-4, 2015	PATMOS	2015	DBLP BibTeX RDF
1	Anastasis Keliris, Vasilis Dimitsas, Olympia Kremmyda, Dimitris Gizopoulos, Michail Maniatakos	Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris	Constructing stability-based clock gating with hierarchical clustering.	PATMOS	2015	DBLP DOI BibTeX RDF
1	K. Gao, Y. Xu, Delong Shang, Fei Xia, Alex Yakovlev	Wideband dynamic voltage sensing mechanism for EH systems.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Hamid Mushtaq, Zaid Al-Ars, Koen Bertels	Calculation of worst-case execution time for multicore processors using deterministic execution.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Sheng Yang 0003, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis 0001, Bashir M. Al-Hashimi	Adaptive energy minimization of embedded heterogeneous systems using regression-based learning.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Sidinei Ghissoni, Eduardo Costa 0001, Ricardo Reis 0001	Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Roger Caputo-Llanos, Diego Sousa, Marco Terres, Guilherme Bontorin, Ricardo Reis 0001, Marcelo O. Johann	Energy-efficient Level Shifter topology.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Viviane Lucy Santos de Souza, Abel G. Silva-Filho, V. C. Wanderely	ABeeMap: A mapping algorithm based on multi-objective Artificial Bee Colony.	PATMOS	2015	DBLP DOI BibTeX RDF
1	Amir Morad, Leonid Yavits, Ran Ginosar	Efficient Dense and Sparse Matrix Multiplication on GP-SIMD.	PATMOS	2014	DBLP DOI BibTeX RDF
1	Oliver Schrape, Markus Appel, Frank Winkler 0001, Milos Krstic	Low-power design methodology for CML and ECL circuits.	PATMOS	2014	DBLP DOI BibTeX RDF
1	Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal	VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms.	PATMOS	2014	DBLP DOI BibTeX RDF
1	Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana	Robust sub-powered asynchronous logic.	PATMOS	2014	DBLP DOI BibTeX RDF
1	Akiya Baba, Nanoka Sumi, Vasily G. Moshnyaga	Impact of computation offloading on efficiency of wireless face recognition.	PATMOS	2014	DBLP DOI BibTeX RDF
1	Juan Núñez 0002, Maria J. Avedillo, Hector J. Quintero	DOE based high-performance gate-level pipelines.	PATMOS	2014	DBLP DOI BibTeX RDF

Publications at "PATMOS"( http://dblp.L3S.de/Venues/PATMOS )