Search results for "PI-Bus"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
41	Kousuke Kawamura, Naoto Mukai	Optimization of Transport Plan for On-Demand Bus System Using Electrical Vehicles.	KES (2)	2009	DBLP DOI BibTeX RDF
41	Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede	A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
41	Sujan Pandey, Rolf Drechsler	Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs.	DATE	2008	DBLP DOI BibTeX RDF
41	Xi Chen 0068, Robert P. Dick, Alok N. Choudhary	Operating System Controlled Processor-Memory Bus Encryption.	DATE	2008	DBLP DOI BibTeX RDF
41	Tilen Ma, Evangeline F. Y. Young	TCG-based multi-bend bus driven floorplanning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
41	Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi	A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck.	FPL	2008	DBLP DOI BibTeX RDF
41	Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner	Process variations aware robust on-chip bus architecture synthesis for MPSoCs.	ISCAS	2008	DBLP DOI BibTeX RDF
41	Stephan Eberle	Adaptive Internet Integration of Field Bus Systems.	IEEE Trans. Ind. Informatics	2007	DBLP DOI BibTeX RDF
41	Sujan Pandey, Christian Genz, Rolf Drechsler	Co-synthesis of custom on-chip bus and memory for MPSoC architectures.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
41	Xiaolan Zhang 0003, Jim Kurose, Brian Neil Levine, Donald F. Towsley, Honggang Zhang 0003	Study of a bus-based disruption-tolerant network: mobility modeling and impact on routing.	MobiCom	2007	DBLP DOI BibTeX RDF	mobility trace modeling, DTN, epidemic routing
41	Hui Kong 0002, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal	Optimal bus sequencing for escape routing in dense PCBs.	ICCAD	2007	DBLP DOI BibTeX RDF
41	Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak	Latency-Guided On-Chip Bus-Network Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Sujan Pandey, Tudor Murgan, Manfred Glesner	Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
41	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Constraint-driven bus matrix synthesis for MPSoC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
41	Sujan Pandey, Manfred Glesner	Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.	ISCAS	2006	DBLP DOI BibTeX RDF
41	Nattawut Thepayasuwan, Alex Doboli	Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
41	Haris Lekatsas, Jörg Henkel, Wayne H. Wolf	Approximate arithmetic coding for bus transition reduction in low power designs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
41	Suresh Srinivasan, Lin Li 0002, Narayanan Vijaykrishnan	Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures.	DATE	2005	DBLP DOI BibTeX RDF
41	Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
41	Suvodeep Gupta, Srinivas Katkoori	A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk.	DATE	2004	DBLP DOI BibTeX RDF
41	Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim	Resource-constrained low-power bus encoding with crosstalk delay elimination.	ASP-DAC	2004	DBLP DOI BibTeX RDF
41	YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang 0001	A New Maximal Diagnosis Algorithm for Bus-structured Systems.	ITC	2003	DBLP DOI BibTeX RDF
41	Rung-Bin Lin, Chi-Ming Tsai	Theoretical analysis of bus-invert coding.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
41	Diana Hecht, Constantine Katsinis	Protocols for Fault-Tolerant Distributed-Shared-Memory on the SOME-Bus Multiprocessor Architecture.	IPDPS	2002	DBLP DOI BibTeX RDF
41	Dongxiao Li, Qingdong Yao, Peng Liu 0016, Li Zhou	A bus arbitration scheme for HDTV decoder SoC.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
41	Wonjong Noh, Sangkyung Kim, Dong-Ho Kim, Youngsik Ma, Sunshin An	Adaptive Bus Model for Distributed Multimedia Stream in Mobile Computing Environments.	ICOIN	2001	DBLP DOI BibTeX RDF
41	Jochen Liedtke, Marcus Völp, Kevin Elphinstone	Preliminary thoughts on memory-bus scheduling.	ACM SIGOPS European Workshop	2000	DBLP DOI BibTeX RDF
41	Andrea Acquaviva, Riccardo Scarsi	A spatially-adaptive bus interface for low-switching communication (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
41	Constantine Katsinis	Distributed-Shared-Memory Support on the Simultaneous Optical Multiprocessor Exchange Bus.	MASCOTS	1998	DBLP DOI BibTeX RDF
41	Gregory E. Beers, Lizy Kurian John	Novel Memory Bus Driver/Receiver Architecture for Higher Throughput.	VLSI Design	1998	DBLP DOI BibTeX RDF
41	Laxmi N. Bhuyan, Ashwini K. Nanda	Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors.	SPDP	1991	DBLP DOI BibTeX RDF
40	Gianluca Casarosa, Michele Apuzzo, Luca Fanucci, Bruno Sarti	Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites.	DSD	2006	DBLP DOI BibTeX RDF
40	Hua Wang, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement.	ASP-DAC	2004	DBLP DOI BibTeX RDF
38	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Extending the transaction level modeling approach for fast communication architecture exploration.	DAC	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
38	Jui-Hua Li, Nam Ling	An efficient video decoder design for MPEG-2 MP@ML.	ASAP	1997	DBLP DOI BibTeX RDF	video decoder design, MPEG-2 MP@ML, video decoder architecture, function-specific processing blocks, variable-length decoder, inverse 2-D discrete cosine transform, motion compensation unit, bus-monitoring model, bus arbitration schemes, DRAM accesses, motion compensation, buffer sizes
38	Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har	Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS
38	Charbel J. Akl, Magdy A. Bayoumi	Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transition skew coding, global on-chip interconnects, bus encoding technique, encoding latencies, decoding latencies, 90 nm
38	Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra	Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	address bus, low power, encoding, energy dissipation
38	Enrico Macii, Massimo Poncino, Sabino Salerno	Combining wire swapping and spacing for low-power deep-submicron buses.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	low-power design, physical design, crosstalk, bus encoding
38	W. J. Bainbridge, Stephen B. Furber	Asynchronous Macrocell Interconnect using MARBLE.	ASYNC	1998	DBLP DOI BibTeX RDF	Macrocell Bus, VLSI, Interconnect, Asynchronous
38	Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito	SSM-MP: more scalability in shared-memory multi-processor.	ICCD	1995	DBLP DOI BibTeX RDF	SSM-MP, shared-memory multi-processor, cache refill latency, bus bottle neck problem, MTag, scalability, shared memory systems, cache coherency, memory architecture, multi-processor system
38	David W. Pritty, Duncan N. Smeed, Norman L. Lawrie	A new class of high speed LAN access protocols based on the principle of timed packet release.	LCN	1995	DBLP DOI BibTeX RDF	timed packet release, high speed local area network, bus structures, TPR, performance evaluation, performance, discrete event simulation, discrete event simulation, local area networks, access protocols, access protocols, comparative evaluation, high speed LAN
37	Amitava Datta	Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	pipelined bus, reconfigurable bus, matrix multiplication, addition, optical computing, prefix sum
37	Jih-Fu Tu, Chih-Yung Chen	An Effective Bus-Band Arbiter for Processors Communication.	AINA (2)	2004	DBLP DOI BibTeX RDF	Bus-based arbitration circuit, multistage bus network (MBN), M-to-B Arbiter and inter-processor communication
37	Amitava Datta, Subbiah Soundaralakshmi, Robyn A. Owens	Fast Sorting Algorithms on a Linear Array with a Reconfigurable Pipelined Bus System.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	reconfigurable bus, pipelined communication, merging, sorting algorithm, optical bus, deterministic sampling
37	Haris Lekatsas, Jörg Henkel	ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	bus invert, low power, bus encoding
37	Sushil Kumar, Anura P. Jayasumana	Request based channel access protocol on folded bus topology.	LCN	1995	DBLP DOI BibTeX RDF	channel access protocol, folded bus topology, Request Based Channel Access, RBCA protocol, bandwidth request, dedicated monitor node, folded bus, multichannel optical networks, protocols, local area networks, optical communication, data transmission
37	Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra	Power Consumption of Fault Tolerant Busses.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
37	Kimish Patel, Wonbok Lee, Massoud Pedram	In-order pulsed charge recycling in off-chip data buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	data buses, power, charge recycling
37	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	SiPS	2006	DBLP DOI BibTeX RDF
37	Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
37	Kanishka Lahiri, Anand Raghunathan	Power analysis of system-level on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
37	Mountassar Maamoun, Abdelhalim Benbelkacem, Daoud Berkani, Abderrezak Guessoum	Interfacing in Microprocessor-based Systems with a Fast Physical Addressing.	IWSOC	2003	DBLP DOI BibTeX RDF	Software/hardware System, Fast Physical Addressing, Interfacing, DMA
37	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	Bus via reduction based on floorplan revising.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	floorplan revising, via reduction, bus routing
37	Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu	A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus-invert, coupling, interconnect delay
37	Horng-Ren Tsai	Parallel Algorithms for the Weighted Distance Transform on Linear Arrays with a Reconfigurable Pipelined Bus System.	ICA3PP	2009	DBLP DOI BibTeX RDF	linear array with a reconfigurable pipelined bus system, parallel algorithms, image processing, Distance transform
37	Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra	Simultaneous Switching Noise: The Relation between Bus Layout and Coding.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques
37	Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura	Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.	PATMOS	2008	DBLP DOI BibTeX RDF	Arrival time variation, coupling power, power estiamtion, low power coding, on-chip bus
37	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi	On-Chip Optical Technology in Future Bus-Based Multicore Designs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	optical technology, snoopy bus, chip multiprocessor, on-chip interconnect
37	Thomas William Ainsworth, Timothy Mark Pinkston	On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus.	NOCS	2007	DBLP DOI BibTeX RDF	Element Interconnect Bus, heterogeneous multicore, network characterization, interconnection networks, network-on-chip, Cell Broadband Engine, on-chip network, performance bottleneck
37	Fan Mo, Robert K. Brayton	Semi-detailed bus routing with variation reduction.	ISPD	2007	DBLP DOI BibTeX RDF	routing, variation, bus
37	Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang	A bus architecture for crosstalk elimination in high performance processor design.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	instruction/data bus, architecture, high performance, crosstalk
37	Darren J. Reed, Peter C. Wright	Experiencing BLISS when becoming a bus passenger.	Conference on Designing Interactive Systems	2006	DBLP DOI BibTeX RDF	experience framework, experience scenarios, real-time bus information, conversation analysis
37	Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har	High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	asynchronous on-chip bus, in-order completion, multiple issue, out-of-order completion, SoC, GALS
37	Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design.	DATE	2004	DBLP DOI BibTeX RDF	Bus Configuration, genetic algorithm, Optimization, Platform-based design, SoC design
37	Xiaotong Zhuang, Tao Zhang 0037, Santosh Pande	HIDE: an infrastructure for efficiently protecting information leakage on the address bus.	ASPLOS	2004	DBLP DOI BibTeX RDF	address bus leakage protection, secure processor
37	Trevor Meyerowitz, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli	A tool for describing and evaluating hierarchical real-time bus scheduling policies.	DAC	2003	DBLP DOI BibTeX RDF	bus scheduling, scheduling, metrics, hybrid scheduling
37	Yijie Han, Yi Pan 0001, Hong Shen 0001	Sublogarithmic Deterministic Selection on Arrays with a Reconfigurable Optical Bus.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	parallel algorithms, selection, Analysis of algorithms, massive parallelism, optical bus
37	Horng-Ren Tsai	Parallel Algorithms for the Medial Axis Transform on Linear Arrays with a Reconfigurable Pipelined Bus System.	ICPADS	2002	DBLP DOI BibTeX RDF	linear array with a reconfigurable pipelined bus system, computer vision, parallel algorithms, image processing, image compression, Medial axis transform
37	Huan-Yu Tu, Lois Wright Hawkes	Families of Optimal Fault-Tolerant Multiple-Bus Networks.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	partial-connection, multiple-bus, Fault tolerance, interconnection networks, multiprocessor, self-routing, randomized routing
37	Cecilia Metra, Michele Favalli, Bruno Riccò	Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	bus lines, diagnosis, transient faults, On-line testing, delay faults, self-checking, crosstalk faults
37	Peter James Aldworth	System-on-a-Chip Bus Architecture for Embedded Applications.	ICCD	1999	DBLP DOI BibTeX RDF	architecture, interconnect, latency, infrastructure, system-on-a-chip, bus, capacitance, peripherals
37	Jung-Joon Kim, Ahmed El-Amawy	Performance and Architectural Features of Segmented Multiple Bus System.	ICPP	1999	DBLP DOI BibTeX RDF	flit buffer, segment, wormhole routing, mean value analysis, multiple bus systems
37	Si-Qing Zheng, Yueming Li	A Pipelined TDM Optical Bus with Improved Performance.	ISPAN	1997	DBLP DOI BibTeX RDF	reconfigurable bus, parallel architecture, reconfigurable architecture, optical interconnection, optical switch
37	H. Bekker, E. J. Dijkstra	Delay-Insensitive Synchronization on a Message-Passing Architecture with an Open Collector Bus.	PDP	1996	DBLP DOI BibTeX RDF	delay-insensitive synchronization, open collector bus, high latency, constraint algorithm, SHAKE, Constraint Molecular Dynamics simulation, ring architecture, delay insensitive algorithm, performance evaluation, performance, parallel algorithms, parallel algorithms, parallel architectures, message passing, multiprocessor interconnection networks, multiprocessor interconnection networks, synchronisation, digital simulation, physics computing, system buses, communication time, message passing architecture
37	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
37	Biing-Feng Wang, Gen-Huey Chen	Constant Time Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Arrays with Reconfigurable Bus Systems.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	related graph problems, reconfigurable bus systems, parallel algorithms, graph theory, minimum spanning trees, bipartite graphs, transitive closure, transitive closure, connected components, processor arrays, undirected graph, bridges, biconnected components, graph problems, articulation points
36	Chien-Yen Chang, Chai-Chun Li	Visual and Operational Impacts of Variable Speed Limit Signs on Bus Drivers on Freeways Using Driving Simulator.	APSCC	2008	DBLP DOI BibTeX RDF
36	Lei Li, Zheng Cao, Mingyu Chen 0001, Jianping Fan 0002	Design and Evaluation of Optical Bus in High Performance Computer.	ICYCS	2008	DBLP DOI BibTeX RDF
36	Dae Hyun Kim 0004, Sung Kyu Lim	Global bus route optimization with application to microarchitectural design exploration.	ICCD	2008	DBLP DOI BibTeX RDF
36	Truong Quang Vinh, Young-Chul Kim 0001	A low power crosstalk-free bus encoding using genetic algorithm.	AICCSA	2008	DBLP DOI BibTeX RDF
36	Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov	Protecting bus-based hardware IP by secret sharing.	DAC	2008	DBLP DOI BibTeX RDF	cryptography, manufacturing, integrated circuits, computer crime
36	Masaru Takesue	The SKB: A Semi-Completely-Connected Bus for On-Chip Systems.	NPC	2007	DBLP DOI BibTeX RDF
36	Fan Mo, Robert K. Brayton	A simultaneous bus orientation and bused pin flipping algorithm.	ICCAD	2007	DBLP DOI BibTeX RDF
36	Chandan Giri, Santanu Chattopadhyay	Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Chun-Mok Chung, Jihong Kim 0001, Dohyung Kim	Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcasts.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	broadcast filtering, low-energy cache coherency, MPSoC
36	Peter Wohl, John A. Waicukauski, Sanjay Patel	Automated Design and Insertion of Optimal One-Hot Bus Encoders.	VTS	2007	DBLP DOI BibTeX RDF
36	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	FABSYN: floorplan-aware bus architecture synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
36	Brock J. LaMeres, Sunil P. Khatri	Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission.	DATE	2006	DBLP DOI BibTeX RDF
36	Ru Yang, Gang Feng, Donghai Li	Power Optimization for Bus on Multimedia SoC.	IIH-MSP	2006	DBLP DOI BibTeX RDF
36	Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.	ISQED	2005	DBLP DOI BibTeX RDF
36	Peter Petrov, Alex Orailoglu	Low-power instruction bus encoding for embedded processors.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
36	Dongwan Shin, Samar Abdi, Daniel Gajski	Automatic generation of bus functional models from transaction level models.	ASP-DAC	2004	DBLP DOI BibTeX RDF
36	Constantine Katsinis	A Model of Distributed-Shared-Memory on the SOME-Bus Architecture.	IPDPS	2004	DBLP DOI BibTeX RDF
36	Constantine Katsinis, Diana Hecht	SOME-Bus-NOW: A Network of Workstations with Broadcast.	NCA	2003	DBLP DOI BibTeX RDF
36	Abhik Roychoudhury, Tulika Mitra, S. R. Karri	Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol.	DATE	2003	DBLP DOI BibTeX RDF
36	Masaru Takahashi, Boon-Keat Tan, Hiroshi Iwamura, Toshimasa Matsuoka, Kenji Taniguchi 0001	A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
36	Hairong Sun, Xinyu Zang, Kishor S. Trivedi	Performance of broadcast and unknown server (BUS) in ATM LAN emulation.	IEEE/ACM Trans. Netw.	2001	DBLP DOI BibTeX RDF	LAN emulation, broadcast and unknown server, stochastic petri net package, ATM, stochastic reward nets
36	Kanna Shimizu, David L. Dill, Ching-Tsun Chou	A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® ItaniumTM Processor Bus Protocol.	CHARME	2001	DBLP DOI BibTeX RDF
36	Bruce R. Childers, Tarun Nakra	Reordering Memory Bus Transactions for Reduced Power Consumption.	LCTES	2000	DBLP DOI BibTeX RDF