Search results for "RLC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Taeyong Je, Yungseon Eo	Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching.	ISQED	2006	DBLP DOI BibTeX RDF
30	Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee	Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.	APCCAS	2006	DBLP DOI BibTeX RDF
30	Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He 0001	A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.	ASP-DAC	2005	DBLP DOI BibTeX RDF
30	Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
30	Yici Cai, Bin Liu 0007, Qiang Zhou 0001, Xianlong Hong	Integrated routing resource assignment for RLC crosstalk minimization.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
30	Aziz S. Inan, Peter M. Osterberg	Special singularity integrals encountered in electric circuits [RLC circuit examples].	ISCAS (2)	2005	DBLP DOI BibTeX RDF
30	Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam	A closed-form delay formula for on-chip RLC interconnects in current-mode signaling.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
30	Lakshmi Kalpana Vakati, Janet Meiling Wang	A new multi-ramp driver model with RLC interconnect load.	ISPD	2004	DBLP DOI BibTeX RDF	inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance
30	Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Analytical Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on Switching.	ISQED	2004	DBLP DOI BibTeX RDF
30	Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester	Optimal Inductance for On-chip RLC Interconnections.	ICCD	2003	DBLP DOI BibTeX RDF
30	Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter	Realizable reduction of RLC circuits using node elimination.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
30	Kai-Sheng Lu	Some structural conditions under which an RLC network is controllable over F(z).	ISCAS (1)	2003	DBLP DOI BibTeX RDF
30	Dorothy Kucar, Anthony Vannelli	InterconnectionModelling Using Distributed RLC Models.	IWSOC	2003	DBLP DOI BibTeX RDF
30	Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter	Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.	DATE	2002	DBLP DOI BibTeX RDF
30	Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti 0001	Timing analysis of tree-like RLC circuits.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
30	Ji-Eun Kang, Dong-Min Kim, Yong-Chul Shin, Hee-Yoon Park, Jai-Yong Lee	Performance Evaluation of TCP over WCDMA RLC.	ICOIN (2)	2002	DBLP DOI BibTeX RDF
30	Himanshu Kaul, Dennis Sylvester, David T. Blaauw	Active shielding of RLC global interconnects.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
30	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driving point model for on-chip RLC interconnects.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
30	Payam Heydari, Massoud Pedram	Balanced truncation with spectral shaping for RLC interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF	MATLAB
30	Rui Wang, Kaushik Roy 0001, Cheng-Kok Koh	Short-circuit power analysis of an inverter driving an RLC load.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
30	Andrew B. Kahng, Sudhakar Muddu	An analytical delay model for RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
30	Qing Zhu, Wayne Wei-Ming Dai	High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
30	Carol V. Gura, Jacob A. Abraham	Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics.	DAC	1988	DBLP BibTeX RDF
22	Jahangir Dadkhah Chimeh, Mohammad Hakkak, Paeiz Azmi, Hamidreza Bakhshi	Internet connection with UMTS.	Ann. des Télécommunications	2009	DBLP DOI BibTeX RDF	TCP/ARQ, Fading channel, UTRAN
22	Sampo Tuuna, Li-Rong Zheng 0001, Jouni Isoaho, Hannu Tenhunen	Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
22	Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng 0001	Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
22	Malek Boussif, Jeroen Wigard, Troels E. Kolding, Nina A. H. Madsen	Errors on the HSUPA E-HICH Channel and Their Effect on System Performance.	VTC Spring	2007	DBLP DOI BibTeX RDF
22	Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud	Frequency Selective Model Order Reduction via Spectral Zero Projection.	ASP-DAC	2007	DBLP DOI BibTeX RDF
22	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).	ISCAS	2007	DBLP DOI BibTeX RDF
22	Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu 0001	General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
22	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Non-gaussian statistical interconnect timing analysis.	DATE	2006	DBLP DOI BibTeX RDF
22	Giulio Antonini, Giuseppe Ferri	A ladder network delay model for coupled interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Juan J. Alcaraz, Fernando Cerdán	Using Buffer Management in 3G Radio Bearers to Enhance End-to-End TCP Performance.	AINA (2)	2006	DBLP DOI BibTeX RDF
22	Jinwook Jang, Sheng Xu, Wayne P. Burleson	Jitter in Deep Sub-Micron Interconnect.	ISVLSI	2005	DBLP DOI BibTeX RDF
22	Oumer M. Teyeb, Malek Boussif, Troels B. Sørensen, Jeroen Wigard, Preben E. Mogensen	Emulation Based Performance Investigation of FTP File Downloads over UMTS Dedicated Channels.	ICN (1)	2005	DBLP DOI BibTeX RDF
22	Lonnie J. Love, John F. Jansen, François G. Pin	On the Modeling of Robots Operating on Ships.	ICRA	2004	DBLP DOI BibTeX RDF
22	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.	PATMOS	2004	DBLP DOI BibTeX RDF
22	James D. Ma, Rob A. Rutenbar	Interval-valued reduced order statistical interconnect modeling.	ICCAD	2004	DBLP DOI BibTeX RDF
22	Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong	Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.	ISQED	2004	DBLP DOI BibTeX RDF
22	Qinwei Xu, Pinaki Mazumder	Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
22	Jérôme Lescot, François J. R. Clément	Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
22	Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni	Effects of Temperature in Deep-Submicron Global Interconnect Optimization.	PATMOS	2003	DBLP DOI BibTeX RDF
22	Timo Palenius, Janne Roos	An efficient reduced-order interconnect macromodel for time-domain simulation.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
22	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	on-chip inductance, shielding effect, propagation delay, interconnect modeling, gate delay
22	Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim	Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
22	Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects.	SLIP	2002	DBLP DOI BibTeX RDF	TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave
22	Jun Chen 0008, Lei He 0001	Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	interconnect design
22	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	PRIMA: passive reduced-order interconnect macromodeling algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
22	Jason Cong, David Zhigang Pan, Lei He 0001, Cheng-Kok Koh, Kei-Yong Khoo	Interconnect design for deep submicron ICs.	ICCAD	1997	DBLP BibTeX RDF	required-arrival-time Steiner tree higher-order moment signal delay and integrity
22	Ibrahim M. Elfadel, David D. Ling	Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks.	DAC	1997	DBLP DOI BibTeX RDF
22	Daksh Lehther, Sachin S. Sapatnekar	Clock tree synthesis for multi-chip modules.	ICCAD	1996	DBLP DOI BibTeX RDF	Pade' approximants, Interconnect optimization
22	Curtis L. Ratzlaff, Lawrence T. Pillage	RICE: rapid interconnect circuit evaluation using AWE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Lawrence T. Pillage, Ronald A. Rohrer	Asymptotic waveform evaluation for timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
22	J. V. R. Ravindra, M. B. Srinivas	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	krylov subspace techniques, monte-carlo simulation, model order reduction, rlc
22	Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu	Piece-wise approximations of RLCK circuit responses using moment matching.	DAC	2005	DBLP DOI BibTeX RDF	RC, RLCK circuits, interconnect timing analysis, moments, RLC
22	Shannon V. Morton	On-Chip Inductance Issues in Multiconductor Systems.	DAC	1999	DBLP DOI BibTeX RDF	alpha microprocessor, cross-talk, interconnect, noise, inductance, transmission line, capacitance, resistance, buses, semiconductor, RLC
21	Juan J. Alcaraz, Fernando Cerdán	Slope based discard: a buffer management scheme for 3G links supporting TCP traffic.	IWCMC	2006	DBLP DOI BibTeX RDF	TCP over 3G links, radio link control (RLC)
21	Payam Heydari, Massoud Pedram	Interconnect Energy Dissipation in High-Speed ULSI Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Ultra-large integrated (ULSI) circuits, Energy dissipation CMOS circuits, RLC circuits, Interconnect, Transmission lines
19	Ahmed S. Elwakil, Anis Allagui, Ahmed Ibrahim El-Mesady, Amr Elsonbaty, Sohaib Majzoub, Brent J. Maundy	Chaos in Inter-State-Controlled RLC Networks.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
19	Zi-Ming Wang 0001, Xudong Zhao 0001, Xiaodi Li, Xianfu Zhang, Rui Mu	Energy-Based Control for Switched Uncertain Port-Controlled Hamiltonian Systems With Its Application to RLC Circuit Systems.	IEEE Trans. Syst. Man Cybern. Syst.	2024	DBLP DOI BibTeX RDF
19	Muzaffer Ates, Muhammet Ates	Stability and passivity analysis of higher-order differential systems inspired by RLC circuits.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
19	Mark Keran, Anestis Dounavis	An Analytic RLC Model for Coupled Interconnects Which Uses a Numerical Inverse Laplace Transform.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
19	Dusan Zorica, Stevan M. Cveticanin	Dissipative and generative fractional RLC circuits in the transient regime.	Appl. Math. Comput.	2023	DBLP DOI BibTeX RDF
19	Matap Shankar, Swaroop Nandan Bora	Generalized Ulam-Hyers-Rassias Stability of Solution for the Caputo Fractional Non-instantaneous Impulsive Integro-differential Equation and Its Application to Fractional RLC Circuit.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
19	Siddhanta Borah, R. Kumar	Designing an Optimized RLC Network for Efficient Soil Moisture Data Logger System Using IoT.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
19	Pritam M. Gharat, Narges Shadab, Shrey Tiwari, Shuvendu K. Lahiri, Akash Lal	Resource Leak Checker (RLC#) for C# Code using CodeQL.	CoRR	2023	DBLP DOI BibTeX RDF
19	Yutao Xu, Qiang Ye, Yujie Tang, Hui Huang, Kamran Sattar Awaisi	RLC: A Reinforcement Learning Based Charging Scheme for Battery Swap Stations.	GLOBECOM	2023	DBLP DOI BibTeX RDF
19	Sumit Kumar 0001, Chandan Kumar Sheemar, Jorge Querol, Amirhossein Nik, Symeon Chatzinotas	Experimental Study of the Effects of RLC Modes for 5G-NTN Applications Using OpenAirInterface5G.	GLOBECOM (Workshops)	2023	DBLP DOI BibTeX RDF
19	Dong Liu, Hong Zhang 0003, Xiaoting Xiao, Qiuping Ma, Haoran Li, Guiyun Tian 0001, Bin Gao 0003, Jianbo Wu	RLC Parameters Measurement and Fusion for High-Sensitivity Inductive Sensors.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
19	Kristian Haska, Dusan Zorica, Stevan M. Cveticanin	Frequency Characteristics of Dissipative and Generative Fractional RLC Circuits.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
19	Siavash Kananian, George Alexopoulos, Ada S. Y. Poon	Robust Wireless Interrogation of Fully-Passive RLC Sensors.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
19	Yao Huang, Yao-Lin Jiang, Kang-Li Xu	Model Order Reduction of RLC Circuit System Modeled by Port-Hamiltonian Structure.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
19	Héléna Shourick, Damien Tromeur-Dervout, Laurent Chedot	Accelerating the convergence of Dynamic Iteration method with Restricted Additive Schwarz splitting for the solution of RLC circuits.	CoRR	2022	DBLP BibTeX RDF
19	Bartlomiej Sulikowski, Krzysztof Galkowski, Dongdong Zhao 0002, Li Xu 0004	Stability investigation and control synthesis of RLC ladder circuits modeled as uncertain spatially interconnected systems.	ICARCV	2022	DBLP DOI BibTeX RDF
19	Srihari Das Sunkada Gopinath, Aneesh Deshmukh, Nayan Ostwal	Efficient Timer Optimization Method for RLC in Mobile Communication.	GLOBECOM (Workshops)	2022	DBLP DOI BibTeX RDF
19	Saeed Ghaneei Aarani, MohammadReza Mehranpouy, Benoit Gosselin	A Novel Ultra-Wideband Low-Noise Amplifier Using an Extended Bandwidth RLC Topology.	NEWCAS	2022	DBLP DOI BibTeX RDF
19	Nestor Tsafack, Abdullah M. Iliyasu, Jean De Dieu Nkapkop, Zeric Tabekoueng Njitacke, Jacques Kengne, Bassem Abd-El-Atty, Akram Belazi, Ahmed A. Abd El-Latif 0001	A memristive RLC oscillator dynamics applied to image encryption.	J. Inf. Secur. Appl.	2021	DBLP DOI BibTeX RDF
19	Mikel Irazabal, Elena López-Aguilera, Ilker Demirkol, Robert Schmidt 0001, Navid Nikaein	Preventing RLC Buffer Sojourn Delays in 5G.	IEEE Access	2021	DBLP DOI BibTeX RDF
19	Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis	Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
19	Peyman Rezaei Baravati, Seyed Mohammad Hassan Hosseini, Majid Moazzami	Comparing the New Improved RLC and CMTL Models for Measuring Partial Discharge in Transformer Winding.	IEEE Trans. Instrum. Meas.	2021	DBLP DOI BibTeX RDF
19	Issam El Hamdi, Alessandro N. Vargas, Hassane Bouzahir, Ricardo C. L. F. Oliveira, Leonardo Acho	Robust stability of stochastic systems with varying delays: Application to RLC circuit with intermittent closed-loop.	Appl. Math. Comput.	2021	DBLP DOI BibTeX RDF
19	Noemen Ammar, Gabzili Hanen	Investigation of a Heterogeneous RLC Lattice with Triangular Topology, Excited by a Lumped Voltage Source.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
19	Rafid Adnan Khan, Mohammad Muhtady Muhaisin, Gordon W. Roberts	Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
19	Mohamed M. Khader, José Francisco Gómez-Aguilar, Mohamed Adel	Numerical study for the fractional RL, RC, and RLC electrical circuits using Legendre pseudo-spectral method.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
19	Sunil Jadav, Shubham Tayal, Rajeevan Chandel, Munish Vashishath	High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
19	Tang Liu 0001, Baijun Wu, Wenzheng Xu, Xianbo Cao, Jian Peng 0002, Hongyi Wu	RLC: A Reinforcement Learning-Based Charging Algorithm for Mobile Devices.	ACM Trans. Sens. Networks	2021	DBLP DOI BibTeX RDF
19	Adriana Lipovac, Vlatko Lipovac, Borivoj Modlic	PHY, MAC, and RLC Layer Based Estimation of Optimal Cyclic Prefix Length.	Sensors	2021	DBLP DOI BibTeX RDF
19	Jessica S. Mendoza, Isabel de la Bandera, David Palacios, Raquel Barco	QoE Optimization in a Live Cellular Network through RLC Parameter Tuning.	Sensors	2021	DBLP DOI BibTeX RDF
19	Kristian Haska, Dusan Zorica, Stevan M. Cveticanin	Fractional RLC circuit in transient and steady state regimes.	Commun. Nonlinear Sci. Numer. Simul.	2021	DBLP DOI BibTeX RDF
19	Thomas Chaffey 0001, Rodolphe Sepulchre	Monotone RLC circuits.	ECC	2021	DBLP DOI BibTeX RDF
19	Krzysztof Oprzedkiewicz	A Discrete, Fractional Order, Memory-Effective State Space Model of a RLC Circuit.	AUTOMATION	2021	DBLP DOI BibTeX RDF
19	Yue Yu 0004, Behçet Açikmese	RLC Circuits-Based Distributed Mirror Descent Method.	IEEE Control. Syst. Lett.	2020	DBLP DOI BibTeX RDF
19	Lin Zhu, Danting Zhong, Bei Wang, Rongrui Lin, Min Xu	Understanding Subsynchronous Oscillation in DFIG-Based Wind Farms With Rotor-Side Converter Control Based on the Equivalent RLC Model.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Vincent Roca, Belkacem Teibi	Sliding Window Random Linear Code (RLC) Forward Erasure Correction (FEC) Schemes for FECFRAME.	RFC	2020	DBLP DOI BibTeX RDF
19	Jessica S. Mendoza, Isabel de la Bandera, David Palacios, Ana Herrera-García, Raquel Barco	On the Capability of QoE Improvement Based on the Adjustment of RLC Parameters.	Sensors	2020	DBLP DOI BibTeX RDF
19	Mohammad Saleh Tavazoei	Conditions on Polynomials Involved in Admittance Functions Passively Realizable by Using RLC and Two Fractional Elements.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
19	Satoshi Ichiki	RLC LOAD Vdc Idc SIM.		2020	DOI RDF
19	Khanidtha Thinthaworn, Winai Jaikla, Peerawut Suwanjan, Suchin Adhan, Nattapol Srichaiya, Adisorn Kwawsibsame, Fabian Khateb	A Compact Electronically Controllable Biquad Filter Synthesizing from Parallel Passive RLC Configuration.	SICE	2020	DBLP BibTeX RDF
19	Shivani Gupta, Vandana Gupta	Analytical modeling of RLC protocol of LTE using stochastic reward nets.	Int. J. Commun. Syst.	2019	DBLP DOI BibTeX RDF
19	Thomas Berger, Nicos Karcanias, Maria Livada	The Pseudo-McMillan Degree of Implicit Transfer Functions of RLC Networks.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF