Search results for "SIMD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
37	Asadollah Shahbahrami, Ben H. H. Juurlink	Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices.	APPT	2009	DBLP DOI BibTeX RDF
37	David Tarjan, Jiayuan Meng, Kevin Skadron	Increasing memory miss tolerance for SIMD cores.	SC	2009	DBLP DOI BibTeX RDF
37	Chunjiang J. Duanmu, M. Omair Ahmad, M. N. S. Swamy	Fast Block Motion Estimation With 8-Bit Partial Sums Using SIMD Architectures.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
37	Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.	ARCS	2007	DBLP DOI BibTeX RDF
37	Kevin Schaffer, Robert A. Walker 0001	A Prototype Multithreaded Associative SIMD Processor.	IPDPS	2007	DBLP DOI BibTeX RDF
37	Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft, Neil Hickey, David Stuttard	Revisiting SIMD Programming.	LCPC	2007	DBLP DOI BibTeX RDF
37	Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa	Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Guang-Huei Lin, Sao-Jie Chen, R. B. Lee, Yu Hen Hu	Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor.	APCCAS	2006	DBLP DOI BibTeX RDF
37	C. J. Duanmu	Accelearation of Full-Search Algorithm on SIMD Architectures by Using Eight-Bit Partial Sums of Four Luminance Values.	APCCAS	2006	DBLP DOI BibTeX RDF
37	C. J. Duanmu	A Fast Hexagon-Based Search Algorithm on SIMD Architectures.	APCCAS	2006	DBLP DOI BibTeX RDF
37	John G. Allen, Richard Y. D. Xu, Jesse S. Jin	Mean Shift Object Tracking for a SIMD Computer.	ICITA (1)	2005	DBLP DOI BibTeX RDF
37	Weihua Jiang, Chao Mei, Bo Huang 0002, Jianhui Li, Jiahua Zhu, Binyu Zang, Chuanqi Zhu	Boosting the Performance of Multimedia Applications Using SIMD Instructions.	CC	2005	DBLP DOI BibTeX RDF
37	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
37	Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki	Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
37	Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu	A two-way SIMD-based reconfigurable computing architecture for multimedia applications.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
37	Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat	Power Consumption of Performance-Scaled SIMD Processors.	PATMOS	2004	DBLP DOI BibTeX RDF
37	Liang Han, Jie Chen 0012, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li	An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing.	ICCD	2004	DBLP DOI BibTeX RDF
37	Stefan Kral, Franz Franchetti, Juergen Lorenz, Christoph W. Ueberhuber	SIMD Vectorization of Straight Line FFT Code.	Euro-Par	2003	DBLP DOI BibTeX RDF
37	Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh	Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches.	DSD	2002	DBLP DOI BibTeX RDF
37	Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado	-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation.	HiPC	2002	DBLP DOI BibTeX RDF
37	Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
37	Stefan Lund, Lars Bengtsson	Synchronizing a High-Speed SIMD Processor Array.	DSD	2001	DBLP DOI BibTeX RDF
37	Rainer Leupers	Code Selection for Media Processors with SIMD Instructions.	DATE	2000	DBLP DOI BibTeX RDF
37	Nael B. Abu-Ghazaleh, Philip A. Wilsey	Shared Control - Supporting Control Parallelism Using a SIMD-like Architecture.	Euro-Par	1998	DBLP DOI BibTeX RDF
37	P. J. Narayanan	Processor Autonomy on SIMD Architectures.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
37	Craig A. Farrell, Dorota H. Kieronska	Load Balanced Optimisation of Virtualised Algorithms for Implementation on Massively Parallel SIMD Architectures.	PARLE	1993	DBLP DOI BibTeX RDF
37	Jean-Luc Levaire	Using the Centaur System to for Data-Parallel SIMD Programming: A Case Study.	ESOP	1992	DBLP DOI BibTeX RDF
37	Reinhard von Hanxleden, Ken Kennedy	Relaxing SIMD Control Flow Constraints using Loop Transformations.	PLDI	1992	DBLP DOI BibTeX RDF	FORTRAN
37	Guido K. Jouret	Compiling functional languages for SIMD architectures.	SPDP	1991	DBLP DOI BibTeX RDF
37	Curt Powley, Chris Ferguson, Richard E. Korf	Parallel tree search on a SIMD machine.	SPDP	1991	DBLP DOI BibTeX RDF
37	Laxmi N. Bhuyan, Dharma P. Agrawal	Applications of SIMD computers in signal processing.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
37	Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chaitali Chakrabarti, Scott A. Mahlke, Trevor N. Mudge	Diet SODA: a power-efficient processor for digital cameras.	ISLPED	2010	DBLP DOI BibTeX RDF	digital still cameras, near-threshold, dynamic voltage scaling, SIMD
37	Jiayuan Meng, David Tarjan, Kevin Skadron	Dynamic warp subdivision for integrated branch and memory divergence tolerance.	ISCA	2010	DBLP DOI BibTeX RDF	branch divergence, memory divergence, cache, warp, latency hiding, simd
37	Karthik Ramani, Christiaan P. Gribble, Al Davis	StreamRay: a stream filtering architecture for coherent ray tracing.	ASPLOS	2009	DBLP DOI BibTeX RDF	wide simd architectures, ray tracing, graphics processors, interactive rendering
37	Patricio Bulic, Veselko Gustin	An efficient way to filter out data dependences with a sufficiently large distance between memory references.	ACM SIGPLAN Notices	2005	DBLP DOI BibTeX RDF	SIMD microprocessors, vectorizing compilers, data dependence analysis
37	Dorit Naishlos, Marina Biberstein, Shay Ben-David, Ayal Zaks	Vectorizing for a SIMdD DSP architecture.	CASES	2003	DBLP DOI BibTeX RDF	compiler controlled cache, rotating register file, SIMD, vectorization, data reuse, subword parallelism, viterbi
37	Deependra Talla, Lizy Kurian John	MediaBreeze: a decoupled architecture for accelerating multimedia applications.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	access and execute mechanisms, multimedia, prefetching, SIMD, hardware accelerators, decoupling, microprocessor design, general-purpose processors
37	Robert Allen, Luigi Cinque, Steven L. Tanimoto, Linda G. Shapiro, Dean Yasuda	A Parallel Algorithm for Graph Matching and Its MasPar Implementation.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	MasPar, combinatorial explosion, forward checking, parallel algorithm, load balancing, search, Graph, matching, branch-and-bound, SIMD
34	Kouichi Nitta, Osamu Matoba	A Scheme for SIMD Processing in Two Dimensional Binary Images and Its Applications.	OSC	2009	DBLP DOI BibTeX RDF	SIMD pattern processing, 2D binary image, huge scale information processing, image compression
34	Wonchul Lee, Hyojin Choi, Wonyong Sung	Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	variable block size motion estimation, H.264/AVC encoder, VLIW (very long instruction word), SIMD (single instruction multiple data)
34	Amr M. Bayoumi, Yasser Y. Hanafy	Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures.	IFMT	2008	DBLP DOI BibTeX RDF	BSIM, parallel computing, graphics processing units, GPGPU, SIMD, SPICE, manycore
34	Radoslaw Mantiuk, Dawid Pajak	Acceleration of High Dynamic Range Imaging Pipeline Based on Multi-threading and SIMD Technologies.	ICCS (1)	2008	DBLP DOI BibTeX RDF	multi-threading architecture, computer visualization, image processing, high dynamic range imaging, SIMD architecture, SSE
34	Robert D. Cameron	A case study in SIMD text processing with parallel bit streams: UTF-8 to UTF-16 transcoding.	PPoPP	2008	DBLP DOI BibTeX RDF	UTF-16, UTF-8, parallel bit streams, simd text processing, transcoding
34	Gang Ren 0002, Peng Wu 0001, David A. Padua	Optimizing data permutations for SIMD devices.	PLDI	2006	DBLP DOI BibTeX RDF	SIMD compilation, data permutation, optimization
34	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform.	ASAP	2005	DBLP DOI BibTeX RDF	SIMD extensions, Discrete Wavelet Transform, lifting scheme
34	Jong Won Park	Multiaccess Memory System for Attached SIMD Computer.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	prime memory system, multiaccess memory system, conflict-free memory system, routing circuit, SIMD computer, address calculation
34	Alexandre E. Eichenberger, Peng Wu 0001, Kevin O'Brien	Vectorization for SIMD architectures with alignment constraints.	PLDI	2004	DBLP DOI BibTeX RDF	simdization, compiler, SIMD, vectorization, alignment, multimedia extensions
34	Carlos García 0001, Roberto Lario, Manuel Prieto 0001, Luis Piñuel, Francisco Tirado	Vectorization of Multigrid Codes Using SIMD ISA Extensions.	IPDPS	2003	DBLP DOI BibTeX RDF	SIMD exploitation, Robust Multigrid, Cache-efficient multigrid, Multigrid methods
34	Ariel Ortiz	Teaching the SIMD execution model: : assembling a few parallel programming skills.	SIGCSE	2003	DBLP DOI BibTeX RDF	parallel computing, computer architecture, SIMD, assembly language, x86
34	Akihito Takahashi, Mostafa I. Soliman, Stanislav Sedukhin	Parallel LU-decomposition on Pentium Streaming SIMD Extensions.	ISHPC	2003	DBLP DOI BibTeX RDF	streaming SIMD, performance evaluation, parallel processing, data reusing, Gaussian elimination
34	Markus Lorenz, Lars Wehmeyer, Thorsten Dräger	Energy aware compilation for DSPs with SIMD instructions.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	zero overhead hardware loop, DSP, vectorization, energy minimization, SIMD instruction
34	Franz Franchetti, Markus Püschel	A SIMD Vectorizing Compiler for Digital Signal Processing Algorithms.	IPDPS	2002	DBLP DOI BibTeX RDF	code generation, FFT, discrete cosine transform, discrete Fourier transform, SIMD, SPIRAL, SSE, vector code
34	Sek M. Chai, Antonio Gentile, D. Scott Wills	Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor.	ARVLSI	1999	DBLP DOI BibTeX RDF	billion-transistor, image processing, technology, SIMD, system modeling, parallel computer architecture, Power density, focal plane
34	Amit Sengupta, Cauligi S. Raghavendra	All-To-All Broadcast and Matrix Multiplication in Faulty SIMD Hypercubes.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	SIMD hypercube, global sum, fault tolerance, broadcast, matrix multiplication, all-to-all broadcast, dimension ordering
34	Gene Saghi, Howard Jay Siegel	Compiler techniques for increasing CU/PE overlap in SIMD machines.	IPPS	1995	DBLP DOI BibTeX RDF	CU/PE overlap, control unit, single program, loop index variable manipulation, automatic specification, ELP compiler, load balancing, parallel processing, program compilers, processing elements, SIMD machines, compiler techniques
34	Michael Bolotski, Thomas Simon, Carlin Vieri, Rajeevan Amirtharajah, Thomas F. Knight Jr.	Abacus: a 1024 processor 8 ns SIMD array.	ARVLSI	1995	DBLP DOI BibTeX RDF	bit-slice computers, Abacus, SIMD array, reconfigurable bit-parallel array, system-level design issues, real-time early vision processing, bit-slice processing element, 8 ns, real-time systems, computer vision, VLSI, parallel architectures, reconfigurable architectures, microarchitecture, VLSI implementation, communication primitives
34	Montse Peiron, Mateo Valero, Eduard Ayguadé	Synchronized access to streams in SIMD vector multiprocessors.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF	SIMD vector multiprocessors, multi-module memories, vectors with constant stride, interconnection networks, conflict-free access
34	S. Ivanets, N. Ilinsky, M. Krylov	WAM Specification for Parallel Execution on SIMD Computer.	RCLP	1991	DBLP DOI BibTeX RDF	parallel unification, Warren Abstract Machine, compiler, Prolog, hypercube, SIMD-computer
34	Viktor K. Prasanna, Venkatesh Krishnan	Efficient Parallel Algorithms for Image Template Matching on Hypercube SIMD Machines.	IEEE Trans. Pattern Anal. Mach. Intell.	1989	DBLP DOI BibTeX RDF	image template matching, hypercube SIMD machines, parallel algorithms, parallel algorithms, computational complexity, computerised picture processing, computerised picture processing, computerised pattern recognition, computerised pattern recognition, time complexities, bounds
32	Liu Peng, Richard Seymour, Ken-ichi Nomura, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta, Alexander Loddoch, Michael Netzband, William R. Volz, Chap C. Wong	High-order stencil computations on multicore clusters.	IPDPS	2009	DBLP DOI BibTeX RDF
32	Jared Hoberock, Victor Lu, Yuntao Jia, John C. Hart	Stream compaction for deferred shading.	High Performance Graphics	2009	DBLP DOI BibTeX RDF
32	Daniele Paolo Scarpazza, Gregory F. Russell	High-performance regular expression scanning on the Cell/B.E. processor.	ICS	2009	DBLP DOI BibTeX RDF	multi-core, regular expressions, cell processor
32	Meilian Xu, Parimala Thulasiraman	Finite-difference time-domain on the cell/B.E. processor.	IPDPS	2008	DBLP DOI BibTeX RDF
32	Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez	Analysis of video filtering on the cell processor.	ISCAS	2008	DBLP DOI BibTeX RDF
32	Xiaofang Wang, Sotirios G. Ziavras	Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.	ISQED	2007	DBLP DOI BibTeX RDF
32	Luigi Di Stefano, Stefano Mattoccia, Federico Tombari	Speeding-up NCC-Based Template Matching Using Parallel Multimedia Instructions.	CAMP	2005	DBLP DOI BibTeX RDF
32	Peng Wu 0001, Alexandre E. Eichenberger, Amy Wang, Peng Zhao	An integrated simdization framework using virtual vectors.	ICS	2005	DBLP DOI BibTeX RDF
32	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Implementing and Evaluating Color-Aware Instruction Set for Low-Memory, Embedded Video Processing in Data Parallel Architectures.	EUC	2005	DBLP DOI BibTeX RDF
32	Esther Salamí, Mateo Valero	A Vector-µSIMD-VLIW Architecture for Multimedia Applications.	ICPP	2005	DBLP DOI BibTeX RDF
32	Hong Wang 0007, Lei Xie, Meiduo Wu, Robert A. Walker 0001	A Scalable Associative Processor with Applications in Database and Image Processing.	IPDPS	2004	DBLP DOI BibTeX RDF
32	Leo Chin Sim, Heiko Schröder 0001, Graham Leedham	Hybrid System, A New Low Cost Parallel Cluster.	HPCS	2002	DBLP DOI BibTeX RDF
32	Patrick Lincoln, José Meseguer 0001, Livio Ricciulli	The Rewrite Rule Machine Node Architecture and Its Performance.	CONPAR	1994	DBLP DOI BibTeX RDF
29	Hoseok Chang, Wonyong Sung	Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
29	Chengkun Wu, Jianping Yin, Zhiping Cai, En Zhu, Jieren Cheng	A Hybrid Parallel Signature Matching Model for Network Security Applications Using SIMD GPU.	APPT	2009	DBLP DOI BibTeX RDF	network security, GPU, parallel model, signature matching
29	Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit, Rui Dai	IRIS: A Firmware Design Methodology for SIMD Architectures.	DSD	2008	DBLP DOI BibTeX RDF
29	Mark Woh, Yuan Lin 0002, Sangwon Seo, Trevor N. Mudge, Scott A. Mahlke	Analyzing the scalability of SIMD for the next generation software defined radio.	ICASSP	2008	DBLP DOI BibTeX RDF
29	Ghulam Lashari, Ondrej Lhoták, Michael McCool	Control Flow Emulation on Tiled SIMD Architectures.	CC	2008	DBLP DOI BibTeX RDF
29	Kevin Schaffer, Robert A. Walker 0001	Using hardware multithreading to overcome broadcast/reduction latency in an associative SIMD processor.	IPDPS	2008	DBLP DOI BibTeX RDF
29	Yifan He, Zoran Zivkovic, Richard P. Kleihorst, Alexander Danilin, Henk Corporaal, Bart Mesman	Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration.	ACIVS	2008	DBLP DOI BibTeX RDF
29	I. K. Hong, S. T. Chung, H. K. Kim, Y. B. Kim, Y. D. Son, Zang Hee Cho	Ultra Fast Symmetry and SIMD-Based Projection-Backprojection (SSP) Algorithm for 3-D PET Image Reconstruction.	IEEE Trans. Medical Imaging	2007	DBLP DOI BibTeX RDF
29	Christopher Kumar Anand, Wolfram Kahl	Code Graph Transformations for Verifiable Generation of SIMD-Parallel Assembly Code.	AGTIVE	2007	DBLP DOI BibTeX RDF
29	Nicolas Fritz, Philipp Lucas 0001, Reinhard Wilhelm	Exploiting SIMD Parallelism with the CGiSCompiler Framework.	LCPC	2007	DBLP DOI BibTeX RDF
29	Arpith C. Jacob, Marcin Paprzycki, Maria Ganzha, Sugata Sanyal	Applying SIMD Approach to Whole Genome Comparison on Commodity Hardware.	PPAM	2007	DBLP DOI BibTeX RDF
29	Mohammed Sayed, Wael M. Badawy	An affine-based algorithm and SIMD architecture for video compression with low bit-rate applications.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
29	Stephen Warrington, Hassan Shojania, Subramania Sudharsanan, Wai-Yip Chan	Performance improvement of the H.264/AVC deblocking filter using SIMD instructions.	ISCAS	2006	DBLP DOI BibTeX RDF
29	Junho Cho, Hoseok Chang, Wonyong Sung	An FPGA based SIMD processor with a vector memory unit.	ISCAS	2006	DBLP DOI BibTeX RDF
29	Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten	Dynamic-SIMD for lens distortion compensation.	ASAP	2006	DBLP DOI BibTeX RDF
29	Hossein Ahmadi 0001, Maryam Moslemi Naeini, Hamid Sarbazi-Azad	Efficient SIMD Numerical Interpolation.	HPCC	2005	DBLP DOI BibTeX RDF
29	Dong-Sun Kim 0002, Hyunsik Kim, Hong-Sik Kim, Gunhee Han, Duck-Jin Chung	A SIMD Neural Network Processor for Image Processing.	ISNN (2)	2005	DBLP DOI BibTeX RDF
29	M. Moslemi, Hossein Ahmadi 0001, Hamid Sarbazi-Azad	Efficient Polynomial Root Finding Using SIMD Extensions.	ICPADS (2)	2005	DBLP DOI BibTeX RDF
29	Xizhen Xu, Sotirios G. Ziavras	H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication.	ICCD	2005	DBLP DOI BibTeX RDF
29	Daisuke Takahashi, Taisuke Boku, Mitsuhisa Sato	An Implementation of Parallel 3-D FFT Using Short Vector SIMD Instructions on Clusters of PCs.	PARA	2004	DBLP DOI BibTeX RDF
29	Dietmar Fey, Lutz Hoppe, Andreas Loos	Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips.	PARELEC	2004	DBLP DOI BibTeX RDF
29	Sandeep Koranne	A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine Platform.	ISQED	2004	DBLP DOI BibTeX RDF
29	Maurício Breternitz Jr., Herbert H. J. Hum, Sanjeev Kumar	Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU.	IEEE PACT	2003	DBLP DOI BibTeX RDF
29	Gregorio Bernabé, José M. García 0001, José González 0002	Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions.	PDP	2003	DBLP DOI BibTeX RDF
29	Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai	A Code Selection Method for SIMD Processors with PACK Instructions.	SCOPES	2003	DBLP DOI BibTeX RDF
29	Jonathan Mangnall, Steven F. Quigley	System Level Simulation of a SIMD Active Memory Enhanced PC (Or, Why We Don't Want 100% Bandwidth Utilisation.	IPDPS	2003	DBLP DOI BibTeX RDF
29	Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado	Vectorization of the 2D Wavelet Lifting Transform Using SIMD Extensions.	IPDPS	2003	DBLP DOI BibTeX RDF
29	Alexander Paar, Manuel L. Anido, Nader Bagherzadeh	A Novel Predication Scheme for a SIMD System-on-Chip.	Euro-Par	2002	DBLP DOI BibTeX RDF