Search results for "VCO"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Sankaran Aniruddhan, Min Chu, David J. Allstot	A lateral-BJT-biased CMOS voltage-controlled oscillator.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
34	Hyuk-Jun Sung, Kwang Sub Yoon	A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
27	Xin Xin 0005, Chang Zhang, Xingyuan Tong	An 11-bit Nyquist SAR-VCO Hybrid ADC with a Reused Ring-VCO for Power Reduction.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
27	Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi	A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
27	N. R. Sivaraaj, K. K. Abdul Majeed	A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends.	IEEE Access	2023	DBLP DOI BibTeX RDF
27	Shea Smith, Armin Tajalli, Shiuh-Hua Wood Chiang	A VCO Linearization Technique Using Dual-VCO and Interpolation for Time-Based ADCs.	MWSCAS	2023	DBLP DOI BibTeX RDF
27	Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn	A 0.024mm² 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM).	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
27	Yuekang Guo, Jing Jin 0005, Xiaoming Liu 0008, Zhaolin Yang, Jianjun Zhou	A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$.	ISCAS	2023	DBLP DOI BibTeX RDF
27	David Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez	VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC.	PATMOS	2018	DBLP DOI BibTeX RDF
27	Qiong Zou, Kaixue Ma, Kiat Seng Yeo	A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
27	Takahiro Nakamura, Tomomitsu Kitamura, Nobuhiro Shiramizu, Toru Masuda	A Wide-Tuning-Range VCO with Small VCO-Gain Variation for Multi-Band W-CDMA RFIC.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
27	Zhentao Xu, X. L. Zhang, J. Z. Chen, Shaogang Hu, Qi Yu 0002, Yang Liu 0062, Wei Meng Lim	Vco-Based continuous-Time Sigma Delta ADC Based on a Dual-VCO-quantizer-Loop Structure.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
27	Waleed El-Halwagy, Mohamed Dessouky, Hassan El-Ghitani	A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization.	ICECS	2013	DBLP DOI BibTeX RDF
27	Yun Du, Tao He, Yang Jiang 0002, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW.	ISCAS	2013	DBLP DOI BibTeX RDF
27	Ching-Ian Shie, Yi-Chyun Chiang, Jinq-Min Lin	Low Power and High Efficiency VCO and Quadrature VCO Circuits Constructed with Transconductance-Enhanced Colpitts Oscillator Feature.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
25	Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee	Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	wafer probe test, test yield, loopback test, DFT, RF test, low-cost test
25	Burak Çatli, Mona Mostafa Hella	A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications.	ISCAS	2008	DBLP DOI BibTeX RDF
25	Li Ke 0002, Reuben Wilcock, Peter R. Wilson	Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range.	ISCAS	2008	DBLP DOI BibTeX RDF
25	Basab Datta, Wayne P. Burleson	Temperature measurement in Content Addressable Memory cells using bias-controlled VCO.	SoCC	2008	DBLP DOI BibTeX RDF
25	Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury	A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels.	ASP-DAC	2006	DBLP DOI BibTeX RDF
25	Young-Jae Lee, Hyun-Kyu Yu	A transformer-based low phase noise and widely tuned CMOS quadrature VCO.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Chih-Wei Yao, Alan N. Willson Jr.	Energy circulation quadrature LC-VCO.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Peter H. R. Popplewell, Victor Karam, Atef Shamim, John W. M. Rogers, Mark Cloutier, Calvin Plett	5.2 GHz self-powered lock and roll radio using VCO injection-locking and on-chip antennas.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Chia-Chieh Tu, Ching-Yuan Yang	A 6.5-GHz LC VCO with Integrated-Transformer Tuning.	APCCAS	2006	DBLP DOI BibTeX RDF
25	Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury	Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y. Wong	NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO.	ASP-DAC	2004	DBLP DOI BibTeX RDF
25	Sule Ozev, Christian Olgaard	Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures.	VTS	2004	DBLP DOI BibTeX RDF
25	Pietro Andreani	A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
25	Pietro Andreani, Sven Mattisson	A 2.4-GHz CMOS monolithic VCO based on an MOS varactor.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
25	Ravindranath Naiknaware, Terri S. Fiez	Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
23	Kalyan Bhattacharyya	23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently.	VLSI Design	2010	DBLP DOI BibTeX RDF	Distributed oscillator, CMOS RF IC, Monolithic Microwave Integrated Circuits, VCO
23	Xiaolue Lai, Jaijeet S. Roychowdhury	A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators.	DAC	2006	DBLP DOI BibTeX RDF	DCO, PPV, simulation, PLL, macromodel, VCO, DPLL
23	Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay	A comparative study of MOS VCOs for low voltage high performance operation.	ISLPED	2004	DBLP DOI BibTeX RDF	FOM, low power, low voltage, VCO, phase noise, RF design
23	Domine Leenaerts	Low power RF IC design for wireless communication.	ISLPED	2003	DBLP DOI BibTeX RDF	low power, wireless communication, technology, PLL, RF, VCO, transceivers, LNA
23	B. S. Sreeja, S. Radha	Design and implementation of MEMS based differential voltage controlled oscillator.	EIT	2009	DBLP DOI BibTeX RDF
23	Yang Liu, Ashok Kumar Srivastava, Yao Xu	A switchable PLL frequency synthesizer and hot carrier effects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise
23	Leburu Manojkumar, Arun Mohan 0003, Nagendra Krishnapura	A Comparison of Approaches to Carrier Generation for Zigbee Transceivers.	VLSI Design	2009	DBLP DOI BibTeX RDF
23	Christopher I. Byrnes	CSS bode lecture: "Analysis and design of steady-state behavior for nonlinear feedback systems".	CDC	2008	DBLP DOI BibTeX RDF
23	Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng	A 24GHz low-power CMOS receiver design.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Jagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva	Quadrature generation techniques for frequency multiplication based oscillators.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Régis Roubadia, Sami Ajram, Guy Cathébras	Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio	A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Masoud Roham, Pedram Mohseni	A Wireless IC for Wide-Range Neurochemical Monitoring Using Amperometry and Fast-Scan Cyclic Voltammetry.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Shuilong Huang, Zhihua Wang	A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto	A new test and characterization scheme for 10+ GHz low jitter wide band PLL.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Xiaolue Lai, Jaijeet S. Roychowdhury	TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation.	ICCAD	2006	DBLP DOI BibTeX RDF
23	Saeed Saeedi, Saeid Mehrmanesh, Armin Tajalli, Seyed Mojtaba Atarodi	A technique to suppress tail current flicker noise in CMOS LC VCOs.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar	Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.	DAC	2006	DBLP DOI BibTeX RDF	pareto surfaces, performance space, optimization, yield
23	Young Uk Yim, John F. McDonald 0001, Russell P. Kraft	12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes.	ISVLSI	2005	DBLP DOI BibTeX RDF
23	Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.	DATE	2005	DBLP DOI BibTeX RDF
23	Zhangwen Tang, Jie He 0003, Hongyan Jian, Haiqing Zhang, Jie Zhang, Hao Min	Prediction of LC-VCOs' tuning curves with period calculation technique.	ASP-DAC	2005	DBLP DOI BibTeX RDF
23	Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg	A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
23	Ellie Cijvat, Niklas Troedsson, Henrik Sjöland	A 2.4 GHz CMOS power amplifier using internal frequency doubling.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
23	Chien-Hung Kuo, Yi-Shun Shih	A frequency synthesizer using two different delay feedbacks.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
23	Meng-Lieh Sheu, Ta-Wei Lin, Wei-Hung Hsu	Wide frequency range voltage controlled ring oscillators based on transmission gates.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
23	Jaehong Ko, Wookwan Lee, Soo-Won Kim	2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	jitter, PLL, output buffer, charge-pump
23	Manas Behera, Volodymyr Kratyuk, Yutao Hu, Kartikeya Mayaram	Accurate simulation of phase noise in RF MEMS VCOs.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
23	Dean A. Badillo, Sayfe Kiaei	A novel low phase noise 1.8V 900MHz CMOS voltage controlled ring oscillator.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
23	Chao Su, Sreenath Thoka, Kee-Chee Tiew, Randall L. Geiger	A 40 GHz modified-Colpitts voltage controlled oscillator with increased tuning range.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
23	Wen-Chi Wu, Chih-Chien Huang, Chih-Hsiung Chang, Nai-Heng Tseng	Low-power CMOS PLL for clock generator.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
23	Georg Konstanznig, Andreas Springer, Robert Weigel	A low power 4.3 GHz phase-locked loop with advanced dual-mode tuning technique including I/Q-signal generation in 0.12µm standard CMOS.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
23	Carl De Ranter, Michiel Steyaert	Design techniques for low power high bandwidth upconversion in CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	upconversion, low power, CMOS, analog, oscillators, RF design
23	Hong-Sing Kao, Chung-Yu Wu	An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
23	Robin R.-B. Sheen, Oscal T.-C. Chen	A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
23	Ahmed Fakhfakh, N. Milet-Lewis, Yann Deval, Hervé Levi	Study and behavioural simulation of phase noise and jitter in oscillators.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
23	Jin-Ku Kang, Dong-Hee Kim	A CMOS clock and data recovery with two-XOR phase-frequency detector circuit.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
23	Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee	A wideband digital frequency synthesizer.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
23	Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung	A low-power high driving ability voltage control oscillator used in PLL.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
23	Rafael J. Betancourt-Zamora, Thomas H. Lee	CMOS VCOs for frequency synthesis in wireless biotelemetry.	ISLPED	1998	DBLP DOI BibTeX RDF
22	Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen	1-V 7-mW dual-band fast-locked frequency synthesizer.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	HiperLAN, WLAN, low-power design, phase-locked loops (PLLs), voltage-controlled oscillator (VCO), phase noise, frequency synthesizer
22	Maneesha Dalmia, André Ivanov, Sassan Tabatabaei	Power supply current monitoring techniques for testing PLLs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	power supply current monitoring, PLL testing, digital IC, VCO testing, analogue circuit testing, fault detection, phase locked loops, phase-locked loops, current testing, nonlinear circuits, mixed-signal ICs
14	Ziyi Lin, Haikun Jia, Ruichang Ma, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi	A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
14	Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn	An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
14	Heyi Li, Kaixuan Du, Yuanxin Bao, Yanchi Dong, Jiayoon Ru, Han Xiao 0006, Hao Zhang, Zhixuan Wang, Yi Zhong, Linxiao Shen, Le Ye, Ru Huang	A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
14	Mahsa Zareie, Kamal El-Sankary, Ezz I. El-Masry, Ximing Fu	An Open-Loop VCO-ADC Based on a Linearized Current Control Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
14	Behnam Moradi, Xuyang Liu, Hamidreza Aghasi	A 76-82 GHz VCO in 65 nm CMOS With 189.3 dBc/Hz PN FOM and -0.6 dBm Harmonic Power for mm-Wave FMCW Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
14	Kyung-Chan An, Neelakantan Narasimman, Tony Tae-Hyoung Kim	A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
14	Yubing Li, Tao Tan, Xiuping Li	A 40.6% Tuning Range Low-Phase-Noise Class-F-1/3 VCO Using Simultaneous Frequency and Harmonic-Mode Switching.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
14	Razieh Ghasemi, Mohammad Azim Karami	A low phase noise quadrature VCO using super-harmonic coupling technique in 65-nm CMOS technology.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
14	Shuenn-Yuh Lee, Yi-Ting Hsieh, Hao-Yun Lee, Shih-Shuo Chang, Ju-Yi Chen	A Direct Current-Sensing VCO-Based 2nd-Order Continuous-Time Sigma-Delta Modulator for Biosensor Readout Applications.	IEEE Trans. Biomed. Circuits Syst.	2024	DBLP DOI BibTeX RDF
14	Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang	A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
14	Yuetong Lyu, Changwenquan Song, Pei Qin, Liang Wu	A 11.3-16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2024	DBLP DOI BibTeX RDF
14	Tailize C. De-Oliveira, Tawan Chrysther dos Santos, Renan D. P. de Oliveira, Claudio E. C. P. Júnior, Rodrigo S. Moraes, Diego M. de Mattos, Martina C. Rodrigues, Alessandro Gonçalves Girardi, Paulo César Comassetto de Aguirre, Lucas Compassi Severo	A 5.8-GHz RF VCO-Based Sensing System with Integrated RF Energy Harvesting in CMOS 65-nm for Health Monitoring Applications.	LASCAS	2024	DBLP DOI BibTeX RDF
14	Raphael R. N. Souza, Agord M. Pinto, Roberto L. de Orio, Leandro Tiago Manera, Eduardo R. de Lima	A 2.0 GHz LC- VCO with 1.4 GHz Tuning Range and Switched Varactor Array.	LASCAS	2024	DBLP DOI BibTeX RDF
14	Nazmus Saquib, Ahmed Elmenshawi, Mona Mostafa Hella	A 100 GHz Varactor-less Fundamental VCO With 12% Tuning Range in 22nm FDSOI Technology.	RWS	2024	DBLP DOI BibTeX RDF
14	Huanyu Ge, Haikun Jia, Wei Deng 0001, Ruichang Ma, Zhihua Wang 0001, Baoyong Chi	19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique.	ISSCC	2024	DBLP DOI BibTeX RDF
14	Haijun Shao, Rui Paulo Martins, Pui-In Mak	23.4 A 167 μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO.	ISSCC	2024	DBLP DOI BibTeX RDF
14	Haoran Li, Tailong Xu, Xi Meng, Jun Yin 0001, Rui Paulo Martins, Pui-In Mak	10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment.	ISSCC	2024	DBLP DOI BibTeX RDF
14	Haikun Jia, Pingda Guan, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi	A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
14	Chao Li, Jinhua Guo, Pei Qin, Quan Xue	A Wideband Mode-Switching Quad-Core VCO Using Compact Multi-Mode Magnetically Coupled LC Network.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
14	Yaqian Sun, Wei Deng 0001, Haikun Jia, Yejun He, Zhihua Wang 0001, Baoyong Chi	A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
14	Yizhuo Wang, Jiahe Shi, Hao Xu 0005, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao 0001, Hao Min, Na Yan	Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
14	Hee Sung Lee, Tae Hwan Jang, Joon Hyung Kim, Chul Soon Park	Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With gm-Boosting Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
14	Shruti Konwar, Bibhu Datta Sahoo 0002	Johnson Counter-Based Multiphase Generation for VCO-Based ADC for Direct Digitization of Low Amplitude Sensor Signals.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
14	Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski	Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
14	Mahin Esmaeilzadeh, Yves Audet, Mohamed Ali 0001, Mohamad Sawan	A Low-Offset VCO-Based Time-Domain Comparator Using a Phase Frequency Detector With Reduced Dead and Blind Zones.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
14	Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu	A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
14	Xi Meng, Haoran Li, Peng Chen 0022, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins	Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
14	Huaiyu Liu, Yang Lin, Liang Qi, Yongwei Lou, Guoxing Wang, Yan Liu 0016	Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
14	Jonas Borgmans, Pieter Rombouts	The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF