Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | Sankaran Aniruddhan, Min Chu, David J. Allstot |
A lateral-BJT-biased CMOS voltage-controlled oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 976-979, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Hyuk-Jun Sung, Kwang Sub Yoon |
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 553-556, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Xin Xin 0005, Chang Zhang, Xingyuan Tong |
An 11-bit Nyquist SAR-VCO Hybrid ADC with a Reused Ring-VCO for Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 43(3), pp. 1339-1365, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
27 | Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi |
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(12), pp. 3338-3350, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
27 | N. R. Sivaraaj, K. K. Abdul Majeed |
A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 127987-128017, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
27 | Shea Smith, Armin Tajalli, Shiuh-Hua Wood Chiang |
A VCO Linearization Technique Using Dual-VCO and Interpolation for Time-Based ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 996-1000, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
27 | Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn |
A 0.024mm² 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
27 | Yuekang Guo, Jing Jin 0005, Xiaoming Liu 0008, Zhaolin Yang, Jianjun Zhou |
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
27 | David Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez |
VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018, pp. 19-22, 2018, IEEE, 978-1-5386-6365-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
27 | Qiong Zou, Kaixue Ma, Kiat Seng Yeo |
A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2), pp. 554-563, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
27 | Takahiro Nakamura, Tomomitsu Kitamura, Nobuhiro Shiramizu, Toru Masuda |
A Wide-Tuning-Range VCO with Small VCO-Gain Variation for Multi-Band W-CDMA RFIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 96-C(6), pp. 790-795, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Zhentao Xu, X. L. Zhang, J. Z. Chen, Shaogang Hu, Qi Yu 0002, Yang Liu 0062, Wei Meng Lim |
Vco-Based continuous-Time Sigma Delta ADC Based on a Dual-VCO-quantizer-Loop Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(9), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Waleed El-Halwagy, Mohamed Dessouky, Hassan El-Ghitani |
A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, UAE, December 8-11, 2013, pp. 157-160, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Yun Du, Tao He, Yang Jiang 0002, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins |
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, pp. 373-376, 2013, IEEE, 978-1-4673-5760-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Ching-Ian Shie, Yi-Chyun Chiang, Jinq-Min Lin |
Low Power and High Efficiency VCO and Quadrature VCO Circuits Constructed with Transconductance-Enhanced Colpitts Oscillator Feature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 91-C(2), pp. 193-199, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee |
Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 150-159, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
wafer probe test, test yield, loopback test, DFT, RF test, low-cost test |
25 | Burak Çatli, Mona Mostafa Hella |
A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 996-999, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Li Ke 0002, Reuben Wilcock, Peter R. Wilson |
Improved 6.7GHz CMOS VCO delay cell with up to seven octave tuning range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 444-447, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Basab Datta, Wayne P. Burleson |
Temperature measurement in Content Addressable Memory cells using bias-controlled VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 147-150, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury |
A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 291-296, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Young-Jae Lee, Hyun-Kyu Yu |
A transformer-based low phase noise and widely tuned CMOS quadrature VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Chih-Wei Yao, Alan N. Willson Jr. |
Energy circulation quadrature LC-VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Peter H. R. Popplewell, Victor Karam, Atef Shamim, John W. M. Rogers, Mark Cloutier, Calvin Plett |
5.2 GHz self-powered lock and roll radio using VCO injection-locking and on-chip antennas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Chia-Chieh Tu, Ching-Yuan Yang |
A 6.5-GHz LC VCO with Integrated-Transformer Tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 510-513, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury |
Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 459-464, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y. Wong |
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 169-174, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Sule Ozev, Christian Olgaard |
Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 217-222, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Pietro Andreani |
A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 714-717, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Pietro Andreani, Sven Mattisson |
A 2.4-GHz CMOS monolithic VCO based on an MOS varactor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 557-560, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Ravindranath Naiknaware, Terri S. Fiez |
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 33-36, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Kalyan Bhattacharyya |
23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 182-187, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Distributed oscillator, CMOS RF IC, Monolithic Microwave Integrated Circuits, VCO |
23 | Xiaolue Lai, Jaijeet S. Roychowdhury |
A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1017-1022, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
DCO, PPV, simulation, PLL, macromodel, VCO, DPLL |
23 | Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay |
A comparative study of MOS VCOs for low voltage high performance operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 244-247, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FOM, low power, low voltage, VCO, phase noise, RF design |
23 | Domine Leenaerts |
Low power RF IC design for wireless communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 428-433, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low power, wireless communication, technology, PLL, RF, VCO, transceivers, LNA |
23 | B. S. Sreeja, S. Radha |
Design and implementation of MEMS based differential voltage controlled oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 202-206, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Yang Liu, Ashok Kumar Srivastava, Yao Xu |
A switchable PLL frequency synthesizer and hot carrier effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 481-486, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise |
23 | Leburu Manojkumar, Arun Mohan 0003, Nagendra Krishnapura |
A Comparison of Approaches to Carrier Generation for Zigbee Transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 367-372, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Christopher I. Byrnes |
CSS bode lecture: "Analysis and design of steady-state behavior for nonlinear feedback systems". ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: Proceedings of the 47th IEEE Conference on Decision and Control, CDC 2008, December 9-11, 2008, Cancún, Mexico, pp. 10-11, 2008, IEEE, 978-1-4244-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng |
A 24GHz low-power CMOS receiver design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 980-983, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Jagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva |
Quadrature generation techniques for frequency multiplication based oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 440-443, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Régis Roubadia, Sami Ajram, Guy Cathébras |
Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2490-2493, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio |
A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 429-432, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Masoud Roham, Pedram Mohseni |
A Wireless IC for Wide-Range Neurochemical Monitoring Using Amperometry and Fast-Scan Cyclic Voltammetry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3131-3134, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Shuilong Huang, Zhihua Wang |
A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3924-3927, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto |
A new test and characterization scheme for 10+ GHz low jitter wide band PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 856-859, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Xiaolue Lai, Jaijeet S. Roychowdhury |
TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 269-274, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Saeed Saeedi, Saeid Mehrmanesh, Armin Tajalli, Seyed Mojtaba Atarodi |
A technique to suppress tail current flicker noise in CMOS LC VCOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar |
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 31-36, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pareto surfaces, performance space, optimization, yield |
23 | Young Uk Yim, John F. McDonald 0001, Russell P. Kraft |
12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 278-279, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay |
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 270-275, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Zhangwen Tang, Jie He 0003, Hongyan Jian, Haiqing Zhang, Jie Zhang, Hao Min |
Prediction of LC-VCOs' tuning curves with period calculation technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 687-690, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg |
A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5453-5456, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Ellie Cijvat, Niklas Troedsson, Henrik Sjöland |
A 2.4 GHz CMOS power amplifier using internal frequency doubling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2683-2686, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Chien-Hung Kuo, Yi-Shun Shih |
A frequency synthesizer using two different delay feedbacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2799-2802, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Meng-Lieh Sheu, Ta-Wei Lin, Wei-Hung Hsu |
Wide frequency range voltage controlled ring oscillators based on transmission gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2731-2734, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Jaehong Ko, Wookwan Lee, Soo-Won Kim |
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 122-125, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
jitter, PLL, output buffer, charge-pump |
23 | Manas Behera, Volodymyr Kratyuk, Yutao Hu, Kartikeya Mayaram |
Accurate simulation of phase noise in RF MEMS VCOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 677-680, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Dean A. Badillo, Sayfe Kiaei |
A novel low phase noise 1.8V 900MHz CMOS voltage controlled ring oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 160-163, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Chao Su, Sreenath Thoka, Kee-Chee Tiew, Randall L. Geiger |
A 40 GHz modified-Colpitts voltage controlled oscillator with increased tuning range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 717-720, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Wen-Chi Wu, Chih-Chien Huang, Chih-Hsiung Chang, Nai-Heng Tseng |
Low-power CMOS PLL for clock generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 633-636, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Georg Konstanznig, Andreas Springer, Robert Weigel |
A low power 4.3 GHz phase-locked loop with advanced dual-mode tuning technique including I/Q-signal generation in 0.12µm standard CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 288-291, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Carl De Ranter, Michiel Steyaert |
Design techniques for low power high bandwidth upconversion in CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 237-242, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
upconversion, low power, CMOS, analog, oscillators, RF design |
23 | Hong-Sing Kao, Chung-Yu Wu |
An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 5-8, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Robin R.-B. Sheen, Oscal T.-C. Chen |
A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 722-725, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Ahmed Fakhfakh, N. Milet-Lewis, Yann Deval, Hervé Levi |
Study and behavioural simulation of phase noise and jitter in oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 323-326, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Jin-Ku Kang, Dong-Hee Kim |
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 266-269, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee |
A wideband digital frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 710-713, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung |
A low-power high driving ability voltage control oscillator used in PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 614-617, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Rafael J. Betancourt-Zamora, Thomas H. Lee |
CMOS VCOs for frequency synthesis in wireless biotelemetry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 91-94, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen |
1-V 7-mW dual-band fast-locked frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 431-435, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
HiperLAN, WLAN, low-power design, phase-locked loops (PLLs), voltage-controlled oscillator (VCO), phase noise, frequency synthesizer |
22 | Maneesha Dalmia, André Ivanov, Sassan Tabatabaei |
Power supply current monitoring techniques for testing PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 366-371, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
power supply current monitoring, PLL testing, digital IC, VCO testing, analogue circuit testing, fault detection, phase locked loops, phase-locked loops, current testing, nonlinear circuits, mixed-signal ICs |
14 | Ziyi Lin, Haikun Jia, Ruichang Ma, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi |
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 253-267, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn |
An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(4), pp. 1171-1183, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Heyi Li, Kaixuan Du, Yuanxin Bao, Yanchi Dong, Jiayoon Ru, Han Xiao 0006, Hao Zhang, Zhixuan Wang, Yi Zhong, Linxiao Shen, Le Ye, Ru Huang |
A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(2), pp. 435-448, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Mahsa Zareie, Kamal El-Sankary, Ezz I. El-Masry, Ximing Fu |
An Open-Loop VCO-ADC Based on a Linearized Current Control Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 32(3), pp. 587-591, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Behnam Moradi, Xuyang Liu, Hamidreza Aghasi |
A 76-82 GHz VCO in 65 nm CMOS With 189.3 dBc/Hz PN FOM and -0.6 dBm Harmonic Power for mm-Wave FMCW Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(1), pp. 51-61, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Kyung-Chan An, Neelakantan Narasimman, Tony Tae-Hyoung Kim |
A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(4), pp. 1481-1494, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Yubing Li, Tao Tan, Xiuping Li |
A 40.6% Tuning Range Low-Phase-Noise Class-F-1/3 VCO Using Simultaneous Frequency and Harmonic-Mode Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(3), pp. 1037-1041, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Razieh Ghasemi, Mohammad Azim Karami |
A low phase noise quadrature VCO using super-harmonic coupling technique in 65-nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 52(1), pp. 97-110, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Shuenn-Yuh Lee, Yi-Ting Hsieh, Hao-Yun Lee, Shih-Shuo Chang, Ju-Yi Chen |
A Direct Current-Sensing VCO-Based 2nd-Order Continuous-Time Sigma-Delta Modulator for Biosensor Readout Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 18(2), pp. 288-298, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang |
A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 143, pp. 106061, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Yuetong Lyu, Changwenquan Song, Pei Qin, Liang Wu |
A 11.3-16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 14(1), pp. 133-141, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Tailize C. De-Oliveira, Tawan Chrysther dos Santos, Renan D. P. de Oliveira, Claudio E. C. P. Júnior, Rodrigo S. Moraes, Diego M. de Mattos, Martina C. Rodrigues, Alessandro Gonçalves Girardi, Paulo César Comassetto de Aguirre, Lucas Compassi Severo |
A 5.8-GHz RF VCO-Based Sensing System with Integrated RF Energy Harvesting in CMOS 65-nm for Health Monitoring Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 15th IEEE Latin America Symposium on Circuits and Systems, LASCAS 2024, Punta del Este, Uruguay, February 27 - March 1, 2024, pp. 1-5, 2024, IEEE, 979-8-3503-8122-1. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Raphael R. N. Souza, Agord M. Pinto, Roberto L. de Orio, Leandro Tiago Manera, Eduardo R. de Lima |
A 2.0 GHz LC- VCO with 1.4 GHz Tuning Range and Switched Varactor Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 15th IEEE Latin America Symposium on Circuits and Systems, LASCAS 2024, Punta del Este, Uruguay, February 27 - March 1, 2024, pp. 1-5, 2024, IEEE, 979-8-3503-8122-1. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Nazmus Saquib, Ahmed Elmenshawi, Mona Mostafa Hella |
A 100 GHz Varactor-less Fundamental VCO With 12% Tuning Range in 22nm FDSOI Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RWS ![In: IEEE Radio and Wireless Symposium, RWS 2024, San Antonio, TX, USA, January 21-24, 2024, pp. 99-101, 2024, IEEE, 979-8-3503-4045-7. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Huanyu Ge, Haikun Jia, Wei Deng 0001, Ruichang Ma, Zhihua Wang 0001, Baoyong Chi |
19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 356-358, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Haijun Shao, Rui Paulo Martins, Pui-In Mak |
23.4 A 167 μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 406-408, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Haoran Li, Tailong Xu, Xi Meng, Jun Yin 0001, Rui Paulo Martins, Pui-In Mak |
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 204-206, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Haikun Jia, Pingda Guan, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi |
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(2), pp. 371-385, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Chao Li, Jinhua Guo, Pei Qin, Quan Xue |
A Wideband Mode-Switching Quad-Core VCO Using Compact Multi-Mode Magnetically Coupled LC Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(7), pp. 1959-1972, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Yaqian Sun, Wei Deng 0001, Haikun Jia, Yejun He, Zhihua Wang 0001, Baoyong Chi |
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(10), pp. 2861-2873, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Yizhuo Wang, Jiahe Shi, Hao Xu 0005, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao 0001, Hao Min, Na Yan |
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(8), pp. 2252-2266, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Hee Sung Lee, Tae Hwan Jang, Joon Hyung Kim, Chul Soon Park |
Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With gm-Boosting Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(10), pp. 1629-1633, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Shruti Konwar, Bibhu Datta Sahoo 0002 |
Johnson Counter-Based Multiphase Generation for VCO-Based ADC for Direct Digitization of Low Amplitude Sensor Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 72, pp. 1-4, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski |
Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(3), pp. 1043-1056, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Mahin Esmaeilzadeh, Yves Audet, Mohamed Ali 0001, Mohamad Sawan |
A Low-Offset VCO-Based Time-Domain Comparator Using a Phase Frequency Detector With Reduced Dead and Blind Zones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(3), pp. 1017-1029, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu |
A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(9), pp. 3545-3556, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Xi Meng, Haoran Li, Peng Chen 0022, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins |
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(12), pp. 5110-5123, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Huaiyu Liu, Yang Lin, Liang Qi, Yongwei Lou, Guoxing Wang, Yan Liu 0016 |
Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(3), pp. 1214-1227, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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14 | Jonas Borgmans, Pieter Rombouts |
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(2), pp. 579-592, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|