Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Stephan Nolting, Lin Liu, Guillermo Payá Vayá	Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices.	FPL	2017	DBLP DOI BibTeX RDF
21	Ming Zhu, Yingtao Jiang, Mei Yang, Louie De Luna	A Scalable Parameterized NoC Emulator Built Upon Xilinx Virtex-7 FPGA.	ICSEng	2017	DBLP DOI BibTeX RDF
21	Deepak Kapoor, Rahul Yamasani, Saket Saurav, Abhishek Bajpai	LUT Optimization In Implementation Of Combinational Karatsuba Ofman On Virtex-6 FPGA.	SEM4HPC@HPDC	2016	DBLP DOI BibTeX RDF
21	Vishwa Seneviratne, Arjuna Madanayake, Nilan Udayanga	Wideband 32-element 200-MHz 2-D IIR beam filters using ROACH-2 Virtex-6 sx475t FPGA.	nDS	2015	DBLP DOI BibTeX RDF
21	Alexey I. Dordopulo, Ilya I. Levin, Yuri I. Doronchenko, Maxim K. Raskladkin	High-Performance Reconfigurable Computer Systems Based on Virtex FPGAs.	PaCT	2015	DBLP DOI BibTeX RDF
21	Ignacio Herrera-Alzu, Marisa López-Vallejo, C. Gil Soriano	A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs.	DFTS	2015	DBLP DOI BibTeX RDF
21	Mohamed Anane, Nadjia Anane	SHA-2 hardware core for virtex-5 FPGA.	SSD	2015	DBLP DOI BibTeX RDF
21	Khaldoon Moosa Mhaidat, Ahmad Baset, Osama Daifallah Al-Khaleel	OpenSPARC Processor Evaluation Using Virtex-5 FPGA and High Performance Embedded Computing (HPEC) Benchmark Suite.	Int. J. Embed. Real Time Commun. Syst.	2014	DBLP DOI BibTeX RDF
21	Vlad-Cristian Miclea	Speeding-up polynomial multiplication on Virtex FPGAs: Finding the best addition method.	AQTR	2014	DBLP DOI BibTeX RDF
21	Muzaffar Rao, Thomas Newe, Ian Andrew Grout	Efficient High Speed Implementation of Secure Hash Algorithm-3 on Virtex-5 FPGA.	DSD	2014	DBLP DOI BibTeX RDF
21	Aiwu Ruan, Wei Tian, Bo Ni, Ke Wu	A hierarchical switch matrix and interconnect resources test in Virtex-5 FPGA.	ISIC	2014	DBLP DOI BibTeX RDF
21	Kazuki Kamegai, Takashi Kakue, Tomoyoshi Shimobaba, Tomoyoshi Ito, Nobuyuki Masuda	Development of special-purpose computer based on Virtex-7 FPGA for high-speed digital holography.	APCCAS	2014	DBLP DOI BibTeX RDF
21	S. Syed Ameer Abbas, S. J. Thiruvengadam	Realisation of 3GPP-LTE physical downlink data channel with diversity techniques using PlanAhead tool and Virtex device.	Int. J. Wirel. Mob. Comput.	2013	DBLP DOI BibTeX RDF
21	Riadh Brinci, Walid Khmiri, Mefteh Mbarek, Abdellatif Ben Rabaa, Ammar Bouallegue, Faouzi Chekir	Efficient Multiplier for pairings over Barreto-Naehrig Curves on Virtex-6 FPGA.	IACR Cryptol. ePrint Arch.	2013	DBLP BibTeX RDF
21	Aiwu Ruan, Junhao Yang, Li Wan, Bairui Jie, Zhiqiang Tian	Insight Into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
21	Ali Ebrahim, Khaled Benkrid, Jalal Khalifat, Chuan Hong	A platform for secure IP integration in Xilinx Virtex FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
21	Raymond J. Weber, Justin A. Hogan, Brock J. LaMeres	Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGA.	ReConFig	2013	DBLP DOI BibTeX RDF
21	Rico Backasch, Christian Hochberger	Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables.	ARCS	2013	DBLP DOI BibTeX RDF
21	Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias	Analysis of matrix multiplication on high density Virtex-7 FPGA.	FPL	2013	DBLP DOI BibTeX RDF
21	Cory Gorman, Paul Siqueira, Russell Tessier	An open-source SATA core for Virtex-4 FPGAs.	FPT	2013	DBLP DOI BibTeX RDF
21	Holger Michel, Frank Bubenhagen, Kai Grurmann, Tobias Lange 0002, Björn Fiethe, Harald Michalik	Worst case error rate predictions and mitigation schemes for Virtex-4 FPGAs on solar orbiter.	AHS	2013	DBLP DOI BibTeX RDF
21	Ali Ebrahim, Khaled Benkrid, Xabier Iturbe, Chuan Hong	Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs.	AHS	2013	DBLP DOI BibTeX RDF
21	Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker 0001	Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices.	Int. J. Reconfigurable Comput.	2012	DBLP DOI BibTeX RDF
21	Mário P. Véstias, Horácio C. Neto, Helena Sarmento	Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs.	DSD	2012	DBLP DOI BibTeX RDF
21	Andres Upegui, Julien Izui, Gilles Curchod	Fault mitigation by means of dynamic partial reconfiguration of Virtex-5 FPGAs.	ReConFig	2012	DBLP DOI BibTeX RDF
21	Amir Moradi 0001, Alessandro Barenghi, Timo Kasper, Christof Paar	On the Vulnerability of FPGA Bitstream Encryption against Power Analysis Attacks - Extracting Keys from Xilinx Virtex-II FPGAs.	IACR Cryptol. ePrint Arch.	2011	DBLP BibTeX RDF
21	Jeong-Gun Lee, Deok-Young Lee, Myeong-Hoon Oh, Young Woong Ko	472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
21	Amir Moradi 0001, Alessandro Barenghi, Timo Kasper, Christof Paar	On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs.	CCS	2011	DBLP DOI BibTeX RDF
21	Ignacio Herrera-Alzu, Marisa López-Vallejo	Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs.	PATMOS	2011	DBLP DOI BibTeX RDF
21	Guillermo Conde, Gregory W. Donohoe	Reconfigurable Block Floating Point Processing Elements in Virtex Platforms.	ReConFig	2011	DBLP DOI BibTeX RDF
21	Dur-e-Shahwar Kundi, Arshad Aziz, Nassar Ikram	Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA.	Inf. Process. Lett.	2010	DBLP DOI BibTeX RDF
21	Malte Baesler, Sven-Ole Voigt, Thomas Teufel	A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA.	Int. J. Reconfigurable Comput.	2010	DBLP DOI BibTeX RDF
21	Julien Francq, Céline Thuillet	Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.pdf.	IACR Cryptol. ePrint Arch.	2010	DBLP BibTeX RDF
21	Mohamed El-Hadedy 0001, Danilo Gligoroski, Svein J. Knapskog	Single Core Implementation of Blue Midnight Wish Hash Function on VIRTEX 5 Platform.	IACR Cryptol. ePrint Arch.	2010	DBLP BibTeX RDF
21	Julien Francq, Céline Thuillet	Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.	ReConFig	2010	DBLP DOI BibTeX RDF
21	Mohamed El-Hadedy 0001, Martin Margala, Danilo Gligoroski, Svein J. Knapskog	Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform.	ReConFig	2010	DBLP DOI BibTeX RDF
21	Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker 0001	Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space.	ReConFig	2010	DBLP DOI BibTeX RDF
21	Saeid Taherkhani, Enver Ever, Orhan Gemikonakli	Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology.	CIT	2010	DBLP DOI BibTeX RDF	Very High Speed Integrated Circuit Hardware Description Language, Field Programmable Gate Arrays, Finite State Machine, Data Encryption Standard
21	Yasuaki Ito, Koji Nakano	Efficient exhaustive verification of the Collatz conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
21	Dirk Koch, Christian Beckhoff, Jim Tørresen	Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
21	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson	Packing Techniques for Virtex-5 FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF
21	Stanislav Stankovic, Jaakko Astola	QDD Based Method of Automatic Circuit Design for Xilinx Virtex-5 FPGA Devices.	J. Multiple Valued Log. Soft Comput.	2009	DBLP BibTeX RDF
21	Christian Schuck, Bastian Haetzer, Jürgen Becker 0001	An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing.	Int. J. Reconfigurable Comput.	2009	DBLP DOI BibTeX RDF
21	Peter Alfke	Xilinx Virtex-6 and Spartan-6 FPGA families.	Hot Chips Symposium	2009	DBLP DOI BibTeX RDF
21	Mariusz Grad, Christian Plessl	Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX.	ERSA	2009	DBLP BibTeX RDF
21	Brooks R. Garrison, Daniel T. Milton, Charles E. Stroud	Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays.	CATA	2009	DBLP BibTeX RDF
21	Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Pérez 0001, Armando Astarloa	A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
21	Peter Alfke	Virtex-6 and Spartan-6, plus a look into the future.	FPL	2009	DBLP DOI BibTeX RDF
21	Ángel Quirós-Olozábal, Juan Manuel Barrientos-Villar, Ma de los Ángeles Cifredo Chacón	Reconfiguration-based time-to-digital converter for Virtex FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
21	Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin	Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA.	VTS	2009	DBLP DOI BibTeX RDF
21	Hergys Rexha, Betim Cico	Implementing Codesign in Xilinx Virtex II Pro.	BCI	2009	DBLP DOI BibTeX RDF
21	Per Karlström, Andreas Ehliar, Dake Liu	High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4.	IET Comput. Digit. Tech.	2008	DBLP DOI BibTeX RDF
21	Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle	Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA.	IOLTS	2008	DBLP DOI BibTeX RDF
21	Messaoud Mostefai, Djamila Mechta, Youssef Chahir	Efficient Real Time Face Tracking Operator Study and Implementation Within Virtex FPGA Technology.	Int. Arab J. Inf. Technol.	2007	DBLP BibTeX RDF
21	Jae Young Hur, Stephan Wong, Stamatis Vassiliadis	Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs.	ARC	2007	DBLP DOI BibTeX RDF
21	Subodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang	CAD Techniques for Power Optimization in Virtex-5 FPGAs.	CICC	2007	DBLP DOI BibTeX RDF
21	Farshid Farshadjam, Mehdi Dehghan 0001, Mahmood Fathy, Majid Ahmadi	A new compression based approach for reconfiguration overhead reduction in virtex based RTR systems.	Comput. Electr. Eng.	2006	DBLP DOI BibTeX RDF
21	Katarina Paulsson, Michael Hübner 0001, Markus Jung, Jürgen Becker 0001	Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs.	ISVLSI	2006	DBLP DOI BibTeX RDF	Fault Tolerance, FPGA, Reconfigurable Architectures, Automotive, Organic Computing
21	Christopher Claus, Florian Helmut Müller, Walter Stechele	Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro.	ARCS Workshops	2006	DBLP BibTeX RDF
21	Carsten Bieser, Martin Bahlinger, Matthias Heinz, Christian Stops, Klaus D. Müller-Glaser	A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup.	FPL	2006	DBLP DOI BibTeX RDF
21	Peter J. Green, Desmond P. Taylor	Implementation of a real-time multiple input multiple output channel estimator on the smart antenna software radio test system platform using the Xilinx Virtex 2 Pro Field Programmable Gate Array.	FPT	2006	DBLP DOI BibTeX RDF
21	Blagomir Donchev, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev	External Memory Controller for Virtex II Pro.	SoC	2006	DBLP DOI BibTeX RDF
21	Lok-Kee Ting, Roger F. Woods, C. F. N. Cowan	Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo	Flexible Core Reallocation for Virtex II Structures.	ERSA	2005	DBLP BibTeX RDF
21	Michael Hübner 0001, Katarina Paulsson, Marcus Stitz, Jürgen Becker 0001	Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs.	ARCS Workshops	2005	DBLP BibTeX RDF
21	Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru	Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs.	ARCS Workshops	2005	DBLP BibTeX RDF
21	N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght	Modular Partial Reconfiguration in Virtex FPGAs.	FPL	2005	DBLP DOI BibTeX RDF
21	Gerd Van den Branden, Abdellah Touhafi, Erik F. Dirkx	A Design Methodology to Generate Dynamically Self-Reconfigurable SoCs for Virtex-II Pro FPGAs.	FPT	2005	DBLP BibTeX RDF
21	Messaoud Mostefai, Samira Djebrani, Youssef Chahir	Real Time Embedded Moving Objects Detector - Study and Implementation Within Virtex FPGA Technology.	Comput. Sci. J. Moldova	2004	DBLP BibTeX RDF
21	Romain Desplats, S. Petit, Sana Rezgui, Carl Carmichael, Pascal Fouillat, Dean Lewis	Investigation of SEU sensitivity of Xilinx Virtex II FPGA by pulsed laser fault injections.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
21	Jesse Hunter, Peter Athanas, Cameron D. Patterson	VTSim: A Virtex-II Device Simulator.	ERSA	2004	DBLP BibTeX RDF
21	Brandon Blodget, Christophe Bobda, Michael Hübner 0001, Adronis Niyonkuru	Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
21	Gunnar Tufte, Pauline C. Haddow	Biologically-Inspired: A Rule-Based Self-Reconfiguration of a Virtex Chip.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
21	J. Chandran, R. Kaluri, Jugdutt Singh, Viktor Öwall, Ronny Veljanovski	Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter.	DELTA	2004	DBLP DOI BibTeX RDF
21	Omar Hammami, R. Benmouhoub, Imed Aouadi	Exploring JPEG-2000 entropy coder implementations on xilinx virtex-II pro platforms.	EUSIPCO	2004	DBLP BibTeX RDF
21	Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann	Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations.	VLSI-SOC	2003	DBLP BibTeX RDF
21	Han Tao, Toh Lik Khoong, Chai Geok Ling Serena	Bayesian digital terrain model reconstruction on Virtex-II FPGA.	FPT	2003	DBLP DOI BibTeX RDF
21	Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello	Speed-efficient wide adders for VIRTEX FPGAs.	ICECS	2002	DBLP DOI BibTeX RDF
21	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs.	FPT	2002	DBLP DOI BibTeX RDF
21	Lok-Kee Ting, Roger F. Woods, Colin Cowan	Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver.	FPL	2001	DBLP DOI BibTeX RDF
21	Zhiyuan Li 0008, Scott Hauck	Configuration Compression for Virtex FPGAs.	FCCM	2001	DBLP DOI BibTeX RDF
21	Juri Põldre, Kalle Tammemäe	Reconfigurable Multiplier for Virtex FPGA Family.	FPL	1999	DBLP DOI BibTeX RDF
21	Stefan H.-M. Ludwig, Robert Slous, Satnam Singh	Implementing Photoshop Filters in Virtex.	FPL	1999	DBLP DOI BibTeX RDF
21	Donald MacVicar, Satnam Singh, Robert Slous	Bézier Curve Rendering on Virtex(tm).	FCCM	1999	DBLP DOI BibTeX RDF
21	Bianka Buschbeck, Renate Henschel, Iris Höser, Gerda Klimonow, Andreas Küstner, Ingrid Starke	VIRTEX - a German-Russian Translation Experiment.	COLING	1990	DBLP BibTeX RDF
16	Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong 0001, Xu Cheng 0001	FPGA prototyping of an amba-based windows-compatible SoC.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, microsoft windows, amba, x86
16	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
16	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
16	Mohamed Anane, Hamid Bessalah, Mohamed Issad, Nadjia Anane, Hassen Salhi	Higher Radix and Redundancy Factor for Floating Point SRT Division.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Heng Tan, Ronald F. DeMara	A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	William N. Chelton, Mohammed Benaissa	Fast Elliptic Curve Cryptography on FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	James Moscola, John W. Lockwood, Young H. Cho	Reconfigurable content-based router using hardware-accelerated language parser.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	parser hardware, XML, pattern matching, Parsing, regular expressions, content-based routing
16	Boguslaw Szlachetko, Andrzej Lewandowski	FPGA Implementation of the Gradient Adaptive Lattice Filter Structure for Feature Extraction.	Computer Recognition Systems 2	2008	DBLP DOI BibTeX RDF
16	Etienne Bergeron, Marc Feeley, Jean-Pierre David	Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs.	CC	2008	DBLP DOI BibTeX RDF
16	Valeri Kirischian, Vadim Geurkov, Lev Kirischian	A multi-mode video-stream processor with cyclically reconfigurable architecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	cost-performance ratio, video-stream processor, FPGA, computer architecture, reconfigurable computing, dynamic reconfiguration, pre-fetching, temporal partitioning
16	Máire McLoone, Ciaran McIvor	High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	hash function implementation, cryptography, whirlpool
16	Nouma Izeboudjen, Ahcene Farah, Hamid Bessalah, Ahmed Bouridane, Nassim Chikhi	Towards a Platform for FPGA Implementation of the MLP Based Back Propagation Algorithm.	IWANN	2007	DBLP DOI BibTeX RDF
16	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
16	Katarina Paulsson, Michael Hübner 0001, Günther Auer, Michael Dreschmann, Jürgen Becker 0001	Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Jordana L. Seixas, Edson Barbosa, Stelita M. da Silva, Paulo Sérgio B. do Nascimento, Vinícius Kursancew, Remy Eskinazi Sant'Anna, Edna Barros, Manoel Eusébio de Lima	Aquarius: a dynamically reconfigurable computing platform.	SBCCI	2007	DBLP DOI BibTeX RDF	?CLinux, FPGAs, prototyping, dynamic reconfiguration, tasks scheduling, device driver, bitstream