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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 823 occurrences of 430 keywords
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Results
Found 1191 publication records. Showing 1191 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
32 | Daniel Etiemble |
Ternary and Quaternary CNTFET Full Adders are less efficient than the Binary Ones for Carry-Propagate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.04839, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
32 | P. Balasubramanian 0001, Shigeru Yamashita |
Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1604.04006, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
32 | Robin Perrot, Nadine Azémard, Philippe Maurine |
Request-skip adders : CMOS standard cell data dependent adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 510-513, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Stanislaw J. Piestrak |
Design of residue generators and multioperand modular adders using carry-save adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991, pp. 100-107, 1991, IEEE, 0-8186-9151-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
32 | Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija |
Delay optimization of carry-skip adders and block carry-lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991, pp. 154-164, 1991, IEEE, 0-8186-9151-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
32 | Hung Chi Lai |
A Study of Current Logic Design Problems: Part I, Design of Diagnosable Mos Networks; Part Ii, Minimum Nor (Nand) Networks for Parity Functions of an Arbitrary Number of Variables; Part Iii, Minimum Parallel Binary Adders With Nor (Nand) Gates and Their Extensions to Networks Consisting of Carry-Save Adders ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1976 |
RDF |
|
31 | Robert T. Grisamore, Earl E. Swartzlander Jr. |
Negative Save Sign Extension for Multi-term Adders and Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(1), pp. 1-11, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers |
31 | Robert D. Kenney, Michael J. Schulte |
High-Speed Multioperand Decimal Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 953-963, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic |
31 | Wu-Tung Cheng, Janak H. Patel |
A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(7), pp. 891-895, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
minimum test set, testing, Adders, iterative logic arrays, multiple fault detection |
31 | Alain Guyot, Bertrand Hochet, Jean-Michel Muller |
A Way to Build Efficient Carry-Skip Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(10), pp. 1144-1152, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
VLSI design, Carry-skip adders |
31 | K. Wayne Current |
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(5), pp. 400-403, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
quaternary threshold logic full adders, Multiple-valued logic, threshold logic, parallel counters |
31 | Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan |
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 535-540, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT |
31 | Reto Zimmermann |
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 158-167, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Modulo (2^n=B11) adders and multipliers, end-around-carry parallel-prefix adders, IDEA cipher, cryptography, computer arithmetic, RNS, VLSI circuits |
31 | Jaume A. Segura 0001, Miquel Roca 0001, Diego Mateo, Antonio Rubio 0001 |
An approach to dynamic power consumption current testing of CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 95-100, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current |
31 | Zhi-Jian (Alex) Mou, Francis Jutand |
"Overturned-Stairs" Adder Trees and Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 940-948, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
VLSI circuit layout, multioperand adders, Overturned-Stairs trees, 2's complement parallel multiplier, VLSI, logic design, digital arithmetic, trees (mathematics), adders, multiplying circuits, Wallace trees |
31 | Jordi Cortadella, José M. Llabería |
Evaluation of A + B = K Conditions Without Carry Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(11), pp. 1484-1488, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
parallel adders, carry propagation delay, performance, digital arithmetic, response time, adders |
31 | Abhijit Chatterjee, Jacob A. Abraham |
The Testability of Generalized Counters Under Multiple Faulty Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(11), pp. 1378-1385, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
generalized counters, multiple faulty cells, counting circuits, logic testing, fault model, testability, adders, full adders |
31 | Stephen H. Unger |
Tree Realizations of Iterative Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(4), pp. 365-383, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, tree circuits, synthesis, combinational circuits, Adders, carry lookahead, binary adders |
27 | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1250-1255, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong |
Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1898-1907, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Kavallur Gopi Smitha, A. Prasad Vinod 0001 |
A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2327-2330, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jong-Suk Lee, Dong Sam Ha |
High Speed 1-bit Bypass Adder Design for Low Precision Additions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1093-1096, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López |
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 514-523, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar |
A Power-Aware Technique for Functional Units in High-Performance Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 456-459, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), pp. 1936-1946, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen |
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(3), pp. 343-353, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
B-spline factorization, discrete wavelet transform, VLSI architecture |
27 | Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham |
Constructing zero-deficiency parallel prefix adder of minimum depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 883-888, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Youngmoon Choi, Earl E. Swartzlander Jr. |
Parallel Prefix Adder Design with Matrix Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 90-98, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Ilya Obridko, Ran Ginosar |
Low energy asynchronous architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5238-5241, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 496-499, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner |
Variable delay ripple carry adder with carry chain interrupt detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 113-116, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Massimo Alioto, Gaetano Palumbo |
Analysis and comparison on full adder block in submicron technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 806-823, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Ernest Jamro, Kazimierz Wiatr |
FPGA Implementation of Addition as a Part of the Convolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 458-465, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Feng Zhou, Peter Kornerup |
Computing Moments by Prefix Sums. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(1), pp. 5-17, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Vojin G. Oklobdzija, David Villeger, Thierry Soulas |
An integrated multiplier for complex numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(3), pp. 213-222, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Chang Nian Zhang, Behrooz A. Shirazi, David Y. Y. Yun |
Computing multiple modulo summation (abstract only): a new algorithm, its VLSI designs and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the 15th ACM Annual Conference on Computer Science, St. Louis, Missouri, USA, February 16-19, 1987, pp. 438, 1987, ACM, 0-89791-218-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
25 | Yi Zhu 0002, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng |
Timing-power optimization for mixed-radix Ling adders by integer linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 131-137, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Julien Francq, Jean-Baptiste Rigaud, Pascal Manet, Assia Tria, Arnaud Tisserand |
Error Detection for Borrow-Save Adders Dedicated to ECC Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008, FDTC 2008, Washington, DC, USA, 10 August 2008, pp. 77-86, 2008, IEEE Computer Society, 978-0-7695-3314-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
Synthesis of parallel prefix adders considering switching activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 404-409, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima |
ROM based logic (RBL) design: High-performance and low-power adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 796-799, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Himanshu Thapliyal, A. Prasad Vinod 0001 |
Designing Efficient Online Testable Reversible Adders With New Reversible Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1085-1088, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Massimo Alioto, Gaetano Palumbo |
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3732-3735, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Ismo Hänninen, Jarmo Takala |
Robust Adders Based on Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007, pp. 391-396, 2007, IEEE Computer Society, 978-1-4244-1026-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Taeko Matsunaga, Yusuke Matsunaga |
Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 435-440, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
arithmetic synthesis, dynamic programming, parallel prefix adder |
25 | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 534-540, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Fault tolerance, error checking, high-speed arithmetic |
25 | Kavallur Gopi Smitha, Hossam A. H. Fahmy, A. Prasad Vinod 0001 |
Redundant Adders Consume Less Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 422-425, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 148-152, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Kenny Johansson, Oscar Gustafsson, Lars Wanhammar |
Power Estimation for Ripple-Carry Adders with Correlated Input Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 662-674, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Matthew M. Ziegler, Mircea R. Stan |
A Unified Design Space for Regular Parallel Prefix Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1386-1387, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder |
25 | Jin-Fu Li 0001, Chih-Chiang Hsu |
Efficient Test Methodologies for Conditional Sum Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 319-324, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara |
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 260-261, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng |
An Algorithmic Approach for Generic Parallel Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 734-740, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou |
An Efficient BIST scheme for High-Speed Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 89-93, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou |
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 326-336, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr. |
Quadruple Time Redundancy Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 250-256, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Antonio Blotti, Maurizio Castellucci, Roberto Saletti |
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 118-127, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Peter Kornerup |
Reviewing 4-to-2 Adders for Multi-Operand Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 218-, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Peter-Michael Seidel, Guy Even |
On the Design of Fast IEEE Floating-Point Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 184-194, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Meghanad D. Wagh, Chien-In Henry Chen |
High-level design synthesis with redundancy removal for high speed testable adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 358-361, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Vassilis Paliouras, Thanos Stouraitis |
Novel high-radix residue number system multipliers and adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 451-454, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Bernd Becker 0001, Rolf Drechsler, Sudhakar M. Reddy |
(Quasi-) Linear Path Delay Fault Tests for Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 101-105, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho |
Delay-Insensitive Carry-Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 322-328, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Bernd Becker 0001, Rolf Drechsler, Paul Molitor |
On the generation of area-time optimal testable adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9), pp. 1049-1066, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Zhan Chen, Israel Koren |
Techniques for Yield Enhancement of VLSI Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 222-229, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI yield, VLSI adder, defect tolerance, VLSI layout |
25 | Thomas K. Callaway, Earl E. Swartzlander Jr. |
Estimating the power consumption of CMOS adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 210-216, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Bernd Becker 0001 |
Efficient Testing of Optimal Time Adders (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 1986, Bratislava, Czechoslovakia, August 25-29, 1996, Proceedings, pp. 218-229, 1986, Springer, 3-540-16783-8. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
24 | Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas |
Efficient Reversible Logic Design of BCD Subtractors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Comput. Sci. ![In: Transactions on Computational Science III, pp. 99-121, 2009, Springer, 978-3-642-00211-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
BCD subtractors, BCD adders, Reversible logic |
24 | Michael Kirkedal Thomsen, Holger Bock Axelsen |
Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UC ![In: Unconventional Computing, 7th International Conference, UC 2008, Vienna, Austria, August 25-28, 2008. Proceedings, pp. 228-241, 2008, Springer, 978-3-540-85193-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
quantum computing, adders, circuits, Reversible computing |
24 | M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas |
New and Improved Architectures for Montgomery Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mob. Networks Appl. ![In: Mob. Networks Appl. 12(4), pp. 281-291, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication |
24 | James Alfred Walker, Julian Francis Miller |
Investigating the performance of module acquisition in cartesian genetic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Proceedings, Washington DC, USA, June 25-29, 2005, pp. 1649-1656, 2005, ACM, 1-59593-010-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
digital adders, digital comparators, digital multipliers, modularity, cartesian genetic programming, computational effort, module acquisition |
24 | Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid |
Residue to Binary Number Converters for (2n-1, 2n, 2n+1). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 174-178, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
algorithm, adders, residue number system, circuit, arithmetic |
24 | F. G. Lorca, Lounis Kessal, Didier Demigny |
Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 406-409, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Deriche filter architecture, real time edge detection, optimal edge detectors, FGGA circuits, memory size reduction, scale parameter, first order recursive filter, algorithm, ASIC, CMOS, adders, hardware implementation, IIR filters, IIR filters, software implementation, real time implementation, computation cost reduction, 1.2 micron |
24 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis |
C-Testable modified-Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 241-260, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model |
24 | Albrecht P. Stroele |
Test response compaction using arithmetic functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 380-386, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
arithmetic functions, combinational faults, underflow, feed back, logic testing, built-in self test, digital arithmetic, test pattern generation, adders, circuits, registers, aliasing probability, overflow, subtracters, test response compaction, arithmetic logic units |
24 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 192-198, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
24 | Enric Musoll, Jordi Cortadella |
Scheduling and resource binding for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 104-109, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding |
24 | Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara |
Compact test generation for bridging faults under IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 310-316, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing |
24 | B. Hamdi, Hakim Bederr, Michael Nicolaidis |
A tool for automatic generation of self-checking data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 460-466, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers |
24 | Farzad Zarrinfar |
Economics of "design for test" to remain competitive in the 90s. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(2-3), pp. 171-177, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Bed-of-nails method, DFT strategy, value adders |
24 | Çetin Kaya Koç, Ching Yu Hung |
Bit-level systolic arrays for modular multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(3), pp. 215-223, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
sign estimation, scheduling, systolic array, modular multiplication, carry save adders |
18 | Husain Parvez, Zied Marrakchi, Habib Mehrez |
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 290, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asif, fpga, architecture, application specific, cad |
18 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu |
Energy-aware probabilistic multiplier: design and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 281-290, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, multiplier, voltage scaling, probabilistic computation |
18 | Jun Chen, James E. Stine |
Parallel Prefix Ling Structures for Modulo 2^n-1 Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 16-23, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Sang-Hun Yoon, Jin-Doo Jeong, Jong-Wha Chong |
An area reduction method for digital filter using redundancy of SD number system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUIMC ![In: Proceedings of the 3rd International Conference on Ubiquitous Information Management and Communication, ICUIMC 2009, Suwon, Korea, January 15-16, 2009, pp. 504-508, 2009, ACM, 978-1-60558-405-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adder sharing, flattened coefficient, architecture, digital filter |
18 | Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz |
A fault tolerant, area efficient architecture for Shor's factoring algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 383-394, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ion trap, control, quantum computing, layout, cad |
18 | Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita |
Arithmetic Circuits Verification without Looking for Internal Equivalences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 7-16, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yan Sun, Xin Zhang, Xi Jin |
High-Performance Carry Select Adder Using Fast All-One Finding Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Second Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, Malaysia, May 13-15, 2008, pp. 1012-1014, 2008, IEEE Computer Society, 978-0-7695-3136-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fast all-one finding circuit, add-one circuit, carry-select adder |
18 | Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon |
Integrated circuit design with NEM relays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 750-757, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado |
Applying speculation techniques to implement functional units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 74-80, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001 |
Arithmetic module generator with algorithm optimization capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1796-1799, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith |
Glitch-aware output switching activity from word-level statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1792-1795, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Toshinori Sato, Shingo Watanabe |
Instruction Scheduling for Variation-Originated Variable Latencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 361-364, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations |
18 | Sabyasachi Das, Sunil P. Khatri |
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 572-579, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | S. Vijay, A. Prasad Vinod 0001, Edmund Ming-Kit Lai |
A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3451-3454, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Swapnil Bahl |
A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 331-339, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi |
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(2), pp. 149-158, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
(4,2)-compressor, digit set, signed digit, computer arithmetic, redundant number system, carry-free addition |
18 | Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner |
High speed FIR filter implementation using add and shift method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 231, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Janusz Biernat |
Self-Dual Modules in Design of Dependable Digital Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DepCoS-RELCOMEX ![In: 2006 International Conference on Dependability of Computer Systems (DepCoS-RELCOMEX 2006), 24-28 May 2006, Szklarska Poreba, Poland, pp. 276-281, 2006, IEEE Computer Society, 0-7695-2565-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis |
Asynchronous circuit design on reconfigurable devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 20-25, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGAs, asynchronous circuits |
18 | V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel |
Semi-Custom Design of Adiabatic Adder Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 745-748, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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