Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
32	Daniel Etiemble	Ternary and Quaternary CNTFET Full Adders are less efficient than the Binary Ones for Carry-Propagate Adders.	CoRR	2022	DBLP DOI BibTeX RDF
32	P. Balasubramanian 0001, Shigeru Yamashita	Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders.	CoRR	2016	DBLP BibTeX RDF
32	Robin Perrot, Nadine Azémard, Philippe Maurine	Request-skip adders : CMOS standard cell data dependent adders.	ICECS	2006	DBLP DOI BibTeX RDF
32	Stanislaw J. Piestrak	Design of residue generators and multioperand modular adders using carry-save adders.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
32	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay optimization of carry-skip adders and block carry-lookahead adders.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
32	Hung Chi Lai	A Study of Current Logic Design Problems: Part I, Design of Diagnosable Mos Networks; Part Ii, Minimum Nor (Nand) Networks for Parity Functions of an Arbitrary Number of Variables; Part Iii, Minimum Parallel Binary Adders With Nor (Nand) Gates and Their Extensions to Networks Consisting of Carry-Save Adders		1976	RDF
31	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
31	Robert D. Kenney, Michael J. Schulte	High-Speed Multioperand Decimal Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic
31	Wu-Tung Cheng, Janak H. Patel	A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	minimum test set, testing, Adders, iterative logic arrays, multiple fault detection
31	Alain Guyot, Bertrand Hochet, Jean-Michel Muller	A Way to Build Efficient Carry-Skip Adders.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	VLSI design, Carry-skip adders
31	K. Wayne Current	Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	quaternary threshold logic full adders, Multiple-valued logic, threshold logic, parallel counters
31	Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan	A New Divide and Conquer Method for Achieving High Speed Division in Hardware.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT
31	Reto Zimmermann	Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF	Modulo (2^n=B11) adders and multipliers, end-around-carry parallel-prefix adders, IDEA cipher, cryptography, computer arithmetic, RNS, VLSI circuits
31	Jaume A. Segura 0001, Miquel Roca 0001, Diego Mateo, Antonio Rubio 0001	An approach to dynamic power consumption current testing of CMOS ICs.	VTS	1995	DBLP DOI BibTeX RDF	dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current
31	Zhi-Jian (Alex) Mou, Francis Jutand	"Overturned-Stairs" Adder Trees and Multiplier Design.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	VLSI circuit layout, multioperand adders, Overturned-Stairs trees, 2's complement parallel multiplier, VLSI, logic design, digital arithmetic, trees (mathematics), adders, multiplying circuits, Wallace trees
31	Jordi Cortadella, José M. Llabería	Evaluation of A + B = K Conditions Without Carry Propagation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	parallel adders, carry propagation delay, performance, digital arithmetic, response time, adders
31	Abhijit Chatterjee, Jacob A. Abraham	The Testability of Generalized Counters Under Multiple Faulty Cells.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	generalized counters, multiple faulty cells, counting circuits, logic testing, fault model, testability, adders, full adders
31	Stephen H. Unger	Tree Realizations of Iterative Circuits.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	conditional sum, flow tables, high speed arithmetic units, iterative circuits, modular circuits, semi-groups, tree circuits, synthesis, combinational circuits, Adders, carry lookahead, binary adders
27	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design.	DATE	2008	DBLP DOI BibTeX RDF
27	Fei Xu, Chip-Hong Chang, Ching-Chuen Jong	Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Kavallur Gopi Smitha, A. Prasad Vinod 0001	A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Jong-Suk Lee, Dong Sam Ha	High Speed 1-bit Bypass Adder Design for Low Precision Additions.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López	A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.	PATMOS	2006	DBLP DOI BibTeX RDF
27	Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar	A Power-Aware Technique for Functional Units in High-Performance Processors.	DSD	2006	DBLP DOI BibTeX RDF
27	A. Prasad Vinod 0001, Edmund Ming-Kit Lai	An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
27	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen	VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	B-spline factorization, discrete wavelet transform, VLSI architecture
27	Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham	Constructing zero-deficiency parallel prefix adder of minimum depth.	ASP-DAC	2005	DBLP DOI BibTeX RDF
27	Youngmoon Choi, Earl E. Swartzlander Jr.	Parallel Prefix Adder Design with Matrix Representation.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
27	Ilya Obridko, Ran Ginosar	Low energy asynchronous architectures.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
27	A. Prasad Vinod 0001, Edmund Ming-Kit Lai	Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
27	Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner	Variable delay ripple carry adder with carry chain interrupt detection.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Massimo Alioto, Gaetano Palumbo	Analysis and comparison on full adder block in submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
27	Ernest Jamro, Kazimierz Wiatr	FPGA Implementation of Addition as a Part of the Convolution.	DSD	2001	DBLP DOI BibTeX RDF
27	Feng Zhou, Peter Kornerup	Computing Moments by Prefix Sums.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
27	Vojin G. Oklobdzija, David Villeger, Thierry Soulas	An integrated multiplier for complex numbers.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
27	Chang Nian Zhang, Behrooz A. Shirazi, David Y. Y. Yun	Computing multiple modulo summation (abstract only): a new algorithm, its VLSI designs and applications.	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
25	Yi Zhu 0002, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng	Timing-power optimization for mixed-radix Ling adders by integer linear programming.	ASP-DAC	2008	DBLP DOI BibTeX RDF
25	Julien Francq, Jean-Baptiste Rigaud, Pascal Manet, Assia Tria, Arnaud Tisserand	Error Detection for Borrow-Save Adders Dedicated to ECC Unit.	FDTC	2008	DBLP DOI BibTeX RDF
25	Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga	Synthesis of parallel prefix adders considering switching activities.	ICCD	2008	DBLP DOI BibTeX RDF
25	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima	ROM based logic (RBL) design: High-performance and low-power adders.	ISCAS	2008	DBLP DOI BibTeX RDF
25	Himanshu Thapliyal, A. Prasad Vinod 0001	Designing Efficient Online Testable Reversible Adders With New Reversible Gate.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Massimo Alioto, Gaetano Palumbo	Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
25	Ismo Hänninen, Jarmo Takala	Robust Adders Based on Quantum-Dot Cellular Automata.	ASAP	2007	DBLP DOI BibTeX RDF
25	Taeko Matsunaga, Yusuke Matsunaga	Area minimization algorithm for parallel prefix adders under bitwise delay constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	arithmetic synthesis, dynamic programming, parallel prefix adder
25	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Fault tolerance, error checking, high-speed arithmetic
25	Kavallur Gopi Smitha, Hossam A. H. Fahmy, A. Prasad Vinod 0001	Redundant Adders Consume Less Energy.	APCCAS	2006	DBLP DOI BibTeX RDF
25	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.	ISQED	2005	DBLP DOI BibTeX RDF
25	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Power Estimation for Ripple-Carry Adders with Correlated Input Data.	PATMOS	2004	DBLP DOI BibTeX RDF
25	Matthew M. Ziegler, Mircea R. Stan	A Unified Design Space for Regular Parallel Prefix Adders.	DATE	2004	DBLP DOI BibTeX RDF	Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder
25	Jin-Fu Li 0001, Chih-Chiang Hsu	Efficient Test Methodologies for Conditional Sum Adders.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
25	Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara	High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.	ISVLSI	2003	DBLP DOI BibTeX RDF
25	Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng	An Algorithmic Approach for Generic Parallel Adders.	ICCAD	2003	DBLP DOI BibTeX RDF
25	Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou	An Efficient BIST scheme for High-Speed Adders.	IOLTS	2003	DBLP DOI BibTeX RDF
25	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A Family of Parallel-Pre.x Modulo 2n - 1 Adders.	ASAP	2003	DBLP DOI BibTeX RDF
25	Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.	Quadruple Time Redundancy Adders.	DFT	2003	DBLP DOI BibTeX RDF
25	Antonio Blotti, Maurizio Castellucci, Roberto Saletti	Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library.	PATMOS	2002	DBLP DOI BibTeX RDF
25	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	ASAP	2002	DBLP DOI BibTeX RDF
25	Peter-Michael Seidel, Guy Even	On the Design of Fast IEEE Floating-Point Adders.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
25	Meghanad D. Wagh, Chien-In Henry Chen	High-level design synthesis with redundancy removal for high speed testable adders.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
25	Vassilis Paliouras, Thanos Stouraitis	Novel high-radix residue number system multipliers and adders.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
25	Bernd Becker 0001, Rolf Drechsler, Sudhakar M. Reddy	(Quasi-) Linear Path Delay Fault Tests for Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
25	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho	Delay-Insensitive Carry-Lookahead Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
25	Bernd Becker 0001, Rolf Drechsler, Paul Molitor	On the generation of area-time optimal testable adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
25	Zhan Chen, Israel Koren	Techniques for Yield Enhancement of VLSI Adders.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI yield, VLSI adder, defect tolerance, VLSI layout
25	Thomas K. Callaway, Earl E. Swartzlander Jr.	Estimating the power consumption of CMOS adders.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
25	Bernd Becker 0001	Efficient Testing of Optimal Time Adders (Extended Abstract).	MFCS	1986	DBLP DOI BibTeX RDF
24	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas	Efficient Reversible Logic Design of BCD Subtractors.	Trans. Comput. Sci.	2009	DBLP DOI BibTeX RDF	BCD subtractors, BCD adders, Reversible logic
24	Michael Kirkedal Thomsen, Holger Bock Axelsen	Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder.	UC	2008	DBLP DOI BibTeX RDF	quantum computing, adders, circuits, Reversible computing
24	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	New and Improved Architectures for Montgomery Modular Multiplication.	Mob. Networks Appl.	2007	DBLP DOI BibTeX RDF	reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
24	James Alfred Walker, Julian Francis Miller	Investigating the performance of module acquisition in cartesian genetic programming.	GECCO	2005	DBLP DOI BibTeX RDF	digital adders, digital comparators, digital multipliers, modularity, cartesian genetic programming, computational effort, module acquisition
24	Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid	Residue to Binary Number Converters for (2n-1, 2n, 2n+1).	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	algorithm, adders, residue number system, circuit, arithmetic
24	F. G. Lorca, Lounis Kessal, Didier Demigny	Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection.	ICIP (2)	1997	DBLP DOI BibTeX RDF	Deriche filter architecture, real time edge detection, optimal edge detectors, FGGA circuits, memory size reduction, scale parameter, first order recursive filter, algorithm, ASIC, CMOS, adders, hardware implementation, IIR filters, IIR filters, software implementation, real time implementation, computation cost reduction, 1.2 micron
24	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
24	Albrecht P. Stroele	Test response compaction using arithmetic functions.	VTS	1996	DBLP DOI BibTeX RDF	arithmetic functions, combinational faults, underflow, feed back, logic testing, built-in self test, digital arithmetic, test pattern generation, adders, circuits, registers, aliasing probability, overflow, subtracters, test response compaction, arithmetic logic units
24	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
24	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
24	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
24	B. Hamdi, Hakim Bederr, Michael Nicolaidis	A tool for automatic generation of self-checking data paths.	VTS	1995	DBLP DOI BibTeX RDF	self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers
24	Farzad Zarrinfar	Economics of "design for test" to remain competitive in the 90s.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Bed-of-nails method, DFT strategy, value adders
24	Çetin Kaya Koç, Ching Yu Hung	Bit-level systolic arrays for modular multiplication.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF	sign estimation, scheduling, systolic array, modular multiplication, carry save adders
18	Husain Parvez, Zied Marrakchi, Habib Mehrez	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	asif, fpga, architecture, application specific, cad
18	Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu	Energy-aware probabilistic multiplier: design and analysis.	CASES	2009	DBLP DOI BibTeX RDF	optimization, multiplier, voltage scaling, probabilistic computation
18	Jun Chen, James E. Stine	Parallel Prefix Ling Structures for Modulo 2^n-1 Addition.	ASAP	2009	DBLP DOI BibTeX RDF
18	Sang-Hun Yoon, Jin-Doo Jeong, Jong-Wha Chong	An area reduction method for digital filter using redundancy of SD number system.	ICUIMC	2009	DBLP DOI BibTeX RDF	adder sharing, flattened coefficient, architecture, digital filter
18	Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz	A fault tolerant, area efficient architecture for Shor's factoring algorithm.	ISCA	2009	DBLP DOI BibTeX RDF	ion trap, control, quantum computing, layout, cad
18	Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita	Arithmetic Circuits Verification without Looking for Internal Equivalences.	MEMOCODE	2008	DBLP DOI BibTeX RDF
18	Yan Sun, Xin Zhang, Xi Jin	High-Performance Carry Select Adder Using Fast All-One Finding Logic.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	fast all-one finding circuit, add-one circuit, carry-select adder
18	Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon	Integrated circuit design with NEM relays.	ICCAD	2008	DBLP DOI BibTeX RDF
18	Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado	Applying speculation techniques to implement functional units.	ICCD	2008	DBLP DOI BibTeX RDF
18	Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Arithmetic module generator with algorithm optimization capability.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith	Glitch-aware output switching activity from word-level statistics.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
18	Sabyasachi Das, Sunil P. Khatri	A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	S. Vijay, A. Prasad Vinod 0001, Edmund Ming-Kit Lai	A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Swapnil Bahl	A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema.	DFT	2007	DBLP DOI BibTeX RDF
18	Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi	An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	(4,2)-compressor, digit set, signed digit, computer arithmetic, redundant number system, carry-free addition
18	Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner	High speed FIR filter implementation using add and shift method.	FPGA	2006	DBLP DOI BibTeX RDF
18	Janusz Biernat	Self-Dual Modules in Design of Dependable Digital Devices.	DepCoS-RELCOMEX	2006	DBLP DOI BibTeX RDF
18	R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis	Asynchronous circuit design on reconfigurable devices.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGAs, asynchronous circuits
18	V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel	Semi-Custom Design of Adiabatic Adder Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF