Search results for "crossbar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.	ARCS	2007	DBLP DOI BibTeX RDF
31	Xiangjie Ma, Yuxiang Hu, Junpeng Mao, Julong Lan, Lian Guan, Baisheng Zhang	Analysis on Memory-Space-Memory Clos Packet Switching Network.	APPT	2007	DBLP DOI BibTeX RDF
31	Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen	A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.	DSD	2006	DBLP DOI BibTeX RDF
31	Shang-Tse Chuang, Sundar Iyer, Nick McKeown	Practical algorithms for performance guarantees in buffered crossbars.	INFOCOM	2005	DBLP DOI BibTeX RDF
31	Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal	Logic emulation with virtual wires.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
31	Andreas Nowatzyk, Paul R. Prucnal	Are Crossbars Really Dead? The Case for Optical Multiprocessor Interconnect Systems.	ISCA	1995	DBLP DOI BibTeX RDF
31	Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita	The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures.	ICS	1989	DBLP DOI BibTeX RDF
29	Vamsee Reddy Kommareddy, Baogang Zhang, Fan Yao, Rickard Ewetz, Amro Awad	Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
29	Stefan Sinzinger, Qing Cao, Matthias Gruber, Jürgen Jahns	Integrierte optoelektronische Crossbar-Architekturen in planar-integrierter Freiraumoptik (Integrated Optoelectronic Crossbar Architectures in Planar Integrated Free-Space Optics).	it Inf. Technol.	2003	DBLP DOI BibTeX RDF
29	Farzad Ghannadian, Toshiro Kubota, Joseph I. Chamdani, Philip R. Bingham, Cecil O. Alford	Crossbar Controller for the Adaptive Multistage Crossbar Network.	PDPTA	1996	DBLP BibTeX RDF
27	M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli	Decoding nanowire arrays fabricated with the multi-spacer patterning technique.	DAC	2009	DBLP DOI BibTeX RDF	MSPT, spacer technique, decoder, emerging technologies, crossbar, nanowires
27	George F. Georgakopoulos	Buffered cross-bar switches, revisited: design steps, proofs and simulations towards optimal rate and minimum buffer memory.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	buffered crossbar switches, packet switching, strategic games
27	Reza M. Rad, Mohammad Tehranipoor	SCT: A novel approach for testing and configuring nanoscale devices.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Configuration and testing, reconfigurable nanoscale devices, fault tolerance, crossbar, nanowire
27	Dianxun Shuai, Xiang Feng	Distributed Problem Solving in Multiagent Systems: A Spring Net Approach.	IEEE Intell. Syst.	2005	DBLP DOI BibTeX RDF	crossbar composite spring net, parallel algorithm, multiagent system, distributed artificial intelligence, distributed problem solving
27	Tetsuro Kakeshita, Shenglin Zhang	The Net Disk Architecture for Dynamic Load Balancing among Disk Arrays.	ICPADS	2000	DBLP DOI BibTeX RDF	Parallel Disk System, Dynamic Data Migration, Dynamic Load Balancing, Crossbar Network
27	Pertti Raatikainen, Teleste Oy, Juha Zidbeck	Performance Comparison of Experimented Switching Architectures for ATM.	EUROMICRO	1996	DBLP DOI BibTeX RDF	broadband switching, transfer delay performance, Frame Synchronized Ring, switch structures, multidrop bus, multistage banyan network, interconnection networks, ATM, multiprocessor interconnection networks, ATM-switch, crossbar
27	Justin Strohschneider, Bernd Klauer, Klaus Waldschmidt	An associative communication network for fine and large grain dataflow.	PDP	1995	DBLP DOI BibTeX RDF	associative processing, associative communication network, large grain dataflow, fine grain dataflow, Associative Dataflow Architecture, ADARC, parallel architectures, multiprocessor interconnection networks, hardware implementation, content-addressable storage, crossbar switch, distributed associative memory
27	Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou	Pipelined Memory Shared Buffer for VLSI Switches.	SIGCOMM	1995	DBLP DOI BibTeX RDF	gigabit VLSI switch buffer, multiport buffer, pipelined memory, crossbar switch, shared buffering, input queueing
27	Xiaotie Deng, Patrick W. Dymond	Efficient routing and message bounds for optimal parallel algorithms.	IPPS	1995	DBLP DOI BibTeX RDF	message bounds, round-robin message-delivery, routing, parallel algorithms, computational complexity, routing algorithm, network routing, interprocessor communication, optimal parallel algorithms, crossbar networks, h-relations
27	Rudolf Holzner, Stefan Tomann	Design and Simulation of a Multistage Interconnection Network.	CONPAR	1990	DBLP DOI BibTeX RDF	buffering scheme, parallel computer, network simulation, crossbar switch, virtual cut-through, delta network
25	Mehdi Baradaran Tahoori	Low-overhead defect tolerance in crossbar nanoarchitectures.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	reconfigurable architectures, nanotechnology, Defect tolerance
25	M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli	Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.	CASES	2009	DBLP DOI BibTeX RDF	MSPT, spacer technique, decoder, emerging technologies, gray code, crossbars, nanowires
25	Mohammad Tehranipoor, Reza M. Rad	Defect Tolerance for Nanoscale Crossbar-Based Devices.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
25	Dimitrios Simos, Ioannis Papaefstathiou, Manolis Katevenis	Building an FoC Using Large, Buffered Crossbar Cores.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
25	Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wladek Olesinski, Hans Eberle, Nils Gura	Backlog Aware Scheduling for Large Buffered Crossbar Switches.	ICC	2008	DBLP DOI BibTeX RDF
25	Dengyuan Xu	A Novel Scheduling Algorithm Based on Buffered Crossbar Switch Fabric in EPFTS Switch.	CSSE (3)	2008	DBLP DOI BibTeX RDF
25	Michael J. Neely, Eytan H. Modiano, Yuan-Sheng Cheng	Logarithmic delay for N × N packet switches under the crossbar constraint.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	stochastic queueing analysis, scheduling, optimal control
25	Choudhury A. Al Sayeed, Dewan Tanvir Ahmed, Akbar Ghaffar Pour Rahbar	Hybrid Maximal Matching for Input Buffered Crossbar Switches.	CNSR	2007	DBLP DOI BibTeX RDF
25	Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis	Systematic Customization of On-Chip Crossbar Interconnects.	ARC	2007	DBLP DOI BibTeX RDF
25	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.	ICCAD	2007	DBLP DOI BibTeX RDF
25	O. Zouraraki, Paraskevas Bakopoulos, K. Vyrsokinos, Hercules Avramopoulos	2x2 Bismuth-Oxide-Fiber Based Crossbar Switch for All-Optical Switching Architectures.	ONDM	2007	DBLP DOI BibTeX RDF	Optically controlled 2x2 switch, Bismuth Oxide Nonlinear fiber, Ultrafast Nonlinear Interferometer (UNI), all-optical signal processing
25	George Kornaros	BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory.	DSD	2006	DBLP DOI BibTeX RDF
25	Shane O'Neill, Alan Marshall 0001, Roger F. Woods	Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch.	ISCC	2006	DBLP DOI BibTeX RDF
25	Mehdi Baradaran Tahoori	Application-independent defect-tolerant crossbar nano-architectures.	ICCAD	2006	DBLP DOI BibTeX RDF
25	Henrique C. Freitas, Milene Barbosa Carvalho, Alexandre Marques Amaral, Amanda R. M. Diniz, Carlos Augusto Paiva da Silva Martins, Luiz Eduardo da Silva Ramos	Reconfigurable crossbar switch architecture for network processors.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Ghim Hwee Ong, Jun-Ping Ng	Dynamic Markov Compression Using a Crossbar-Like Tree Initial Structure for Chinese Texts.	ICITA (2)	2005	DBLP DOI BibTeX RDF
25	Minsu Choi, Nohpill Park	Teaching Nanotechnology by Introducing Crossbar-Based Architecture and Quantum-Dot Cellular Automata.	MSE	2005	DBLP DOI BibTeX RDF
25	Carlos Roberto dos Santos, Shusaburo Motoyama	A QoS Provisioned CIOQ Packet Switch Using Crossbar Structure with m Internal Links.	Systems Communications	2005	DBLP DOI BibTeX RDF
25	Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif	CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors.	DSD	2003	DBLP DOI BibTeX RDF
25	Steven P. Young, Peter Alfke, Colm Fewer, Scott McMillan, Brandon Blodget, Delon Levi	A High I/O Reconfigurable Crossbar Switch.	FCCM	2003	DBLP DOI BibTeX RDF
25	Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui	Design and implementation of high-speed arbiter for large scale VOQ crossbar switches.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
25	Naoyuki Fujita, Hirofumi Ookawa	Storage Devices, Local File System and Crossbar Network File System Characteristics, and 1 Terabyte File IO Benchmark on the "Numerical Simulator III" .	IEEE Symposium on Mass Storage Systems	2003	DBLP DOI BibTeX RDF
25	Yoshiko Yasuda, Hiroaki Fujii, Hideya Akashi, Yasuhiro Inagami, Teruo Tanaka, Junji Nakagoshi, Hideo Wada, Tsutomu Sumimoto	Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201.	IPPS	1997	DBLP DOI BibTeX RDF
25	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	Implementing the Data Diffusion Machine Using Crossbar Routers.	IPPS	1996	DBLP DOI BibTeX RDF	multithreading, multitasking, COMA, virtual shared memory
21	Yeow Meng Chee, Alan C. H. Ling	Limit on the Addressability of Fault-Tolerant Nanowire Decoders.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
21	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
21	Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
21	Eryk Laskowski, Marek Tudruj	Optimized Communication Control in Programs for Dynamic Look-Ahead Reconfigurable SoC Systems.	ISPDC	2008	DBLP DOI BibTeX RDF
21	Jiaxin Li, Ning Deng 0002, Caixia Liu, Mengxiao Liu, Zuo Wang, Qi Zuo	FG-NC: A Schedule Algorithm of Designing Concurrent Multi-direction Data Switch Structure.	ICYCS	2008	DBLP DOI BibTeX RDF
21	Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos	Fast arbiters for on-chip network switches.	ICCD	2008	DBLP DOI BibTeX RDF
21	Qixin Wang, Sathish Gopalakrishnan, Xue Liu 0001, Lui Sha	A Switch Design for Real-Time Industrial Networks.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF
21	Mingjie Lin, Steve Ferguson, Yaling Ma, Timothy Greene	HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Yoonjae Huh, Yoon-Hwa Choi	Module Grouping for Defect Tolerance in Nanoscale Memory.	DFT	2008	DBLP DOI BibTeX RDF
21	Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos A. Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic	Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics.	Hot Interconnects	2008	DBLP DOI BibTeX RDF
21	Rongsen He, José G. Delgado-Frias	Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Interleaved switching fabrics, RAIF (Redundant Array of Independent Fabrics), I-Cubeout network, multistage interconnection network (MIN)
21	Jay Cheng	Constructions of Fault-Tolerant Optical 2-to-1 FIFO Multiplexers.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
21	Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan	Designing CMOS/molecular memories while considering device parameter variations.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	CMOS, nanotechnology, molecular electronics
21	Donghyun Kim, Kwanho Kim, Joo-Young Kim 0001, Seungjin Lee 0001, Hoi-Jun Yoo	Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.	NOCS	2007	DBLP DOI BibTeX RDF
21	Cyriel Minkenberg, Mitchell Gusat	Speculative Flow Control for High-Radix Datacenter Interconnect Routers.	IPDPS	2007	DBLP DOI BibTeX RDF
21	Ge Nong, Ning Situ, Mounir Hamdi	Delay Analysis of Combined Input-Crosspoint Queueing Switches.	ICCCN	2007	DBLP DOI BibTeX RDF
21	Eryk Laskowski, Marek Tudruj	Inter-processor Communication Optimization in Dynamically Reconfigurable Embedded Parallel Systems.	PPAM	2007	DBLP DOI BibTeX RDF
21	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.	ICPP	2007	DBLP DOI BibTeX RDF
21	Hyoung-Il Lee, Seung-Woo Seo	Matching output queueing with a multiple input/output-queued switch.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	combined input/output-queued (CIOQ) switch, multiple input/output-queued (MIOQ) switch, output queueing emulation, parallel switching architecture
21	Mehdi Baradaran Tahoori	Application-independent defect tolerance of reconfigurable nanoarchitectures.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, nanotechnology, Defect tolerance
21	Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie E. Taylor, Paul S. Graham, Maya B. Gokhale	A hybrid framework for design and analysis of fault-tolerant architectures.	DATE	2006	DBLP DOI BibTeX RDF
21	Eryk Laskowski, Marek Tudruj	Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources.	DSD	2006	DBLP DOI BibTeX RDF
21	Eryk Laskowski, Marek Tudruj	Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections.	PARELEC	2006	DBLP DOI BibTeX RDF
21	Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour	Design approaches for hybrid CMOS/molecular memory based on experimental device data.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
21	Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim	Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects.	DFT	2006	DBLP DOI BibTeX RDF
21	Peng Yi, Han Qiu 0004, Binqiang Wang	Implementing Priority Scheduling in a Combined Input-Crosspoint-Output Queued Switch.	AINA (2)	2006	DBLP DOI BibTeX RDF
21	Haitham S. Hamza, Jitender S. Deogun	Design and Analysis of a New Class of WDM Optical Interconnect Architectures.	BROADNETS	2006	DBLP DOI BibTeX RDF
21	Young-Su Kwon, C.-M. Kyung	ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	Yuanyuan Yang 0001, Jianchao Wang	Cost-Effective Designs of WDM Optical Interconnects.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	multicast, permutation, network architectures, optical interconnects, Wavelength-division-multiplexing (WDM), optical switches, wavelength conversion, multistage networks, sparse crossbars
21	Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
21	Seung Wook Lee, Jong Tae Kim, Bong Ki Sohn, Keon-Myung Lee, Jee-Hyung Lee, Jae Wook Jeon, Sukhan Lee 0001	Real-Time System-on-a-Chip Architecture for Rule-Based Context-Aware Computing.	KES (1)	2005	DBLP DOI BibTeX RDF
21	John Kim, William J. Dally, Brian Towles, Amit K. Gupta	Microarchitecture of a High-Radix Router.	ISCA	2005	DBLP DOI BibTeX RDF
21	Siu-Kei Wong, Chi-Ying Tsui	Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus.	DATE	2004	DBLP DOI BibTeX RDF
21	Patrick Lysaght, Delon Levi	Of Gates and Wires.	IPDPS	2004	DBLP DOI BibTeX RDF
21	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	Power-driven Design of Router Microarchitectures in On-chip Networks.	MICRO	2003	DBLP DOI BibTeX RDF
21	Hideharu Amano, Akiya Jouraku, Kenichiro Anjo	A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device.	FPL	2003	DBLP DOI BibTeX RDF
21	Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi	An architectural exploration of via patterned gate arrays.	ISPD	2003	DBLP DOI BibTeX RDF	VPGA, lookup table, interconnect architectures, gate array
21	Yuanyuan Yang 0001, Jianchao Wang	Sparse WDM Optical Interconnects under Wavelength-Based Model.	IPDPS	2003	DBLP DOI BibTeX RDF	multicast, Interconnection networks, permutation, optical interconnects, wavelength-division-multiplexing (WDM), wavelength conversion, multistage networks, sparse crossbars
21	Xiaofeng Hu, Zhigang Sun, Xicheng Lu, Jinshu Su	Using Split Queues to Improve the Performance of Parallel Switch.	APPT	2003	DBLP DOI BibTeX RDF
21	John E. Savage	Computing with Electronic Nanotechnologies.	CIAC	2003	DBLP DOI BibTeX RDF
21	Young-Su Kwon, Bong-Il Park, Chong-Min Kyung	SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture.	ICCD	2003	DBLP DOI BibTeX RDF
21	Ali Mohammad Zareh Bidoki, Nasser Yazdani, Sayed Vahid Azhari, Siavash Samadian-Barzoki	A High Speed ATM/IP Switch Fabric Using Distributed Scheduler.	ICOIN	2003	DBLP DOI BibTeX RDF
21	Honglin Wu, Amir Gourgy, Ted H. Szymanski	An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks.	LCN	2003	DBLP DOI BibTeX RDF
21	María Blanca Caminero, Carmen Carrión 0001, Francisco J. Quiles 0001, José Duato, Sudhakar Yalamanchili	Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router.	IPDPS	2002	DBLP DOI BibTeX RDF	Quality of Service, multimedia communications, router architecture, switch scheduler
21	Cheng-Shang Chang, Duan-Shin Lee, Ching-Ming Lien	Load balanced Birkhoff-von Neumann switches with resequencing.	SIGMETRICS Perform. Evaluation Rev.	2001	DBLP DOI BibTeX RDF
21	Guy G. Lemieux, Paul Leventis, David M. Lewis	Generating highly-routable sparse crossbars for PLDs.	FPGA	2000	DBLP DOI BibTeX RDF
21	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
21	Scott Hauck, Gaetano Borriello, Carl Ebeling	Mesh routing topologies for multi-FPGA systems.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
21	Amnon Barak, Eugen Schenfeld	Embedding Classical Communication Topologies in the Scalable OPAM Architecture.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	Graph contractions, parallel programs, interconnection networks, graph embeddings, mapping algorithms
21	Suresh Chalasani, Rajendra V. Boppana	Fault-Tolerance with Multimodule Routers.	HPCA	1996	DBLP DOI BibTeX RDF	multimodule routers, fault-tolerance, communication, multicomputers, wormhole switching, deadlock-free routing
21	Teruo Utsumi, Masayuki Ikeda, Moriyuki Takamura	Architecture of the VPP500 parallel supercomputer.	SC	1994	DBLP DOI BibTeX RDF
21	Susan S. Owicki, Anna R. Karlin	Factors in the Performance of the AN1 Computer Network.	SIGMETRICS	1992	DBLP DOI BibTeX RDF
21	Ted H. Szymanski, Chien Fang	Design and analysis of buffered crossbars and banyans with cut-through switching.	SC	1990	DBLP DOI BibTeX RDF
21	U. V. Premkumar, Rajan N. Kapur, Miroslaw Malek, G. Jack Lipovski, P. Horne	Design and implementation of the banyan interconnection network in TRAC.	AFIPS National Computer Conference	1980	DBLP DOI BibTeX RDF
17	T. H. Szymanski	Scheduling and Channel Assignment of Backhaul Traffic in Infrastructure Wireless Mesh Networks with Near-Minimal Delay and Jitter.	ICDS	2010	DBLP DOI BibTeX RDF	backhaul, low-jitter, scheduling, quality of service, wireless mesh network, TDMA, OFDMA, crossbar, relay network, input-queue
17	Tezaswi Raja, Samiha Mourad	Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial.	DELTA	2010	DBLP DOI BibTeX RDF	memristor, crossbar, logical implication