Search results for "decoder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Darren Moore, John Dines, Mathew Magimai-Doss, Jithendra Vepa, Octavian Cheng, Thomas Hain	Juicer: A Weighted Finite-State Transducer Speech Decoder.	MLMI	2006	DBLP DOI BibTeX RDF
31	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	Area-efficient high-throughput MAP decoder architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
31	Jong Hun Han, Ahmet T. Erdogan, Tughrul Arslan	High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization.	ISVLSI	2005	DBLP DOI BibTeX RDF
31	Hugo Hedberg, Thomas Lenart, Henrik Svensson	A Complete MP3 Decoder on a Chip.	MSE	2005	DBLP DOI BibTeX RDF
31	Seung Wook Lee, Jong Tae Kim, Jae Sang Cha	Implementation of Adaptive Reed-Solomon Decoder for Context-Aware Mobile Computing Device.	KES (1)	2005	DBLP DOI BibTeX RDF
31	G. Provost, Marc-André Cantin, Mohamad Sawan, Christian Cardinal, Yvon Savaria, David Haccoun	Fast parameters optimization of an iterative decoder using a configurable hardware accelerator.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
31	Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang	A new low-power turbo decoder using HDA-DHDD stopping iteration.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
31	Yongtao Wang, Kaushik Roy 0001	A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
31	Indrajit Atluri, Tughrul Arslan	Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation.	ISVLSI	2004	DBLP DOI BibTeX RDF
31	Kalle Ruttik	BER for CMOS Analog Decoder with Different Working Points.	ICT	2004	DBLP DOI BibTeX RDF
31	Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari	An Asynchronous Viterbi Decoder for Low-Power Applications.	PATMOS	2003	DBLP DOI BibTeX RDF
31	Arezou Koohi, Nader Bagherzadeh, Chengzi Pan	A fast parallel reed-solomon decoder on a reconfigurable architecture.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	Berlekamp algorithm, Chein search, reconfigurable architecture, Reed-Solomon codes, SIMD processor
31	Wai-Chi Fang, Anand Sethuraman, K. Belevi	VLSI design of turbo decoder for integrated communication system-on-chip applications.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
31	Mohammad M. Mansour, Naresh R. Shanbhag	Low-power VLSI decoder architectures for LDPC codes.	ISLPED	2002	DBLP DOI BibTeX RDF	BCJR algorithm, lower power architectures, LDPC codes
31	Takehiro Kamada, Toshihiko Fukuoka, Yuji Nakai, Yoshihiko Fukumoto, Yasuhiro Nakakura, Katsuhiko Ueda, Tomonori Shiomi, Kazuhiro Ota	An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
31	Xiaoguang Dai, S. W. Cheung, T. I. Yuk	Simplified ordering for fixed-complexity sphere decoder.	IWCMC	2010	DBLP DOI BibTeX RDF	fixed-complexity sphere decoder, MIMO, ordering, geometrical analysis
31	Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont	Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW
31	Hazem Moussa, Amer Baghdadi, Michel Jézéquel	Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.	DAC	2008	DBLP DOI BibTeX RDF	flexible LDPC decoder, multiprocessor, NoC, de Bruijn graph
31	Egor Bondarev, Michel R. V. Chaudron, Erwin A. de Kock	Exploring performance trade-offs of a JPEG decoder using the deepcompass framework.	WOSP	2007	DBLP DOI BibTeX RDF	JPEG decoder, design trade-offs, simulation, software, performance prediction, system architecture, component-based systems, component models, model synthesis
31	Vaidyanathan Ramadurai, Sanjay Jinturkar, Mayan Moudgill, John Glossner	Implementation of H.264 decoder on Sandblaster DSP.	ICME	2005	DBLP DOI BibTeX RDF	H.264-AVC baseline profile decoder, Sandblaster digital signal processor, ANSI C, DSP, optimization technique, software implementation
31	Anand Selvarathinam, Euncheol Kim, Gwan Choi	Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels.	ICCD	2003	DBLP DOI BibTeX RDF	LDPC Decoder, Serial Architecture, Hardware Scaling, VLSI, Parallel Architecture, Fibre Channel
31	Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa, Ichiro Kuroda	MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	microprocessor, decoder, MPEG, AAC
31	V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed	A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.	ASAP	2000	DBLP DOI BibTeX RDF	disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations
31	Joep L. W. Kessels	VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
28	Ruixing Yang, Lachlan Pockett, Jari Nurmi	Realization of Free Viewpoint TV Based on Improved MVC.	FMN	2009	DBLP DOI BibTeX RDF	FTV, BE-MVC, free view, MVC, multi-view
28	Yongmei Dai, Zhiyuan Yan 0001, Ning Chen 0004	Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
28	Arun Avudainayagam, John M. Shea, Dapeng Wu 0001	Hyper-Trellis Decoding of Pixel-Domain Wyner-Ziv Video Coding.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
28	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
28	Venkat Chandar, Aslan Tchamkerten, Gregory W. Wornell	Optimal Sequential Frame Synchronization.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
28	Jittra Jootar, James R. Zeidler, John G. Proakis	On the performance of concatenated convolutional code and Alamouti space-time code with noisy channel estimates and finite-depth interleaving.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
28	David M. Chen, David P. Varodayan, Markus Flierl, Bernd Girod	Distributed stereo image coding with improved disparity and noise estimation.	ICASSP	2008	DBLP DOI BibTeX RDF
28	Wei Shao, Linda E. M. Brackenbury	Pre-processing of convolutional codes for reducing decoding power consumption.	ICASSP	2008	DBLP DOI BibTeX RDF
28	Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li	Power reduction via macroblock prioritization for power aware H.264 video applications.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	low power, video, h.264, voltage scaling, power aware, mpeg4, frequency scaling
28	Ofer Amrani	Nonlinear Codes: The Product Construction.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
28	Hossein R. Sarrafzadeh	State Transparent Convolutional Codes and Their Novel Maximum-Likelihood Decoding Algorithm.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
28	Yuping Zhang, Keshab K. Parhi	Parallel Architecture of List Sphere Decoders.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Pei Xiao, Erik G. Ström	Correction of extrinsic information for iterative decoding in a serially concatenated multiuser DS-CDMA system.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
28	Chang-Hong Fu 0002, Yui-Lam Chan, Wan-Chi Siu	Efficient reverse-play algorithms for MPEG video with VCR support.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
28	John MacLaren Walsh, Phillip A. Regalia, C. Richard Johnson Jr.	Turbo Decoding as Iterative Constrained Maximum-Likelihood Sequence Detection.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
28	W. A. Rajitha Jayaruwan Weerakkody, Warnakulasuriya Anil Chandana Fernando, A. B. B. Adikari	Distributed Video Coding of Wyner-Ziv Frames using Trellis Coded Modulation.	CCECE	2006	DBLP DOI BibTeX RDF
28	Marc André Armand	Improved list decoding of generalized Reed-Solomon and alternant codes over Galois rings.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
28	João Ascenso, Catarina Brites, Fernando Pereira 0001	Motion compensated refinement for low complexity pixel based distributed video coding.	AVSS	2005	DBLP DOI BibTeX RDF
28	Min Wu 0007, Anthony Vetro, Jonathan S. Yedidia, Huifang Sun, Chang Wen Chen	A study of encoding and decoding techniques for syndrome-based video coding.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
28	Yu-jhih Wu, Michael D. Alston, Paul M. Chau	Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
27	Zihao Fu, Wai Lam, Qian Yu, Anthony Man-Cho So, Shengding Hu, Zhiyuan Liu 0010, Nigel Collier	Decoder-Only or Encoder-Decoder? Interpreting Language Model as a Regularized Encoder-Decoder.	CoRR	2023	DBLP DOI BibTeX RDF
27	Pramote Jangisarakul, Chalie Charoenlarpnopparut	Algebraic decoder of multidimensional convolutional code: constructive algorithms for determining syndrome decoder and decoder matrix based on Gröbner basis.	Multidimens. Syst. Signal Process.	2011	DBLP DOI BibTeX RDF
27	Chanyang Joo, Soojae Kim, Kwangsub Yoon	A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	binary decoder, pseudo-segmentation, swing reduced driver, low power, DAC
27	Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu	Decomposition of instruction decoders for low-power designs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction decoder, Low power
27	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	Energy Efficient VLSI Architecture for Linear Turbo Equalizer.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	iterative equalizer, SISO, turbo, architecture, low-power, iterative decoder
27	Saied Hemati, Amir H. Banihashemi	Iterative decoding in analog CMOS.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	analog CMOS, analog iterative decoder, asynchronous iterative decoding, min-sum decoding, soft decoding, analog circuit, turbo codes, iterative decoding, low-density parity-check codes
27	Lance C. Pérez, Chen Xia	Iterative detection of a CFSK system.	Richard Tapia Celebration of Diversity in Computing Conference	2003	DBLP DOI BibTeX RDF	collision frequency shift keying, consensus decoder, iterative detection
27	Gary E. Kopec, Philip A. Chou	Document Image Decoding Using Markov Source Models.	IEEE Trans. Pattern Anal. Mach. Intell.	1994	DBLP DOI BibTeX RDF	document image decoding, Markov source models, document image recognition, stochastic finite state automaton, message source, 1D message string, 2D bitmap, Viterbi-like dynamic programming, dynamic programming, hidden Markov models, image coding, decoder, document image processing, channel models, communication theory, finite state model
26	Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam	Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.	VLSI Design	2009	DBLP DOI BibTeX RDF
26	Marleen Morbée, Antoni Roca 0002, Josep Prades-Nebot, Aleksandra Pizurica, Wilfried Philips	Reduced decoder complexity and latency in pixel-domain Wyner-Ziv video coders.	Signal Image Video Process.	2008	DBLP DOI BibTeX RDF	Feedback channel, Rate allocation, Distributed video coding, Wyner-Ziv coding
26	Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang	A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder.	IEEE Trans. Multim.	2008	DBLP DOI BibTeX RDF
26	Marco Grangetto, Enrico Magli, Gabriella Olmo	Decoder-driven adaptive distributed arithmetic coding.	ICIP	2008	DBLP DOI BibTeX RDF
26	Matteo Naccari, Marco Tagliasacchi, Fernando Pereira 0001, Stefano Tubaro	No-reference modeling of the channel induced distortion at the decoder for H.264/AVC video coding.	ICIP	2008	DBLP DOI BibTeX RDF
26	Wenjun Wang, Xiaoguang Wu, Xiaoxuan Zhu, Guixia Kang, Xiaofeng Tao	A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder.	VTC Spring	2008	DBLP DOI BibTeX RDF
26	Hongzhi Wang 0003, Pierre Leray, Jacques Palicot	An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management.	ICC	2008	DBLP DOI BibTeX RDF
26	Ji-Hoon Kim, In-Cheol Park	Duo-binary circular turbo decoder based on border metric encoding for WiMAX.	ASP-DAC	2008	DBLP DOI BibTeX RDF
26	Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta	A highly parallel Turbo Product Code decoder without interleaving resource.	SiPS	2008	DBLP DOI BibTeX RDF
26	Luis G. Barbero, Tharmalingam Ratnarajah, Colin Cowan	A low-complexity soft-MIMO detector based on the fixed-complexity sphere decoder.	ICASSP	2008	DBLP DOI BibTeX RDF
26	David A. Bader, Sulabh Patel	High performance MPEG-2 software decoder on the cell broadband engine.	IPDPS	2008	DBLP DOI BibTeX RDF
26	Yong-Je Goo, Hanho Lee	Two bit-level pipelined viterbi decoder for high-performance UWB applications.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Liwei Guo, Oscar C. Au, Mengyao Ma, Peter H. W. Wong	Video decoder embedded with temporal LMMSE denoising filter.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Sangmin Kim, Gerald E. Sobelman, Hanho Lee	Adaptive quantization in min-sum based irregular LDPC decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Yang Sun 0001, Yuming Zhu, Manish Goel, Joseph R. Cavallaro	Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards.	ASAP	2008	DBLP DOI BibTeX RDF
26	Ahmed S. Hadi	Linear block code decoder using neural network.	IJCNN	2008	DBLP DOI BibTeX RDF
26	Zhongfeng Wang 0001, Zhiqiang Cui	Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Zhongfeng Wang 0001, Zhiqiang Cui	A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Jie Jin, Chi-Ying Tsui	Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Myoung-Cheol Shin, In-Cheol Park	SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Tsu-Ming Liu, Sheng-Zen Wang, Bai-Jue Shieh, Chen-Yi Lee	A New Soft Variable Length Decoder for Wireless Video Transmission.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
26	Tom Clerckx, Adrian Munteanu 0001, Jan Cornelis 0001, Peter Schelkens	Distributed Video Coding with Shared Encoder/Decoder Complexity.	ICIP (6)	2007	DBLP DOI BibTeX RDF
26	Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci	A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
26	Chanho Yoon, Jong-Ee Oh, Minho Cheong, Sok-Kyu Lee	A Hardware Efficient LDPC Encoding Scheme for Exploiting Decoder Structure and Resources.	VTC Spring	2007	DBLP DOI BibTeX RDF
26	Imran Ahmed 0001, Tughrul Arslan	VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond.	ASP-DAC	2007	DBLP DOI BibTeX RDF
26	Haisheng Liu, Jean-Philippe Diguet, Christophe Jégo, Michel Jézéquel, Emmanuel Boutillon	Energy Efficient Turbo Decoder with Reduced State Metric Quantization.	SiPS	2007	DBLP DOI BibTeX RDF
26	Hongzhi Wang 0003, Jean-Philippe Delahaye, Pierre Leray, Jacques Palicot	Managing dynamic reconfiguration on MIMO Decoder.	IPDPS	2007	DBLP DOI BibTeX RDF
26	Luigi Cinque, Sergio De Agostino	A Parallel Decoder for Lossless Image Compression by Block Matching.	DCC	2007	DBLP DOI BibTeX RDF
26	Shanq-Jang Ruan, Wei-Te Lin	Bipartition Architecture for Low Power JPEG Huffman Decoder.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Low power, Decoding, Bipartition, Huffman
26	Wen-Ta Lee, Hsin-Jung Chen, Yuh-Shyan Hwang, Jiann-Jong Chen	Joint Source-Channel Decoder for H.264 Coded Video Employing Fuzzy Adaptive Method.	ICME	2007	DBLP DOI BibTeX RDF
26	Mohamed Kawokgy, C. André T. Salama	A low-power CSCD asynchronous viterbi decoder for wireless applications.	ISLPED	2007	DBLP DOI BibTeX RDF	current sensing completion detection, low-power, synchronous, wireless, digital signal processing, asynchronous, viterbi, handshaking
26	Yang Sun 0001, Marjan Karkooti, Joseph R. Cavallaro	VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Ji-Hoon Kim, In-Cheol Park	Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Guichang Zhong, Alan N. Willson Jr.	An Energy-efficient Reconfigurable Viterbi Decoder on a Programmable Multiprocessor.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Ke Zhang, Xiaoyang Wu 0001, Lu Yu 0003	An Area-efficient VLSI Implementation of CA-2D-VLC Decoder for AVS.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Yongru Gu, Keshab K. Parhi	Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	trellis coded modulation, 10 Gigabit ethernet, interleaving, high speed, complexity reduction
26	Tsuguo Maru	High Performance Simplified LDPC Decoder without Knowledge of Multi-path Rayleigh Channel.	VTC Spring	2006	DBLP DOI BibTeX RDF
26	Joon-Sung Kim, Hong-Yeop Song	Concatenated LDGM Codes with Reduced Decoder Complexity.	VTC Spring	2006	DBLP DOI BibTeX RDF
26	Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto	High-throughput decoder for low-density parity-check code.	ASP-DAC	2006	DBLP DOI BibTeX RDF
26	Paul Saunders, Anthony D. Fagan	A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes.	FPL	2006	DBLP DOI BibTeX RDF
26	Hongzhi Wang 0003, Pierre Leray, Jacques Palicot	A Reconfigurable Architecture for MIMO Square Root Decoder.	ARC	2006	DBLP DOI BibTeX RDF
26	Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, Tiberiu Seceleanu	Complexity Analysis of H.264 Decoder for FPGA Design.	ICME	2006	DBLP DOI BibTeX RDF
26	Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra	Programmable LDPC Decoder Based on the Bubble-Sort Algorithm.	VLSI Design	2006	DBLP DOI BibTeX RDF
26	Kun Yang, Chun Zhang, Zhihua Wang 0001	Design of Adaptive Deblocking Filter for H.264/AVC Decoder SOC.	APCCAS	2006	DBLP DOI BibTeX RDF
26	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto	Memory-Efficient Accelerating Schedule for LDPC Decoder.	APCCAS	2006	DBLP DOI BibTeX RDF
26	Anh Dinh, Xiao Hu	A hardware-efficient technique to implement a trellis code modulation decoder.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
26	Tsung-Han Tsai 0001, Ya-Chau Yang, Chun-Nan Liu	A Hardware/Software Co-Design of MP3 Audio Decoder.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	IMDCT, Filterbank, VLSI, DSP, ASIC, MPEG, Co-Design, MP3
26	Indrajit Atluri, Ashwin K. Kumaraswamy	Energy Efficient Architectures for the Log-MAP Decoder through Intelligent Memory Usage.	ISVLSI	2005	DBLP DOI BibTeX RDF