Search results for "fanout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Evrim Guler, Danyang Zheng, Guangchun Luo, Ling Tian, Xiaojun Cao	Embedding Multicast Services in Optical Networks with Fanout Limitation.	ICC	2018	DBLP DOI BibTeX RDF
23	Naveen Katam, Alireza Shafaei, Massoud Pedram	Design of multiple fanout clock distribution network for rapid single flux quantum technology.	ASP-DAC	2017	DBLP DOI BibTeX RDF
23	Shivangi Surati, Devesh C. Jinwala, Sanjay Garg	Evaluating the impact of fanout and dimension on the performance of a hybrid model for multidimensional indexing in peer-to-peer m-ary tree network.	Int. J. Commun. Networks Distributed Syst.	2015	DBLP DOI BibTeX RDF
23	Krzysztof Walkowiak, Róza Goscien, Massimo Tornatore, Michal Wozniak 0001	Impact of fanout and transmission reach on performance of multicasting in Elastic Optical Networks.	OFC	2015	DBLP DOI BibTeX RDF
23	Mehrdad Najibi, Peter A. Beerel	Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits.	ASYNC	2014	DBLP DOI BibTeX RDF
23	Siddhartha 0001, Nachiket Kapre	Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization.	FPT	2014	DBLP DOI BibTeX RDF
23	Kyungmin Kim, Seokhwan Kong, Jaiyong Lee	Fanout Set Partition Scheme for QoS-Guaranteed Multicast Transmission.	IEICE Trans. Commun.	2013	DBLP DOI BibTeX RDF
23	Kyungmin Kim, Jaiyong Lee	Topology-aware fanout set division scheme for QoS-guaranteed multicast transmission.	J. Commun. Networks	2013	DBLP DOI BibTeX RDF
23	Samuel N. Pagliarini, Tian Ban, Lirida A. B. Naviner, Jean-François Naviner	Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis.	MWSCAS	2013	DBLP DOI BibTeX RDF
23	Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis 0001	Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.	ISCAS	2013	DBLP DOI BibTeX RDF
23	Jonathan Lifflander, Phil Miller, Laxmikant V. Kalé	Adoption protocols for fanout-optimal fault-tolerant termination detection.	PPoPP	2013	DBLP DOI BibTeX RDF
23	Alessandro Murgia, Roberto Tonelli, Steve Counsell, Giulio Concas, Michele Marchesi	An Empirical Study of Refactoring in the Context of FanIn and FanOut Coupling.	WCRE	2011	DBLP DOI BibTeX RDF
23	Xun Chen, Jianwen Zhu, Minxuan Zhang	Timing-Driven Routing of High Fanout Nets.	FPL	2011	DBLP DOI BibTeX RDF
23	Daniel Bernhard Fasnacht, Giacomo Indiveri	A PCI based high-fanout AER mapper with 2 GiB RAM look-up table, 0.8 µs latency and 66MHz output event-rate.	CISS	2011	DBLP DOI BibTeX RDF
23	Abhijit R. Asati, Subhendu Kumar Sahoo, Chandra Shekhar 0001	Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load.	ICETET	2009	DBLP DOI BibTeX RDF
23	Cedric Fortuny, Olivier Brun, Jean-Marie Garcia	Fanout Inference from Link Count.	ECUMN	2007	DBLP DOI BibTeX RDF
23	M. Fang, Stephen A. Fenner, Frederic Green, Steven Homer, Yong Zhang 0053	Quantum lower bounds for fanout.	Quantum Inf. Comput.	2006	DBLP DOI BibTeX RDF
23	Koji Yamazaki, Yuzo Takamatsu	Fanout-based fault diagnosis for open faults on pass/fail information.	ATS	2006	DBLP DOI BibTeX RDF
23	Keshab K. Parhi	Eliminating the fanout bottleneck in parallel long BCH encoders.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
23	Keshab K. Parhi	Eliminating the fanout bottleneck in parallel long BCH encoders.	ICC	2004	DBLP DOI BibTeX RDF
23	Anand Pappu, Alyssa B. Apsel	Electrical isolation and fanout in intra-chip optical interconnects.	ISCAS (2)	2004	DBLP BibTeX RDF
23	Frederic Green, Steven Homer, Cristopher Moore, Christopher Pollett	Counting, fanout and the complexity of quantum ACC.	Quantum Inf. Comput.	2002	DBLP DOI BibTeX RDF
23	Geun Rae Cho, Tom Chen 0001	On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis.	IWLS	2002	DBLP BibTeX RDF
23	Tomás Feder	Fanout limitations on constraint systems.	Theor. Comput. Sci.	2001	DBLP DOI BibTeX RDF
23	Wei Chen, Cheng-Ta Hsieh, Massoud Pedram	Simultaneous Gate Sizing and Fanout Optimization.	ICCAD	2000	DBLP DOI BibTeX RDF
23	Cristopher Moore	Quantum Circuits: Fanout, Parity, and Counting	Electron. Colloquium Comput. Complex.	1999	DBLP BibTeX RDF
23	Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Hamid Savoj	LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay.	ICCAD	1999	DBLP DOI BibTeX RDF
23	Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni	Fanout optimization under a submicron transistor-level delay model.	ICCAD	1998	DBLP DOI BibTeX RDF
23	Amir H. Salek, Jinan Lou, Massoud Pedram	A simultaneous routing tree construction and fanout optimization algorithm.	ICCAD	1998	DBLP DOI BibTeX RDF
23	Y. L. Jae, Chong Kwan Un	Performance Analysis of Two Fanout Splitting Schemes for a Multicast Packet Switch With Capacity M.	Perform. Evaluation	1997	DBLP DOI BibTeX RDF
23	Chun-Fai Chan, Chin-Tau Lea	Constructing nonblocking multicast switching networks with fanout reduction.	Advances in Switching Networks	1997	DBLP DOI BibTeX RDF
23	Chuan-Heng Ang, Hanan Samet	Approximate Average Storage Utilization of Bucket Methods with Arbitrary Fanout.	Nord. J. Comput.	1996	DBLP BibTeX RDF
23	T. Aoki, Masami Murakata, Takashi Mitsuhashi, Nobuyuki Goto	Fanout-tree restructuring algorithm for post-placement timing optimization.	ASP-DAC	1995	DBLP DOI BibTeX RDF
23	Antonio Lioy	On the Equivalence of Fanout-Point Faults.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF
23	K. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati	A simple algorithm for fanout optimization using high-performance buffer libraries.	ICCAD	1993	DBLP DOI BibTeX RDF
23	Hirendu Vaishnav, Massoud Pedram	Routability-Driven Fanout Optimization.	DAC	1993	DBLP DOI BibTeX RDF
23	Yehoshua Sagiv, Yatin P. Saraiya	Minimizing Restricted-Fanout Queries.	Discret. Appl. Math.	1992	DBLP DOI BibTeX RDF
23	Xinli Gu, Krzysztof Kuchcinski, Zebo Peng	Testability measure with reconvergent fanout analysis and its applications.	Microprocessing and Microprogramming	1991	DBLP DOI BibTeX RDF
23	Shen Lin 0001, Malgorzata Marek-Sadowska	A fast and efficient algorithm for determining fanout trees in large networks.	EURO-DAC	1991	DBLP BibTeX RDF
23	Pramod Koparkar	Parametric blending using fanout surfaces.	Symposium on Solid Modeling and Applications	1991	DBLP DOI BibTeX RDF
23	Hyoung B. Min, William A. Rogers, Hwei-Tsu Ann Luh	FANHAT: fanout oriented hierarchical automatic test generation system.	ICCAD	1989	DBLP DOI BibTeX RDF
23	Fadi Maamari, Janusz Rajski	A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits.	FTCS	1988	DBLP DOI BibTeX RDF
23	Ki Soo Hwang, M. Ray Mercer	Informed Test Generation Guidance Using Partially Specified Fanout Constraints.	ITC	1986	DBLP BibTeX RDF
23	Edward A. Bender	The Number of Fanout-Free Functions with Various Gates.	J. ACM	1980	DBLP DOI BibTeX RDF
23	George Markowsky	Diagnosing Single Faults in Fanout-Free Combinational Circuits.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF
23	Jon T. Butler	Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates.	J. ACM	1978	DBLP DOI BibTeX RDF
23	John P. Hayes	The Fanout Structure of Switching Functions.	J. ACM	1975	DBLP DOI BibTeX RDF
23	John P. Hayes	Minimization of Fanout in Switching Networks	SWAT	1974	DBLP DOI BibTeX RDF
23	Israel Berger, Zvi Kohavi	Fault Detection in Fanout-Free Combinational Networks.	IEEE Trans. Computers	1973	DBLP DOI BibTeX RDF
19	Anand Agarawala, Ravin Balakrishnan	Keepin' it real: pushing the desktop metaphor with physics, piles and the pen.	CHI	2006	DBLP DOI BibTeX RDF	Lasso'n'Cross, LassoMenu, bumptop, crumple, physics based desktop, pile widgets, piles, piling metaphor, pen-based interfaces, physical interaction, fanout, desktop metaphor
19	Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
19	Jason Cong, Patrick H. Madden	Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
19	Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen	Timing and Crosstalk Driven Area Routing.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
19	John Lillis, Premal Buch	Table-Lookup Methods for Improved Performance-Driven Routing.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
19	Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao	General AC Constraint Transformation for Analog ICs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
19	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer Insertion for Noise and Delay Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
19	Hai Zhou 0001, D. F. Wong 0001	Global Routing with Crosstalk Constraints.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
19	Arun N. Lokanathan, Jay B. Brockman	Process Multi-Circuit Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
19	Oliver Chiu-sing Choy, Lap-kong Chan, Ray Chan, Cheong-Fat Chan	Test Generation with Dynamic Probe Points in High Observability Testing Environment.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	critical path tracing method, E-beam testing, fanout free combinational circuit, wafer stage testing, Automatic test pattern generation
19	Tapan J. Chakraborty, Vishwani D. Agrawal	Design for high-speed testability of stuck-at faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
19	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders
19	Irith Pomeranz, Zvi Kohavi	Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	polynomial complexity algorithms, testing-module insertion, test set merging, fanout free circuits, computational complexity, logic testing, partitioning, combinational circuits, logic CAD, testability, digital circuits, combinatorial circuits, single stuck-at faults, test generation algorithm, placement algorithm
19	Vinod K. Agarwal, Gerald M. Masson	Recursive Coverage Projection of Test Sets.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	recursive projection, internal fanout-free networks, Consistency, fault detection, coverage, multiple faults
19	Israel Koren, Zvi Kohavi	On the Properties of Sensitized Paths.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	unsensitized propagating line, Backward tracing, reconvergent fanout line, sensitized path, combinational network
12	Hua Xiang 0001, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho	Logical and physical restructuring of fan-in trees.	ISPD	2010	DBLP DOI BibTeX RDF	symmetric-function fan-in tree, restructure, commutative
12	Xiangye Xiao, Qiong Luo 0001, Dan Hong, Hongbo Fu 0001, Xing Xie 0001, Wei-Ying Ma	Browsing on small displays by transforming Web pages into hierarchically structured subpages.	ACM Trans. Web	2009	DBLP DOI BibTeX RDF	Web page adaptation, slicing tree, Proxy, Web browsing, small displays, thumbnails
12	Martín Casado, Michael J. Freedman, Justin Pettit, Jianying Luo, Natasha Gude, Nick McKeown, Scott Shenker	Rethinking enterprise network control.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	security, architecture, network, management
12	Liang-Kai Wang, Michael J. Schulte, John D. Thompson, Nandini Jairam	Hardware Designs for Decimal Floating-Point Addition and Related Operations.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
12	Xiao-dong Sun, Hong-Bin Zhang	A Fast Hole-filling Strategy of 3D Scanned Human Body.	CGIV	2009	DBLP DOI BibTeX RDF
12	Davide Frey, Rachid Guerraoui, Anne-Marie Kermarrec, Boris Koldehofe, Martin Mogensen, Maxime Monod, Vivien Quéma	Heterogeneous Gossip.	Middleware	2009	DBLP DOI BibTeX RDF
12	Feng Yuan, Qiang Xu 0001	On systematic illegal state identification for pseudo-functional testing.	DAC	2009	DBLP DOI BibTeX RDF	illegal states, pseudo-functional testing
12	Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri	SAT-based ATPG using multilevel compatible don't-cares.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Boolean satisfiabilty (SAT), testing, Automatic test pattern generation (ATPG), don't cares
12	Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes	Probabilistic transfer matrices in symbolic reliability analysis of logic circuits.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	fault tolerance, Symbolic analysis
12	Can Emre Koksal	On the Speedup Required to Achieve 100% Throughput for Multicast Over Crossbar Switches.	IWQoS	2008	DBLP DOI BibTeX RDF
12	Ramakrishna Garudadri, Krishna Kant 0002	A Hybrid Resource Information Dissemination Protocol for dynamic Grids.	ICON	2008	DBLP DOI BibTeX RDF
12	Xiaopeng Fan, Jiannong Cao 0001, Weigang Wu, Michel Raynal	On Modeling Fault Tolerance of Gossip-Based Reliable Multicast Protocols.	ICPP	2008	DBLP DOI BibTeX RDF
12	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.	VLSI Design	2008	DBLP DOI BibTeX RDF
12	Jiro Inoue, A. James Stewart	Multiresolution sphere packing tree: a hierarchical multiresolution 3D data structure.	Symposium on Solid and Physical Modeling	2008	DBLP DOI BibTeX RDF	MSP-tree, sphere packing, multiresolution, selective refinement
12	Panfeng Zhou, Betty Salzberg	The hB-pi* Tree: An Optimized Comprehensive Access Method for Frequent-Update Multi-dimensional Point Data.	SSDBM	2008	DBLP DOI BibTeX RDF	hB-pi* tree, Empty space, Multi-dimension access method
12	Wang-Dauh Tseng	Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	transition density, switching activity during test, clique, low power testing, full scan
12	Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur	Reversible circuit technology mapping from non-reversible specifications.	DATE	2007	DBLP DOI BibTeX RDF
12	Nikhil Jayakumar, Sunil P. Khatri	An algorithm to minimize leakage through simultaneous input vector control and circuit modification.	DATE	2007	DBLP DOI BibTeX RDF
12	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.	ETS	2007	DBLP DOI BibTeX RDF
12	Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	signal slope, interconnect, gate delay, subthreshold operation
12	Hugo Cheung, Sandeep K. Gupta	Accurate modeling and fault simulation of Byzantine resistive bridges.	ICCD	2007	DBLP DOI BibTeX RDF
12	Sheng Sun, Carl Sechen	Post-layout comparison of high performance 64b static adders in energy-delay space.	ICCD	2007	DBLP DOI BibTeX RDF
12	Kambiz Rahimi	Minimizing peak power in synchronous logic circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power optimization, peak power, clock scheduling
12	Youngsoo Shin, Hyung-Ock Kim	Cell-Based Semicustom Design of Zigzag Power Gating Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
12	Guy Even, Tamir Levi, Ami Litman	Optimal Conclusive Sets for Comparator Networks.	SIROCCO	2007	DBLP DOI BibTeX RDF	Zero-One Principle, Merging Networks, Sorting Networks, Comparator Networks, Bitonic Sorting
12	Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer	Top-k Aggressors Sets in Delay Noise Analysis.	DAC	2007	DBLP DOI BibTeX RDF
12	Audhild Vaaje	Theorems for Fault Collapsing in Combinational Circuits.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	Boolean function, combinational circuit, monotonic function, fault collapsing
12	Chi-Shong Wang, Chingwei Yeh	Performance-driven technology mapping with MSG partition and selective gate duplication.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	gate duplication, maximal super-gate, super-gate, dynamic programming, partition, matching, logic synthesis, directed acyclic graph, Technology mapping, covering
12	Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley	Dataflow Predication.	MICRO	2006	DBLP DOI BibTeX RDF
12	Jun Wang, Carl Tropper	Compiled code in distributed logic simulation.	WSC	2006	DBLP DOI BibTeX RDF
12	Jeroen A. J. Leijten, Menno Lindwer	Multiprocessing Template for Media Applications.	ISM	2006	DBLP DOI BibTeX RDF
12	Hosung (Leo) Kim, John Lillis, Milos Hrkic	Techniques for improved placement-coupled logic replication.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
12	Avijit Dutta, Nur A. Touba	Synthesis of Efficient Linear Test Pattern Generators.	DFT	2006	DBLP DOI BibTeX RDF
12	Miguel Eduardo Litvin, Samiha Mourad	Self-reset logic for fast arithmetic applications.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Giorgos Dimitrakopoulos, Dimitris Nikolos	High-Speed Parallel-Prefix VLSI Ling Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	parallel-prefix carry computation, computer arithmetic, VLSI design, Adders
12	Saravanan Padmanaban, Spyros Tragoudas	Efficient identification of (critical) testable path delay faults using decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF