Search results for "feedthrough"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee	A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Mark S. Hancock, John David Miller, Saul Greenberg, Sheelagh Carpendale	Exploring visual feedback of change conflict in a distributed 3D environment.	AVI	2006	DBLP DOI BibTeX RDF	change conflict, synchronous, asynchronous, distributed collaboration, visual feedback, divergence
18	Jiri Haze, Lukas Fujcik, Ondrej Sajdl, Radimir Vrba	Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
18	Bo Fu, Paul Ampadu	Techniques for robust energy efficient subthreshold domino CMOS circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Weining Ni, Xueyang Geng, Yin Shi, Foster F. Dai	A 12-bit 300 MHz CMOS DAC for high-speed system applications.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Jun-Hong Weng, Chong-Jng Yu, Ching-Yuan Yang, Peng-Chang Yang	A low-noise microsensor amplifier with automatic gain control system.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Honghao Ji, Pamela Abshire	A CMOS image sensor for low light applications.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Jiri Haze, Radimir Vrba	The New Low Power 10-bit Pipelined ADC Using Novel Background Calibration Technique.	DELTA	2006	DBLP DOI BibTeX RDF
18	Guo-Ming Sung, Kuo-Hsuan Chang, Wen-Sheng Lin	A 12-B 10-msamples/s CMOS switched-current delta-sigma modulator.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
18	Angelo Nagari, Germano Nicollini	A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs.	DATE	2004	DBLP DOI BibTeX RDF
18	Yu-Chuan Shih, Chung-Yu Wu	An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Gang Xu, Jiren Yuan	Performance analysis of general charge sampling.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Yiwu Tang, Mohammed Ismail 0001, Steven Bibyk	A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
18	Debapriya Sahu	A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
18	Jader A. De Lima, Antonio Petraglia	On designing OTA-C graphic-equalizers with MOSFET-triode transconductors.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
18	Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois	Design of self-checking fully differential circuits and boards.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
18	Massoud Pedram, Bryan Preas	Interconnection analysis for standard cell layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
18	Andrew E. J. Ng, John I. Sewell	Pseudo-N-path cells for switched-current signal processing.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
18	S. Karthikeyan, A. Tammineedi, C. Boecker, Edward K. F. Lee	A 1 V front-end interface for switched-op amp circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
18	Haluk Konuk, F. Joel Ferguson, Tracy Larrabee	Charge-based fault simulation for CMOS network breaks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou	A power modeling and characterization method for the CMOS standard cell library.	ICCAD	1996	DBLP DOI BibTeX RDF	power characterization, power consumption, power estimation
18	Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen	A cell-based power estimation in CMOS combinational circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
18	Tom Chanak, Rakesh Chadha, Kishore Singhal	Switched-capacitor simulation models for full-chips verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
18	Gregory T. Brauns, R. J. Bishop, Michael Steer, John J. Paulos, Sasan H. Ardalan	Table-based modeling of delta-sigma modulators using ZSIM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
18	Hwan Gue Cho, C. M. Kyung	A heuristic standard cell placement algorithm using constrained multistage graph model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF