Search results for "floorplan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden	Floorplan management: incremental placement for gate sizing and buffer insertion.	ASP-DAC	2005	DBLP DOI BibTeX RDF
29	Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho	Placement constraints in floorplan design.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
29	Chris C. N. Chu, Evangeline F. Y. Young	Nonrectangular shaping and sizing of soft modules for floorplan-design improvement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
29	Thomas Brandtner, Robert Weigel	SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level.	DATE	2004	DBLP DOI BibTeX RDF
29	Johan Berntsson, Maolin Tang	A Slicing Structure Representation for the Multi-layer Floorplan Layout Problem.	EvoWorkshops	2004	DBLP DOI BibTeX RDF
29	Kun Gao, Dinesh P. Mehta	Floorplan Classification Algorithms.	VLSI Design	2004	DBLP DOI BibTeX RDF
29	Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske	Graph-based approach to evaluate net routability of a floorplan.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
29	Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho	A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	placement constraint, physical design, floorplanning
29	Koji Ohashi, Mineo Kaneko, Satoshi Tayu	Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis.	ICCD	2000	DBLP DOI BibTeX RDF
29	Pinghong Chen, Ernest S. Kuh	Floorplan sizing by linear programming approximation.	DAC	2000	DBLP DOI BibTeX RDF
29	Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong	Relaxed Simulated Tempering for VLSI Floorplan Designs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
29	Temo Chen, Michael K. H. Fan	On convex formulation of the floorplan area minimization problem.	ISPD	1998	DBLP DOI BibTeX RDF
29	Maurizio Rebaudengo, Matteo Sonza Reorda	GALLO: a genetic algorithm for floorplan area optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
29	Ting-Chi Wang, Martin D. F. Wong	Optimal floorplan area optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
29	Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen	An analytical approach to floorplan design and optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
29	Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen	An Analytical Approach to Floorplan Design and Optimization.	DAC	1990	DBLP DOI BibTeX RDF
29	Ting-Chi Wang, D. F. Wong 0001	An Optimal Algorithm for Floorplan Area Optimization.	DAC	1990	DBLP DOI BibTeX RDF
29	E. F. M. Kouka, Gabriele Saucier	An Application of Exploratory Data Analysis Techniques to Floorplan Design.	DAC	1987	DBLP DOI BibTeX RDF
29	D. F. Wong 0001, C. L. Liu 0001	A new algorithm for floorplan design.	DAC	1986	DBLP DOI BibTeX RDF
21	Debasri Saha, Susmita Sur-Kolay	Encoding of Floorplans through Deterministic Perturbation.	VLSI Design	2009	DBLP DOI BibTeX RDF
21	Jing Liu 0006, Weicai Zhong, Licheng Jiao, Xue Li 0001	Moving Block Sequence and Organizational Evolutionary Algorithm for General Floorplanning With Arbitrarily Shaped Rectilinear Blocks.	IEEE Trans. Evol. Comput.	2008	DBLP DOI BibTeX RDF
21	Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou 0001	Optimizing wirelength and routability by searching alternative packings in floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	wirelength reduction, Floorplanning
21	Tilen Ma, Evangeline F. Y. Young	TCG-based multi-bend bus driven floorplanning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
21	Renshen Wang, Evangeline F. Y. Young, Yi Zhu 0002, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng	3-D floorplanning using labeled tree and dual sequences.	ISPD	2008	DBLP DOI BibTeX RDF	3-D packing, sequence, labeled tree
21	Dae Hyun Kim 0004, Sung Kyu Lim	Global bus route optimization with application to microarchitectural design exploration.	ICCD	2008	DBLP DOI BibTeX RDF
21	Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, Li Shang	Reliable multiprocessor system-on-chip synthesis.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	synthesis, multiprocessor system-on-chip, thermal
21	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
21	Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma	A Fast 3D-BSG Algorithm for 3D Packing Problem.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Pritha Banerjee 0001, Susmita Sur-Kolay, Arijit Bishnu	Floorplanning in Modern FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau	Power model validation through thermal measurements.	ISCA	2007	DBLP DOI BibTeX RDF	power and thermal measurements
21	Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy 0001	Layout-driven architecture synthesis for high-speed digital filters.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Love Singhal, Elaheh Bozorgzadeh	Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.	FPL	2006	DBLP DOI BibTeX RDF
21	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design.	FPL	2006	DBLP DOI BibTeX RDF
21	Pilok Lim, Taewhan Kim	Thermal-aware high-level synthesis based on network flow method.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	power consumption, temperature, binding
21	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.	FCCM	2006	DBLP DOI BibTeX RDF
21	Krishnan Srinivasan, Karam S. Chatha	A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures.	ISQED	2006	DBLP DOI BibTeX RDF
21	Jin-Tai Yan, Zhi-Wei Chen, Chia-Wei Wu, Ming-Yuen Wu	Optimal Network Analysis in Hierarchical Power Quad-Grids.	APCCAS	2006	DBLP DOI BibTeX RDF
21	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.	ISQED	2005	DBLP DOI BibTeX RDF
21	Aishwarya Dubey	P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop.	ISQED	2005	DBLP DOI BibTeX RDF	P/G (Power/Ground) pad placement, current sink, package resistance, package inductance, IR drop
21	Meng-Chiou Wu, Rung-Bin Lin	Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers.	ISQED	2005	DBLP DOI BibTeX RDF
21	Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie	A Theoretical Upper Bound for IP-Based Floorplanning.	COCOON	2005	DBLP DOI BibTeX RDF
21	Jai-Ming Lin, Yao-Wen Chang	TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
21	Yi-Hui Cheng, Yao-Wen Chang	Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
21	Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani	Abstraction and optimization of consistent floorplanning with pillar block constraints.	ASP-DAC	2004	DBLP DOI BibTeX RDF
21	Jason Cong, Jie Wei, Yan Zhang	A thermal-driven floorplanning algorithm for 3D ICs.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001	Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.	DAC	2004	DBLP DOI BibTeX RDF	piecewise-linear, performance, pipeline, interconnect, floorplanning
21	Chiu-Wing Sham, Evangeline F. Y. Young	Routability-driven floorplanner with buffer block planning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
21	Jae-Gon Kim, Yeong-Dae Kim	A linear programming-based algorithm for floorplanning in VLSI design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
21	Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu	A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.	DATE	2003	DBLP DOI BibTeX RDF
21	Martijn T. Bennebroek	Validation of wire length distribution models on commercial designs.	SLIP	2003	DBLP DOI BibTeX RDF
21	Malgorzata Chrzanowska-Jeske, Benyi Wang, Garrison W. Greenwood	Floorplanning with performance-based clustering.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
21	Jyh Perng Fang, Sao-Jie Chen	Tile-graph-based power planning.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
21	Stelian Alupoaei, Srinivas Katkoori	Net-based force-directed macrocell placement for wirelength optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
21	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.	ISPD	2002	DBLP DOI BibTeX RDF	floorplanning, routability, interconnect estimation
21	Chiu-Wing Sham, Evangeline F. Y. Young	Routability driven floorplanner with buffer block planning.	ISPD	2002	DBLP DOI BibTeX RDF
21	Stephen E. Krufka, Phillip Christie	Terminal optimization analysis for functional block re-use.	SLIP	2002	DBLP DOI BibTeX RDF	optimization, SoC, interconnect, Rent's rule
21	Jai-Ming Lin, Yao-Wen Chang	TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.	DAC	2002	DBLP DOI BibTeX RDF
21	Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura	Floorplanning using a tree representation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
21	Swanwa Liao, Mario Alberto López, Dinesh P. Mehta	Constrained polygon transformations for incremental floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	floorplanning, incremental design, rectilinear polygons
21	Israel Koren, Zahava Koren	Incorporating Yield Enhancement into the Floorplanning Process.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield
21	Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh	Fast and accurate estimation of floorplans in logic/high-level synthesis.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
21	Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan 0002	CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Register and Module Assignment Design for low power, High level synthesis, Low power design, Floorplanning
21	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
21	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang	Slicing floorplans with boundary constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
21	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	ISPD	1998	DBLP DOI BibTeX RDF
21	Kia Bazargan, Samjung Kim, Majid Sarrafzadeh	Nostradamus: a floorplanner of uncertain design.	ISPD	1998	DBLP DOI BibTeX RDF
21	Jin-Tai Yan, Pei-Yung Hsiao	Minimizing the number of switchboxes for region definition and ordering assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
21	Peichen Pan, C. L. Liu 0001	Area minimization for floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
21	Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	A unified approach to topology generation and area optimization of general floorplans.	ICCAD	1995	DBLP DOI BibTeX RDF	VLSI floorplanning, AND-OR graphs, placement, heuristic search
21	J. T. Mowchenko, Y. Yang	Optimizing wiring space in slicing floorplans.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	wiring space optimisation, slicing floorplans, net density, sibling rectangles, circuit modules, routed layouts, VLSI, heuristic, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, branch and bound algorithm, wiring, IC layout
21	Kyunrak Chong, Sartaj Sahni	Optimal realizations of floorplans [VLSI layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
21	Chang-Sheng Ying, Joshua Sook-Leung Wong	An analytical approach to floorplanning for hierarchical building blocks layout [VLSI].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
21	Susmita Sur-Kolay, Bhargab B. Bhattacharya	Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning.	FSTTCS	1988	DBLP DOI BibTeX RDF	plane triangulated graphs, rectangular duals, slicing structures, algorithms, floorplanning, VLSI layout
21	Wing K. Luk, Donald T. Tang, C. K. Wong	Hierarchial global wiring for custom chip design.	DAC	1986	DBLP DOI BibTeX RDF
21	Daniel Gebhardt, JunBok You, Kenneth S. Stevens	Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs.	NOCS	2010	DBLP DOI BibTeX RDF	network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS
21	Vitor de Paulo, Cristinel Ababei	A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans.	ReConFig	2009	DBLP DOI BibTeX RDF	Homogeneous Network-on-Chip, heterogeneous floorplan, 3D circuits
21	H. A. Donegan, G. E. Livesey, T. B. M. McMaster, G. J. McAleavy	Axiomatic considerations of a rule based mechanism for the determination of a building's egress capability.	Artif. Intell. Rev.	2007	DBLP DOI BibTeX RDF	Building evacuation, Egress complexity, Entropy, Floorplan, Rooted tree
21	Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan	Thermal characterization and optimization in platform FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	Virtex4, platform FPGAs, thermal floorplan, placement, temperature, thermal
21	Matthew Moe, Herman Schmit	Floorplanning of pipelined array modules using sequence pairs.	ISPD	2003	DBLP DOI BibTeX RDF	pipelined array, floorplan, sequence pair
21	Helvio P. Peixoto, Margarida F. Jacome, Ander Royo	A Tight Area Upper Bound for Slicing Floorplans.	VLSI Design	2000	DBLP DOI BibTeX RDF	Early area estimation, slicing floorplan, system level design
21	Sandip Das 0001, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.	VLSI Design	1998	DBLP DOI BibTeX RDF	nonslicible floorplan, switchbox, Manhattan-diagonal model, channel, VLSI routing
21	Min Xu, Fadi J. Kurdahi	Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	FPGAs, high-level synthesis, floorplan, binding
21	Weiping Shi	An optimal algorithm for area minimization of slicing floorplans.	ICCAD	1995	DBLP DOI BibTeX RDF	floorplan, area optimization, area minimization
21	Jeffrey R. Horowitz, Alfonso F. Cardenas	Decomposing Heterogeneous Inter-Entity Relationship Updates.	IEEE Trans. Knowl. Data Eng.	1992	DBLP DOI BibTeX RDF	heterogeneous inter-entity relationship, decomposing multilingual update requests, distributed heterogeneous databases, prototype views, network database, update decomposition, unified conceptual view, intermediate control language steps, information retrieval, relational databases, distributed databases, floorplan, joins, update rules
18	Hanme Jang, Kiyun Yu, Jiyoung Kim	Generating Spatial Knowledge Graphs with 2D Indoor Floorplan Data: A Case Study on the Jeonju Express Bus Terminal.	ISPRS Int. J. Geo Inf.	2024	DBLP DOI BibTeX RDF
18	Zu Lin Ewe, Fu-Hao Chang, Yi-Shiang Huang, Li-Chen Fu	Spatial Graph-Based Localization and Navigation on Scaleless Floorplan.	IEEE Robotics Autom. Lett.	2024	DBLP DOI BibTeX RDF
18	Changan Chen, Rui Wang, Christoph Vogel, Marc Pollefeys	F3Loc: Fusion and Filtering for Floorplan Localization.	CoRR	2024	DBLP DOI BibTeX RDF
18	Rohin Gupta, Sandeep Singh Gill	A new representation in 3D VLSI floorplan: 3D O-Tree.	Genet. Program. Evolvable Mach.	2024	DBLP DOI BibTeX RDF
18	Ting-Chi Wang	Pioneering Contributions of Professor Martin D. F. Wong to Automatic Floorplan Design.	ISPD	2024	DBLP DOI BibTeX RDF
18	Shidong Wang, Wei Zeng 0004, Xi Chen, Yu Ye 0002, Yu Qiao 0001, Chi-Wing Fu	ActFloor-GAN: Activity-Guided Adversarial Networks for Human-Centric Floorplan Design.	IEEE Trans. Vis. Comput. Graph.	2023	DBLP DOI BibTeX RDF
18	Seongyong Kim, Yosuke Yajima, Jisoo Park, Jingdao Chen, Yong Kwon Cho	A Hybrid Semantic-Geometric Approach for Clutter-Resistant Floorplan Generation from Building Point Clouds.	CoRR	2023	DBLP DOI BibTeX RDF
18	Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu 0001, Alberto L. Sangiovanni-Vincentelli	Floorplet: Performance-aware Floorplan Framework for Chiplet Integration.	CoRR	2023	DBLP DOI BibTeX RDF
18	Delin Feng, Zhenpeng He, Jiawei Hou, Sören Schwertfeger, Liangjun Zhang	FloorplanNet: Learning Topometric Floorplan Matching for Robot Localization.	ICRA	2023	DBLP DOI BibTeX RDF
18	Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang 0012	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.	FPGA	2023	DBLP DOI BibTeX RDF
18	Vakhtang Janpoladov	A Machine Learning-Based Post-Route PVT-Aware Power Prediction of Benchmark Circuits at Floorplan Stage of Physical Design.	EWDTS	2023	DBLP DOI BibTeX RDF
18	Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang 0034, Yu Huang, Jianye Hao	TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction.	DATE	2023	DBLP DOI BibTeX RDF
18	Sándor Gazdag, Dániel Pasztornicky, Zsolt Jankó, Tamás Szirányi, András L. Majdik	Collaborative Visual-Inertial Localization of Teams With Floorplan Extraction.	ICASSP Workshops	2023	DBLP DOI BibTeX RDF
18	Anselmo Talotta, Valentin Radu, Lorenzo Sorgi	Floorplan Generation from Noisy Point Cloud.	GeoIndstry@SIGSPATIAL	2023	DBLP DOI BibTeX RDF
18	Xin Liu, Egor Bondarev, Peter H. N. de With	DL-based floorplan generation from noisy point clouds.	3DIA	2023	DBLP DOI BibTeX RDF
18	Wenming Wu	Architectural Floorplan Recognition via Iterative Semantic Segmentation Networks.	CSAI	2023	DBLP DOI BibTeX RDF