Search results for "full-adder"

Hits ?▲	Authors	Title	Venue	Year	Link
20	Saeid Seyedi, Nima Jafari Navimipour	Designing a multi-layer full-adder using a new three-input majority gate based on quantum computing.	Concurr. Comput. Pract. Exp.	2022	DBLP DOI BibTeX RDF
20	Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Mahsa Tahghigh	An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending.	Frontiers Inf. Technol. Electron. Eng.	2022	DBLP DOI BibTeX RDF
20	Mahmood Rafiee, Nabiollah Shiri, Ayoub Sadeghi	High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures.	IEEE Embed. Syst. Lett.	2022	DBLP DOI BibTeX RDF
20	Ali Ghorbani, Mehdi Dolatshahi, Sayed Mohammad Ali Zanjani, Behrang Barekatain	A new low-power Dynamic-GDI full adder in CNFET technology.	Integr.	2022	DBLP DOI BibTeX RDF
20	Sandeep Dhariwal, Reeba Korah, Ravi Shankar Mishra, Gaurav Kumar	Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications.	Int. J. Perform. Eng.	2022	DBLP DOI BibTeX RDF
20	Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour	Tolerant and low power subtractor with 4: 2 compressor and a new TG-PTL-float full adder cell.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
20	Pratiksha Shukla, Pramod Kumar, Prasanna Kumar Misra	An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
20	Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat	Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
20	Mi Lin, Qi Han, Wenyao Luo, Xuliang Wang, Junjie Chen, Weifeng Lyu	A ternary memristor full adder based on literal operation and module operation.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
20	K. Praghash, S. Arun Metha, B. Sai Tanuja, K. Preethi, N. P. N. S. Chandana	Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian	A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology.	ACM J. Emerg. Technol. Comput. Syst.	2022	DBLP DOI BibTeX RDF
20	Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Rafael B. Schvittz, Cristina Meinhardt	Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing.	SBCCI	2022	DBLP DOI BibTeX RDF
20	Sarada Musala, P. Durga Vasavi, B. Spandana, Avireni Srinivasulu, Cristian Ravariu	A Novel 2:1 Multiplexer Based Quaternary Full Adder.	iSES	2022	DBLP DOI BibTeX RDF
20	Jihyung Jung, Youngmin Kim	A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory.	ISOCC	2022	DBLP DOI BibTeX RDF
20	Panasa Srikanth, B. Srinivasu	High Performance Ternary Full Adder in CNFET-Memristor Logic Technology.	VDAT	2022	DBLP DOI BibTeX RDF
20	Mohammad Javad Maleki, Ali Mir 0001, Mohammad Soroosh	Ultra-fast all-optical full-adder based on nonlinear photonic crystal resonant cavities.	Photonic Netw. Commun.	2021	DBLP DOI BibTeX RDF
20	Saeid Seyedi, Nima Jafari Navimipour	Designing a three-level full-adder based on nano-scale quantum dot cellular automata.	Photonic Netw. Commun.	2021	DBLP DOI BibTeX RDF
20	Sarah Azimi, Corrado De Sio, Luca Sterpone	A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
20	Mukesh Patidar, Namit Gupta	Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder-subtractor using QCA technology.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
20	Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani	Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
20	Inamul Hussain, Saurabh Chaudhury	Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
20	Seied Ali Hosseini, Sajjad Etezadi	A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
20	Thiruvengadam Rajagopal, Arvind Chakrapani	A Novel High-Performance Hybrid Full Adder for VLSI Circuits.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
20	Mehedi Hasan, Md. Shahbaz Hussain, Mainul Hossain, Mohd. Hasan, Hasan U. Zaman, Sharnali Islam	A high-speed and scalable XOR-XNOR-based hybrid full adder design.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
20	Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen	CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
20	Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen	CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
20	Sadat Riyaz, Syed Farah Naz, Vijay Kumar Sharma	Multioperative reversible gate design with implementation of 1-bit full adder and subtractor along with energy dissipation analysis.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
20	Mehedi Hasan, Sharnali Islam, Mainul Hossain, Hasan U. Zaman	A scalable high-speed hybrid 1-bit full adder design using XOR-XNOR module.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
20	Seyed Erfan Fatemieh, Samira Shirinabadi Farahani, Mohammad Reza Reshadinezhad	LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS.	Sustain. Comput. Informatics Syst.	2021	DBLP DOI BibTeX RDF
20	Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani	Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
20	Jyoti Kandpal, Abhishek Tomar, Mayur Agarwal	Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
20	Mahmood Rafiee, Farshad Pesaran, Ayoub Sadeghi, Nabiollah Shiri	An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
20	Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa	An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation.	J. Electr. Comput. Eng.	2021	DBLP DOI BibTeX RDF
20	Xunbo Hu, Jiarui Xu, Bei Xu, Zixuan Peng, Guoyi Yu, Yuhui He, Chao Wang 0096	A Data Non-destructive IMPLY-based Memristive Semi-parallel Full-Adder for Computing-in-memory Systems.	ICTA	2021	DBLP DOI BibTeX RDF
20	Yuehong Gong, Min Luo, Chenxu Wang	An MTJ reading and writing control circuit applied in a 1-bit full adder.	IECC	2021	DBLP DOI BibTeX RDF
20	Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui	Spin Wave Based Full Adder.	ISCAS	2021	DBLP DOI BibTeX RDF
20	Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt	SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology.	LATS	2021	DBLP DOI BibTeX RDF
20	Xiangyu Zhang, Feng Wei, Xiaoyan Liu, Xiaole Cui	Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array.	ASICON	2021	DBLP DOI BibTeX RDF
20	Geuntae Park, Youngmin Kim	Low Power Gate Diffusion Input Full Adder using Floating Body.	ISOCC	2021	DBLP DOI BibTeX RDF
20	T. Suguna, M. Janaki Rani	Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications.	Int. J. Interact. Mob. Technol.	2020	DBLP DOI BibTeX RDF
20	Wei Xiao, Xinjian Zhang, Xingyi Zhang 0001, Congzhou Chen, Xiaolong Shi	Molecular Full Adder Based on DNA Strand Displacement.	IEEE Access	2020	DBLP DOI BibTeX RDF
20	Shokat Ganjeheizadeh Rohani, Nima Taherinejad, David Radakovits	A Semiparallel Full-Adder in IMPLY Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
20	Jyoti Kandpal, Abhishek Tomar, Mayur Agarwal, Kamal Kumar Sharma	High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
20	Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee	High-Efficient, Ultra-Low-Power and High-Speed 4: 2 Compressor with a New Full Adder Cell for Bioelectronics Applications.	Circuits Syst. Signal Process.	2020	DBLP DOI BibTeX RDF
20	Saeed Rasouli Heikalabad, Fereshteh Salimzadeh, Yashar Zirak Barughi	A unique three-layer full adder in quantum-dot cellular automata.	Comput. Electr. Eng.	2020	DBLP DOI BibTeX RDF
20	Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Parisa Rahimi	A low-power pseudo-dynamic full adder cell for image addition.	Comput. Electr. Eng.	2020	DBLP DOI BibTeX RDF
20	P. Radhakrishnan, Themozhi Govindarajan	FPGA implementation of XOR-MUX full adder based DWT for signal processing applications.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
20	V. J. Arulkarthick, Abinaya Rathinaswamy	Delay and area efficient approximate multiplier using reverse carry propagate full adder.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
20	S. Sharmila Devi, V. Bhanumathi 0001	Design of reversible logic based full adder in current-mode logic circuits.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
20	Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey	A 1-bit full adder using CNFET based dual chirality high speed domino logic.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
20	Sina Bakhtavari Mamaghani, Mohammad Hossein Moaiyeri, Ghassem Jaberipur	Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
20	Otgonnaran Ochirbat, Tseren-Onolt Ishdorj, Gordon Cichon	An error-tolerant serial binary full-adder via a spiking neural P system using HP/LP basic neurons.	J. Membr. Comput.	2020	DBLP DOI BibTeX RDF
20	Mehedi Hasan, Md. Jobayer Hossein, Mainul Hossain, Hasan U. Zaman, Sharnali Islam	Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
20	Mohamed S. Ghoneim, Amr Mohammaden, Rana Hesham, Ahmed H. Madian	Low Power Scalable Ternary Hybrid Full Adder Realization.	ICM	2020	DBLP DOI BibTeX RDF
20	Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt	Mirror Full Adder SET Susceptibility on 7nm FinFET Technology.	ICECS	2020	DBLP DOI BibTeX RDF
20	Shokat Ganjeheizadeh Rohani, Nima Taherinejad, David Radakovits	A Semiparallel Full-Adder in IMPLY Logic.	ISCAS	2020	DBLP DOI BibTeX RDF
20	E. Ramkumar, D. Gracin, P. Rajkamal, Bhuvana B. P., V. S. Kanchana Bhaaskaran	Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS).	iSES	2020	DBLP DOI BibTeX RDF
20	N. Suresh Kumar, Paramasivam K	Energy efficient low-power full-adder by 65 nm CMOS technology in ALU.	Concurr. Comput. Pract. Exp.	2019	DBLP DOI BibTeX RDF
20	Esmail Roosta, Seied Ali Hosseini	A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
20	Kishore Sanapala, Ramachandran Sakthivel	Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
20	Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy	High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
20	K. Murugan, S. Baulkani	VLSI implementation of ultra power optimized adiabatic logic based full adder cell.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
20	Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj	A low leakage TG-CNTFET-based inexact full adder for low power image processing applications.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
20	Aida Ghorbani Asibelagh, Reza Faghih Mirzaee	Applicability of Partial Ternary Full Adder in Ternary Arithmetic Units.	CoRR	2019	DBLP BibTeX RDF
20	Haroon Waris, Chenghua Wang, Weiqiang Liu 0001	High-performance approximate half and full adder cells using NAND logic gate.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
20	Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.	Design and Analysis of Energy Efficient Reversible Logic based Full Adder.	MWSCAS	2019	DBLP DOI BibTeX RDF
20	Xinya Lei, Ruixin Guo, Feng Zhang 0012, Lizhe Wang 0001, Rui Xu, Guangzhi Qu	Accelerating Homomorphic Full Adder Based on FHEW Using Multicore CPU and GPUs.	HPCC/SmartCity/DSS	2019	DBLP DOI BibTeX RDF
20	Lavanya Maddisetti, J. V. R. Ravindra	Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters.	NORCAS	2019	DBLP DOI BibTeX RDF
20	Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah	MRL Crossbar-Based Full Adder Design.	ICECS	2019	DBLP DOI BibTeX RDF
20	Hui Yang, Shukai Duan, Lidan Wang 0001	A Novel Memristor-CMOS Hybrid Full-Adder and Its Application.	ISNN (2)	2019	DBLP DOI BibTeX RDF
20	Rahul Singhal, Marek A. Perkowski	Comparative Analysis of Full Adder Custom Design Circuit using Two Regular Structures in Quantum-Dot Cellular Automata (QCA).	ISMVL	2019	DBLP DOI BibTeX RDF
20	Xiaotian Zhang, Pengjun Wang, Yunfei Yu, Yuejun Zhang, Shunxin Ye	A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback.	ASICON	2019	DBLP DOI BibTeX RDF
20	Mehedi Hasan, Uttam Kumar Saha, Afran Sorwar, Md. Ashik Zafar Dipto, Muhammad Saddam Hossain, Hasan U. Zaman	A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic.	ICCCNT	2019	DBLP DOI BibTeX RDF
20	D. Naveen Sai, G. Surya Kranth, Damarla Paradhasaradhi, R. S. Ernest Ravindran, M. Lakshmana Kumar, K. Mariya Priyadarshini	Five Input Multilayer Full Adder by QCA Designer.	ICACDS (2)	2019	DBLP DOI BibTeX RDF
20	Hamed Naseri, Somayeh Timarchi	Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
20	Saeed Rasouli Heikalabad, Mazaher Naji Asfestani, Mehdi Hosseinzadeh 0001	A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis.	J. Supercomput.	2018	DBLP DOI BibTeX RDF
20	Lei Wang 0141, Guangjun Xie	Novel designs of full adder in quantum-dot cellular automata technology.	J. Supercomput.	2018	DBLP DOI BibTeX RDF
20	Shiva Rahbar Arabani, Mohammad Reza Reshadinezhad, Majid Haghparast	Design of a parity preserving reversible full adder/subtractor circuit.	Int. J. Comput. Intell. Stud.	2018	DBLP DOI BibTeX RDF
20	Majid Amini Valashani, Mehdi Ayat, Sattar Mirzakuchaki	Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
20	Ali Zarei, Farshad Safaei	Power and area-efficient design of VCMA-MRAM based full-adder using approximate computing for IoT applications.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
20	Saeid Seyedi, Nima Jafari Navimipour	Design and evaluation of a new structure for fault-tolerance full-adder based on quantum-dot cellular automata.	Nano Commun. Networks	2018	DBLP DOI BibTeX RDF
20	Fahimeh Danehdaran, Milad Bagherian Khosroshahy, Keivan Navi, Nader Bagherzadeh	Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata.	J. Low Power Electron.	2018	DBLP DOI BibTeX RDF
20	Pankaj Kumar, Rajender Kumar Sharma	Low power low voltage CMOS full adder cells based on energy-efficient architecture.	Int. J. Comput. Appl. Technol.	2018	DBLP DOI BibTeX RDF
20	Shahmini Subramaniam, Ajay Kumar Singh, Gajula Ramana Murthy	Design of power efficient stable 1-bit full adder circuit.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
20	Francesco Maria Puglisi, Lorenzo Pacchioni, Nicolo Zagni, Paolo Pavan	Energy-Efficient Logic-in-Memory I-bit Full Adder Enabled by a Physics-Based RRAM Compact Model.	ESSDERC	2018	DBLP DOI BibTeX RDF
20	Ayrat Galisultanov, Yann Perrin, Hervé Fanet, Louis Hutin, Gaël Pillonnet	Compact MEMS modeling to design full adder in Capacitive Adiabatic Logic.	ESSDERC	2018	DBLP DOI BibTeX RDF
20	Sally Ahmed, Saad Ilyas, Nizar Jaber, Xuecui Zou, Ren Li, Mohammad Ibrahim Younis, Hossein Fariborzi	Design and Demonstration of A Compact Full Adder Using Micro-beam Resonators.	MWSCAS	2018	DBLP DOI BibTeX RDF
20	Muyu Yang, Erdal Oruklu	Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode.	MWSCAS	2018	DBLP DOI BibTeX RDF
20	Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet	Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology.	NORCAS	2018	DBLP DOI BibTeX RDF
20	Sanjay Prajapati, Zeljko Zilic, Brajesh Kumar Kaushik	Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM.	NEWCAS	2018	DBLP DOI BibTeX RDF
20	Prateek Gupta, Shubham Kumar, Zia Abbas	Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power.	VDAT	2018	DBLP DOI BibTeX RDF
20	Mokhtar Mohammadi Ghanatghestani, Behnam Ghavami, Honeya Salehpour	A CNFET full adder cell design for high-speed arithmetic units.	Turkish J. Electr. Eng. Comput. Sci.	2017	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Mohammad Hossein Shafiabadi	A novel high-performance and reliable multi-threshold CNFET full adder cell design.	Int. J. High Perform. Syst. Archit.	2017	DBLP DOI BibTeX RDF
20	Nikolaos I. Dourvas, Georgios Ch. Sirakoulis, Andrew Adamatzky	Cellular Automaton Belousov-Zhabotinsky Model for Binary Full Adder.	Int. J. Bifurc. Chaos	2017	DBLP DOI BibTeX RDF
20	Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur	Radix-8 full adder in QCA with single clock-zone carry propagation delay.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
20	Pankaj Kumar, Rajender Kumar Sharma	An Energy Efficient Logic Approach to Implement CMOS Full Adder.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
20	Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Zahra Zareei, Seyedeh Mohtaram Daryabari	A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
20	M. C. Parameshwara, H. C. Srinivasaiah	Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
20	Arman Roohi, Ramtin Zand, Deliang Fan, Ronald F. DeMara	Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
20	Asma Torkzadeh Mahani, Peiman Keshavarzian	A novel energy-efficient and high speed full adder using CNTFET.	Microelectron. J.	2017	DBLP DOI BibTeX RDF