Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Saeid Seyedi, Nima Jafari Navimipour |
Designing a multi-layer full-adder using a new three-input majority gate based on quantum computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 34(4), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Mahsa Tahghigh |
An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 23(6), pp. 950-965, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Mahmood Rafiee, Nabiollah Shiri, Ayoub Sadeghi |
High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 14(1), pp. 47-50, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Ali Ghorbani, Mehdi Dolatshahi, Sayed Mohammad Ali Zanjani, Behrang Barekatain |
A new low-power Dynamic-GDI full adder in CNFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 83, pp. 46-59, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Sandeep Dhariwal, Reeba Korah, Ravi Shankar Mishra, Gaurav Kumar |
Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Perform. Eng. ![In: Int. J. Perform. Eng. 18(1), pp. 22, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour |
Tolerant and low power subtractor with 4: 2 compressor and a new TG-PTL-float full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 16(6), pp. 437-460, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Pratiksha Shukla, Pramod Kumar, Prasanna Kumar Misra |
An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(11), pp. 4548-4552, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat |
Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(8), pp. 2250146:1-2250146:15, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Mi Lin, Qi Han, Wenyao Luo, Xuliang Wang, Junjie Chen, Weifeng Lyu |
A ternary memristor full adder based on literal operation and module operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(8), pp. 2932-2940, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | K. Praghash, S. Arun Metha, B. Sai Tanuja, K. Preethi, N. P. N. S. Chandana |
Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 126(4), pp. 3041-3069, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian |
A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 18(4), pp. 74:1-74:20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Rafael B. Schvittz, Cristina Meinhardt |
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022, Porto Alegre, Brazil, August 22-26, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8128-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Sarada Musala, P. Durga Vasavi, B. Spandana, Avireni Srinivasulu, Cristian Ravariu |
A Novel 2:1 Multiplexer Based Quaternary Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022, pp. 372-377, 2022, IEEE, 979-8-3503-9922-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Jihyung Jung, Youngmin Kim |
A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022, pp. 131-132, 2022, IEEE, 978-1-6654-5971-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Panasa Srikanth, B. Srinivasu |
High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 420-434, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Mohammad Javad Maleki, Ali Mir 0001, Mohammad Soroosh |
Ultra-fast all-optical full-adder based on nonlinear photonic crystal resonant cavities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 41(1), pp. 93-101, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Saeid Seyedi, Nima Jafari Navimipour |
Designing a three-level full-adder based on nano-scale quantum dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 42(3), pp. 184-193, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Sarah Azimi, Corrado De Sio, Luca Sterpone |
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(8), pp. 1596-1600, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Mukesh Patidar, Namit Gupta |
Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder-subtractor using QCA technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 77(8), pp. 7893-7915, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani |
Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(7), pp. 3523-3535, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Inamul Hussain, Saurabh Chaudhury |
Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(4), pp. 1762-1787, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Seied Ali Hosseini, Sajjad Etezadi |
A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(3), pp. 1314-1332, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Thiruvengadam Rajagopal, Arvind Chakrapani |
A Novel High-Performance Hybrid Full Adder for VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(11), pp. 5718-5732, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Mehedi Hasan, Md. Shahbaz Hussain, Mainul Hossain, Mohd. Hasan, Hasan U. Zaman, Sharnali Islam |
A high-speed and scalable XOR-XNOR-based hybrid full adder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 93, pp. 107200, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen |
CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(10), pp. 2150172:1-2150172:33, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen |
CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(11), pp. 2192001:1, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Sadat Riyaz, Syed Farah Naz, Vijay Kumar Sharma |
Multioperative reversible gate design with implementation of 1-bit full adder and subtractor along with energy dissipation analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(4), pp. 990-1012, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Mehedi Hasan, Sharnali Islam, Mainul Hossain, Hasan U. Zaman |
A scalable high-speed hybrid 1-bit full adder design using XOR-XNOR module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(11), pp. 3597-3606, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Seyed Erfan Fatemieh, Samira Shirinabadi Farahani, Mohammad Reza Reshadinezhad |
LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 30, pp. 100529, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani |
Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 108, pp. 104962, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Jyoti Kandpal, Abhishek Tomar, Mayur Agarwal |
Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 115, pp. 105205, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Mahmood Rafiee, Farshad Pesaran, Ayoub Sadeghi, Nabiollah Shiri |
An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 118, pp. 105287, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa |
An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2021, pp. 8856399:1-8856399:9, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Xunbo Hu, Jiarui Xu, Bei Xu, Zixuan Peng, Guoyi Yu, Yuhui He, Chao Wang 0096 |
A Data Non-destructive IMPLY-based Memristive Semi-parallel Full-Adder for Computing-in-memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021, pp. 212-213, 2021, IEEE, 978-1-6654-1745-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Yuehong Gong, Min Luo, Chenxu Wang |
An MTJ reading and writing control circuit applied in a 1-bit full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECC ![In: IECC 2021: 3rd International Electronics Communication Conference, Ho Chi Minh City, Vietnam, July 8 - 10, 2021, pp. 22-27, 2021, ACM, 978-1-4503-8993-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui |
Spin Wave Based Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt |
SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 22nd IEEE Latin American Test Symposium, LATS 2021, Punta del Este, Uruguay, October 27-29, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2057-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Xiangyu Zhang, Feng Wei, Xiaoyan Liu, Xiaole Cui |
Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Geuntae Park, Youngmin Kim |
Low Power Gate Diffusion Input Full Adder using Floating Body. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 337-338, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | T. Suguna, M. Janaki Rani |
Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Interact. Mob. Technol. ![In: Int. J. Interact. Mob. Technol. 14(5), pp. 73-94, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Wei Xiao, Xinjian Zhang, Xingyi Zhang 0001, Congzhou Chen, Xiaolong Shi |
Molecular Full Adder Based on DNA Strand Displacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 189796-189801, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Shokat Ganjeheizadeh Rohani, Nima Taherinejad, David Radakovits |
A Semiparallel Full-Adder in IMPLY Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(1), pp. 297-301, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Jyoti Kandpal, Abhishek Tomar, Mayur Agarwal, Kamal Kumar Sharma |
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(6), pp. 1413-1422, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee |
High-Efficient, Ultra-Low-Power and High-Speed 4: 2 Compressor with a New Full Adder Cell for Bioelectronics Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 39(12), pp. 6247-6275, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Saeed Rasouli Heikalabad, Fereshteh Salimzadeh, Yashar Zirak Barughi |
A unique three-layer full adder in quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 86, pp. 106735, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Parisa Rahimi |
A low-power pseudo-dynamic full adder cell for image addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 87, pp. 106787, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | P. Radhakrishnan, Themozhi Govindarajan |
FPGA implementation of XOR-MUX full adder based DWT for signal processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 73, pp. 102961, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | V. J. Arulkarthick, Abinaya Rathinaswamy |
Delay and area efficient approximate multiplier using reverse carry propagate full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 74, pp. 103009, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | S. Sharmila Devi, V. Bhanumathi 0001 |
Design of reversible logic based full adder in current-mode logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 76, pp. 103100, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey |
A 1-bit full adder using CNFET based dual chirality high speed domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 48(1), pp. 115-133, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Sina Bakhtavari Mamaghani, Mohammad Hossein Moaiyeri, Ghassem Jaberipur |
Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 103, pp. 104864, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Otgonnaran Ochirbat, Tseren-Onolt Ishdorj, Gordon Cichon |
An error-tolerant serial binary full-adder via a spiking neural P system using HP/LP basic neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Membr. Comput. ![In: J. Membr. Comput. 2(1), pp. 42-48, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Mehedi Hasan, Md. Jobayer Hossein, Mainul Hossain, Hasan U. Zaman, Sharnali Islam |
Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(8), pp. 1464-1468, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Mohamed S. Ghoneim, Amr Mohammaden, Rana Hesham, Ahmed H. Madian |
Low Power Scalable Ternary Hybrid Full Adder Realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 32nd International Conference on Microelectronics, ICM 2020, Aqaba, Jordan, December 14-17, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9664-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt |
Mirror Full Adder SET Susceptibility on 7nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, Scotland, UK, November 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6044-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Shokat Ganjeheizadeh Rohani, Nima Taherinejad, David Radakovits |
A Semiparallel Full-Adder in IMPLY Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | E. Ramkumar, D. Gracin, P. Rajkamal, Bhuvana B. P., V. S. Kanchana Bhaaskaran |
Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2020 (Formerly iNiS), Chennai, India, December 14-16, 2020, pp. 281-284, 2020, IEEE, 978-1-6654-0478-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | N. Suresh Kumar, Paramasivam K |
Energy efficient low-power full-adder by 65 nm CMOS technology in ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 31(12), 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Esmail Roosta, Seied Ali Hosseini |
A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 38(9), pp. 4056-4078, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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20 | Kishore Sanapala, Ramachandran Sakthivel |
Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(4), pp. 465-470, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy |
High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 77, pp. 205-216, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | K. Murugan, S. Baulkani |
VLSI implementation of ultra power optimized adiabatic logic based full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 70, pp. 15-20, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj |
A low leakage TG-CNTFET-based inexact full adder for low power image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 47(9), pp. 1446-1458, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Aida Ghorbani Asibelagh, Reza Faghih Mirzaee |
Applicability of Partial Ternary Full Adder in Ternary Arithmetic Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.06742, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
20 | Haroon Waris, Chenghua Wang, Weiqiang Liu 0001 |
High-performance approximate half and full adder cells using NAND logic gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 16(6), pp. 20190043, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B. |
Design and Analysis of Energy Efficient Reversible Logic based Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019, Dallas, TX, USA, August 4-7, 2019, pp. 339-342, 2019, IEEE, 978-1-7281-2788-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Xinya Lei, Ruixin Guo, Feng Zhang 0012, Lizhe Wang 0001, Rui Xu, Guangzhi Qu |
Accelerating Homomorphic Full Adder Based on FHEW Using Multicore CPU and GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC/SmartCity/DSS ![In: 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019, Zhangjiajie, China, August 10-12, 2019, pp. 2508-2513, 2019, IEEE, 978-1-7281-2058-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Lavanya Maddisetti, J. V. R. Ravindra |
Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-2769-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah |
MRL Crossbar-Based Full Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, pp. 674-677, 2019, IEEE, 978-1-7281-0996-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Hui Yang, Shukai Duan, Lidan Wang 0001 |
A Novel Memristor-CMOS Hybrid Full-Adder and Its Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2019 - 16th International Symposium on Neural Networks, ISNN 2019, Moscow, Russia, July 10-12, 2019, Proceedings, Part II, pp. 556-564, 2019, Springer, 978-3-030-22807-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Rahul Singhal, Marek A. Perkowski |
Comparative Analysis of Full Adder Custom Design Circuit using Two Regular Structures in Quantum-Dot Cellular Automata (QCA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), Fredericton, NB, Canada, May 21-23, 2019, pp. 194-199, 2019, IEEE, 978-1-7281-0092-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Xiaotian Zhang, Pengjun Wang, Yunfei Yu, Yuejun Zhang, Shunxin Ye |
A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Mehedi Hasan, Uttam Kumar Saha, Afran Sorwar, Md. Ashik Zafar Dipto, Muhammad Saddam Hossain, Hasan U. Zaman |
A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 10th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2019, Kanpur, India, July 6-8, 2019, pp. 1-6, 2019, IEEE, 978-1-5386-5906-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | D. Naveen Sai, G. Surya Kranth, Damarla Paradhasaradhi, R. S. Ernest Ravindran, M. Lakshmana Kumar, K. Mariya Priyadarshini |
Five Input Multilayer Full Adder by QCA Designer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACDS (2) ![In: Advances in Computing and Data Sciences - Third International Conference, ICACDS 2019, Ghaziabad, India, April 12-13, 2019, Revised Selected Papers, Part II, pp. 164-174, 2019, Springer, 978-981-13-9941-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Hamed Naseri, Somayeh Timarchi |
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(8), pp. 1481-1493, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Saeed Rasouli Heikalabad, Mazaher Naji Asfestani, Mehdi Hosseinzadeh 0001 |
A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 74(5), pp. 1994-2005, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Lei Wang 0141, Guangjun Xie |
Novel designs of full adder in quantum-dot cellular automata technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 74(9), pp. 4798-4816, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Shiva Rahbar Arabani, Mohammad Reza Reshadinezhad, Majid Haghparast |
Design of a parity preserving reversible full adder/subtractor circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Intell. Stud. ![In: Int. J. Comput. Intell. Stud. 7(1), pp. 19-32, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Majid Amini Valashani, Mehdi Ayat, Sattar Mirzakuchaki |
Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 74, pp. 49-59, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Ali Zarei, Farshad Safaei |
Power and area-efficient design of VCMA-MRAM based full-adder using approximate computing for IoT applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 82, pp. 62-70, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Saeid Seyedi, Nima Jafari Navimipour |
Design and evaluation of a new structure for fault-tolerance full-adder based on quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nano Commun. Networks ![In: Nano Commun. Networks 16, pp. 1-9, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Fahimeh Danehdaran, Milad Bagherian Khosroshahy, Keivan Navi, Nader Bagherzadeh |
Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 14(1), pp. 38-48, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Pankaj Kumar, Rajender Kumar Sharma |
Low power low voltage CMOS full adder cells based on energy-efficient architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Appl. Technol. ![In: Int. J. Comput. Appl. Technol. 57(4), pp. 291-301, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Shahmini Subramaniam, Ajay Kumar Singh, Gajula Ramana Murthy |
Design of power efficient stable 1-bit full adder circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(14), pp. 20180552, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Francesco Maria Puglisi, Lorenzo Pacchioni, Nicolo Zagni, Paolo Pavan |
Energy-Efficient Logic-in-Memory I-bit Full Adder Enabled by a Physics-Based RRAM Compact Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018, pp. 50-53, 2018, IEEE, 978-1-5386-5401-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Ayrat Galisultanov, Yann Perrin, Hervé Fanet, Louis Hutin, Gaël Pillonnet |
Compact MEMS modeling to design full adder in Capacitive Adiabatic Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018, pp. 174-177, 2018, IEEE, 978-1-5386-5401-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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20 | Sally Ahmed, Saad Ilyas, Nizar Jaber, Xuecui Zou, Ren Li, Mohammad Ibrahim Younis, Hossein Fariborzi |
Design and Demonstration of A Compact Full Adder Using Micro-beam Resonators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 623-626, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Muyu Yang, Erdal Oruklu |
Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 420-423, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet |
Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, October 30-31, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-7656-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Sanjay Prajapati, Zeljko Zilic, Brajesh Kumar Kaushik |
Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018, Montréal, QC, Canada, June 24-27, 2018, pp. 317-321, 2018, IEEE, 978-1-5386-4859-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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20 | Prateek Gupta, Shubham Kumar, Zia Abbas |
Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers, pp. 88-99, 2018, Springer, 978-981-13-5949-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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20 | Mokhtar Mohammadi Ghanatghestani, Behnam Ghavami, Honeya Salehpour |
A CNFET full adder cell design for high-speed arithmetic units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 25, pp. 2399-2409, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Mohammad Hossein Shafiabadi |
A novel high-performance and reliable multi-threshold CNFET full adder cell design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 7(1), pp. 15-25, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Nikolaos I. Dourvas, Georgios Ch. Sirakoulis, Andrew Adamatzky |
Cellular Automaton Belousov-Zhabotinsky Model for Binary Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bifurc. Chaos ![In: Int. J. Bifurc. Chaos 27(6), pp. 1750089:1-1750089:14, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur |
Radix-8 full adder in QCA with single clock-zone carry propagation delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 51, pp. 176-184, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Pankaj Kumar, Rajender Kumar Sharma |
An Energy Efficient Logic Approach to Implement CMOS Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(5), pp. 1750084:1-1750084:20, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Zahra Zareei, Seyedeh Mohtaram Daryabari |
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(5), pp. 1750082:1-1750082:15, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | M. C. Parameshwara, H. C. Srinivasaiah |
Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(1), pp. 1750014:1-1750014:15, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Arman Roohi, Ramtin Zand, Deliang Fan, Ronald F. DeMara |
Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12), pp. 2134-2138, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Asma Torkzadeh Mahani, Peiman Keshavarzian |
A novel energy-efficient and high speed full adder using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 61, pp. 79-88, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|