Search results for "instructions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP DOI BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
29	Hans Vandierendonck, André Seznec	Fetch Gating Control through Speculative Instruction Window Weighting.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
29	Woojin Choi, Seok-Jun Park, Michel Dubois 0001	Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
29	Dongsoo Kang, Chen Liu 0001, Jean-Luc Gaudiot	The Impact of Speculative Execution on SMT Processors.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Speculation control, Simultaneous multithreading, Thread scheduling, Confidence estimator
29	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	Compilation for compact power-gating controls.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction
29	Stephen Roderick Hines, Gary S. Tyson, David B. Whalley	Addressing instruction fetch bottlenecks by using an instruction register file.	LCTES	2007	DBLP DOI BibTeX RDF	L0/filter cache, instruction packing, instruction register file
29	Md. Mafijul Islam, Per Stenström	Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications.	SIES	2007	DBLP DOI BibTeX RDF
29	Hans Vandierendonck, André Seznec	Fetch Gating Control Through Speculative Instruction Window Weighting.	HiPEAC	2007	DBLP DOI BibTeX RDF
29	Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy	High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization.	IPCCC	2006	DBLP DOI BibTeX RDF
29	Jaume Abella 0001, Antonio González 0001	SAMIE-LSQ: set-associative multiple-instruction entry load/store queue.	IPDPS	2006	DBLP DOI BibTeX RDF
29	Joseph J. Sharkey, Dmitry V. Ponomarev	Non-uniform Instruction Scheduling.	Euro-Par	2005	DBLP DOI BibTeX RDF
29	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	A sink-n-hoist framework for leakage power reduction.	EMSOFT	2005	DBLP DOI BibTeX RDF	balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction
29	Fabrice Rastello, François de Ferrière, Christophe Guillon	Optimizing Translation Out of SSA Using Renaming Constraints.	CGO	2004	DBLP DOI BibTeX RDF
29	Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero	Out-of-Order Commit Processors.	HPCA	2004	DBLP DOI BibTeX RDF
29	Rolf B. Hilgendorf, Wolfram Sauer	Instruction translation for an experimental S/390 processor.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	IBM System/390
29	Chen-Yong Cher, T. N. Vijaykumar	Skipper: a microarchitecture for exploiting control-flow independence.	MICRO	2001	DBLP DOI BibTeX RDF
29	Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems.	EUROMICRO	1999	DBLP DOI BibTeX RDF
29	Antonio González 0001, Jordi Tubella, Carlos Molina	Trace-Level Reuse.	ICPP	1999	DBLP DOI BibTeX RDF	data value reuse, instruction-level reuse, Instruction-level parallelism
29	Kazuya Murao, Tsutomu Terada	Evaluating Effect of Concreteness in Instructions for Gesture Recognition.	ISWC	2011	DBLP DOI BibTeX RDF	Gesture recognition, Instructions, Concreteness
29	Lorna McKnight, Daniel Fitton	Touch-screen technology for children: giving the right instructions and getting the right responses.	IDC	2010	DBLP DOI BibTeX RDF	CCI, usability, children, gestures, language, touch-screens, instructions
29	Luca Chittaro, Roberto Ranon, Luca De Marco, Augusto Senerchia	User Modeling of Disabled Persons for Generating Instructions to Medical First Responders.	UMAP	2009	DBLP DOI BibTeX RDF	personalized health services, disabled patients, adaptive instructions, user model, first responders
29	Christian Kray, Christian Elting, Katri Laakso, Volker Coors	Presenting route instructions on mobile devices.	IUI	2003	DBLP DOI BibTeX RDF	route instructions, mobile devices, multimodal presentations, positional information
29	Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey	ED4I: Error Detection by Diverse Data and Duplicated Instructions.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Software implemented hardware fault tolerance (SIHFT), low cost fault tolerance, data diversity, duplicated instructions, concurrent error detection
29	Arvind Krishnaswamy, Rajiv Gupta 0001	Profile guided selection of ARM and thumb instructions.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	16/32 bit instructions, code size and speed, low power
27	Ryad Benadjila, Olivier Billet, Shay Gueron, Matthew J. B. Robshaw	The Intel AES Instructions Set and the SHA-3 Candidates.	ASIACRYPT	2009	DBLP DOI BibTeX RDF
27	Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata	New SIMD instructions set for image processing applications enhancement.	ICIP	2008	DBLP DOI BibTeX RDF
27	Carlos Morra, João M. P. Cardoso, Jürgen Becker 0001	Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements.	IPDPS	2007	DBLP DOI BibTeX RDF
27	Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr	A code-generator generator for multi-output instructions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	ISS, code-selection, compiler/architecture co-design, ASIP
27	Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt	On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.	IEEE Comput. Archit. Lett.	2005	DBLP DOI BibTeX RDF
27	Stephen Hines, Gary S. Tyson, David B. Whalley	Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.	MICRO	2005	DBLP DOI BibTeX RDF
27	Luigi Di Stefano, Stefano Mattoccia, Federico Tombari	Speeding-up NCC-Based Template Matching Using Parallel Multimedia Instructions.	CAMP	2005	DBLP DOI BibTeX RDF
27	Kikuo Asai, Hideaki Kobayashi, Tomotsugu Kondo	Augmented Instructions - A Fusion of Augmented Reality and Printed Learning Materials.	ICALT	2005	DBLP DOI BibTeX RDF
27	Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley	Improving Program Efficiency by Packing Instructions into Registers.	ISCA	2005	DBLP DOI BibTeX RDF
27	Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin	Scheduling Reusable Instructions for Power Reduction.	DATE	2004	DBLP DOI BibTeX RDF
27	Shiliang Hu, James E. Smith 0001	Using Dynamic Binary Translation to Fuse Dependent Instructions.	CGO	2004	DBLP DOI BibTeX RDF
27	Sami Yehia, Olivier Temam	From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation.	ISCA	2004	DBLP DOI BibTeX RDF
27	Jae Sung Lee, Myung Hoon Sunwoo	Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	application specific digital signal processor, DMT, fast Fourier transform, OFDM
27	Warren Cheung, William S. Evans, Jeremy Moses	Predicated Instructions for Code Compaction.	SCOPES	2003	DBLP DOI BibTeX RDF
27	Tali Moreshet, R. Iris Bahar	Power-aware issue queue design for speculative instructions.	DAC	2003	DBLP DOI BibTeX RDF	low power design, microarchitecture, speculation
27	Sunghyun Jee, Kannappan Palaniappan	Dynamically Scheduling VLIW Instructions with Dependency Information.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	DISVLIW, VLIW, Dynamic Scheduling, Processor Architecture, ILP
27	Russell S. Blue, Jeff Wampler, G. Bowden Wise, Louis J. Hoebel, Boris Yamrom, Christopher R. Volpe, Bruce Wilde, Pascale Rondot, Ann E. Kelley Sobel, Anne Gilman, Wesley Turner, Steve Linthicum, George Ryon	An automated approach and virtual environment for generating maintenance instructions.	CHI Extended Abstracts	2002	DBLP DOI BibTeX RDF	maintainability analysis, maintenance manual development, XML, virtual environments, haptics, natural language, human-centered design, text generation
27	Rainer Leupers	Code Selection for Media Processors with SIMD Instructions.	DATE	2000	DBLP DOI BibTeX RDF
27	Zhenyu Qian	A Formal Specification of Java Virtual Machine Instructions for Objects, Methods and Subrountines.	Formal Syntax and Semantics of Java	1999	DBLP DOI BibTeX RDF
27	David Bernstein, Michael Rodeh, Shmuel Sagiv	Proving Safety of Speculative Load Instructions at Compile Time.	ESOP	1992	DBLP DOI BibTeX RDF
27	Krishna V. Palem, Barbara B. Simons	Scheduling Time-Critical Instructions on RISC Machines.	POPL	1990	DBLP DOI BibTeX RDF	RISC
27	Lingtao Wang, Chuan-lin Wu	I-NET mechanism for issuing multiple instructions.	SC	1988	DBLP DOI BibTeX RDF
26	Anna Inn-Tung Chen, Ming-Shing Chen, Tien-Ren Chen, Chen-Mou Cheng, Jintai Ding, Eric Li-Hsiang Kuo, Frost Yu-Shuang Lee, Bo-Yin Yang	SSE Implementation of Multivariate PKCs on Modern x86 CPUs.	CHES	2009	DBLP DOI BibTeX RDF	multivariate public key cryptosystem (MPKC), ?IC, vector instructions, SSSE3, Wiedemann, TTS, rainbow, SSE2
26	Renata Yumi Shimabukuro	Designing an interactive spoken help application for preschool children.	IDC	2008	DBLP DOI BibTeX RDF	spoken help, interactive television, instructions, preschool children
26	Aneesh Aggarwal, Manoj Franklin	Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency.	IEEE PACT	2003	DBLP DOI BibTeX RDF	Instruction Replication, Inter-PE communication, Instruction Distribution, Instructions per Cycle, Load Imbalance, Clustered processors
26	Rainer Leupers, Steven Bashford	Graph-based code selection techniques for embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	code selection, irregular data paths, embedded processors, data-flow graphs, SIMD instructions
26	Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge	ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator.	FCCM	1999	DBLP DOI BibTeX RDF	XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions
26	Roger Collins, Gordon B. Steven	Instruction Scheduling for a Superscalar Architecture.	EUROMICRO	1996	DBLP DOI BibTeX RDF	compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions
26	Steven Wallace, Nirav Dagli, Nader Bagherzadeh	Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz
26	V. Prasad Krothapalli, P. Sadayappan	Removal of Redundant Dependences in DOACROSS Loops with Constant Dependences.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	constant dependences, redundant dependences, simple loops, parallelexecution, synchronization instructions, doubly nestedloop, parallel programming, redundancy, directed graphs, nested loops, iteration space, DOACROSS loops
25	Cassandre Simon, Manel Boukli Hacene, Flavien Lebrun, Samir Otmane, Amine Chellali	Influence of multimodal instructions on learning tool manipulation skills through mentoring in an immersive environment: Influence des instructions multimodales sur l'apprentissage par compagnonnage des compétences de manipulation d'outil dans un environnement immersif.	IHM	2024	DBLP DOI BibTeX RDF
25	Yifan Du 0002, Hangyu Guo, Kun Zhou 0002, Wayne Xin Zhao, Jinpeng Wang 0001, Chuyuan Wang, Mingchen Cai, Ruihua Song, Ji-Rong Wen	What Makes for Good Visual Instructions? Synthesizing Complex Visual Reasoning Instructions for Visual Instruction Tuning.	CoRR	2023	DBLP DOI BibTeX RDF
25	Swaroop Mishra, Daniel Khashabi, Chitta Baral, Hannaneh Hajishirzi	Natural Instructions: Benchmarking Generalization to New Tasks from Natural Language Instructions.	CoRR	2021	DBLP BibTeX RDF
25	Elaine C. Khoong, Sachin Shah, Michelle Mourad, Raman R. Khanna	Impact of comprehensive, language-concordant discharge instructions on rates of patient questions about discharge medications or instructions.	AMIA	2020	DBLP BibTeX RDF
25	Ellen S. Wilschut, Reinier Könemann, Molly S. Murphy, Gu J. W. Van Rhijn, Tim Bosch	Evaluating learning approaches for product assembly: using chunking of instructions, spatial augmented reality and display based work instructions.	PETRA	2019	DBLP DOI BibTeX RDF
25	Jonas Blattgerste, Patrick Renner, Benjamin Strenge, Thies Pfeiffer	In-Situ Instructions Exceed Side-by-Side Instructions in Augmented Reality Assisted Assembly.	PETRA	2018	DBLP DOI BibTeX RDF
25	K. A. Batuzov	The use of vector instructions of a processor architecture for emulating the vector instructions of another processor architecture.	Program. Comput. Softw.	2017	DBLP DOI BibTeX RDF
25	Julie Sauvage-Vincent	Un langage contrôlé pour les instructions nautiques du Service Hydographique et Océanographique de la Marine. (A controlled language for the french national Hydrographic and Oceanographic Service Coast Pilot Books instructions nautiques).		2017	RDF
25	Elsa Eiriksdottir, Richard Catrambone	Procedural Instructions, Principles, and Examples: How to Structure Instructions for Procedural Tasks to Enhance Performance, Learning, and Transfer.	Hum. Factors	2011	DBLP DOI BibTeX RDF
25	Joerg C. Wolf, Guido Bugmann	Converting multi-modal task instructions to rule-based robot instructions.	RO-MAN	2008	DBLP DOI BibTeX RDF
25	Guillaume Huard	Algorithmique du décalage d'instructions. (Instructions shifting algorithmics).		2001	RDF
24	Minming Li, Chun Jason Xue, Tiantian Liu 0001, Yingchao Zhao 0001	Analysis and approximation for bank selection instruction minimization on partitioned memory architecture.	LCTES	2010	DBLP DOI BibTeX RDF	bank selection instruction minimization, partitioned memory architecture
24	Aneesh Aggarwal	Complexity Effective Bypass Networks.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
24	Suriya Subramanian, Kathryn S. McKinley	HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.	HiPEAC	2009	DBLP DOI BibTeX RDF
24	Maged M. Michael, Martin T. Vechev, Vijay A. Saraswat	Idempotent work stealing.	PPoPP	2009	DBLP DOI BibTeX RDF	memory barrier, memory fence, atomic, work stealing
24	Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley	Strategies for mapping dataflow blocks to distributed hardware.	MICRO	2008	DBLP DOI BibTeX RDF
24	Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt	Performance-aware speculation control using wrong path usefulness prediction.	HPCA	2008	DBLP DOI BibTeX RDF
24	Arno Puder	Byte Code Transformations using XSL Stylesheets.	SNPD	2008	DBLP DOI BibTeX RDF
24	Guilherme Ottoni, David I. August	Communication optimizations for global multi-threaded instruction scheduling.	ASPLOS	2008	DBLP DOI BibTeX RDF	graph min-cut, communication, synchronization, data-flow analysis, multi-threading, instruction scheduling
24	Steven Swanson, Andrew Schwerin, Martha Mercaldi, Andrew Petersen 0001, Andrew Putnam, Ken Michelson, Mark Oskin, Susan J. Eggers	The WaveScalar architecture.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	WaveScalar, multithreading, dataflow computing
24	Joseph J. Sharkey, Dmitry V. Ponomarev	Exploiting Operand Availability for Efficient Simultaneous Multithreading.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	simultaneous multithreading, Issue queue
24	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Jaewook Shin	Introducing Control Flow into Vectorized Code.	PACT	2007	DBLP DOI BibTeX RDF
24	Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani	AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors.	PACT	2007	DBLP DOI BibTeX RDF
24	Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis	Instruction-Level Fault Tolerance Configurability.	ICSAMOS	2007	DBLP DOI BibTeX RDF
24	Andrea Corradini 0002, Adrian Bak, Thomas Hanneforth	A Natural Language Interface for a 2D Networked Game.	HCI (4)	2007	DBLP DOI BibTeX RDF	Multiplayer Networked Game, Natural Language Processing
24	Josep M. Codina, F. Jesús Sánchez, Antonio González 0001	Virtual Cluster Scheduling Through the Scheduling Graph.	CGO	2007	DBLP DOI BibTeX RDF
24	Paul D. Bryan, Michel C. Rosier, Thomas M. Conte	Reverse State Reconstruction for Sampled Microarchitectural Simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	reverse state reconstruction, sampled microarchitectural simulation, processor simulation
24	Jatan P. Shah, Rama Sangireddy	Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Shengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu, Yiwen Wang 0003	Application-Specific Instruction Generation for SOC Processors.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Volker Paelke, Birgit Elias	Stories as Route Descriptions.	COSIT	2007	DBLP DOI BibTeX RDF
24	Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa	New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP.	PDCAT	2007	DBLP DOI BibTeX RDF
24	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	Branch predictor guided instruction decoding.	PACT	2006	DBLP DOI BibTeX RDF	complexity-effective, instruction decoding, branch predictor
24	Joseph J. Sharkey, Dmitry V. Ponomarev	Efficient instruction schedulers for SMT processors.	HPCA	2006	DBLP DOI BibTeX RDF
24	Kyle Rupnow, Arun Rodrigues, Keith D. Underwood, Katherine Compton	Scientific applications vs. SPEC-FP: a comparison of program behavior.	ICS	2006	DBLP DOI BibTeX RDF
24	Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou	Improving software security via runtime instruction-level taint checking.	ASID	2006	DBLP DOI BibTeX RDF	format string, hardware tagging, buffer overflow
24	Alex Pajuelo, Antonio González 0001, Mateo Valero	Speculative execution for hiding memory latency.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
24	Arvind Krishnaswamy, Rajiv Gupta 0001	Efficient Use of Invisible Registers in Thumb Code.	MICRO	2005	DBLP DOI BibTeX RDF
24	Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez	Checkpointed Early Load Retirement.	HPCA	2005	DBLP DOI BibTeX RDF
24	Michael D. Black, Manoj Franklin	Neural Confidence Estimation for More Accurate Value Prediction.	HiPC	2005	DBLP DOI BibTeX RDF
24	Michael Venable, Mohamed R. Chouchane, Md. Enamul Karim, Arun Lakhotia	Analyzing Memory Accesses in Obfuscated x86 Executables.	DIMVA	2005	DBLP DOI BibTeX RDF
24	Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
24	Christian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi	FSEL - Selective Predicated Execution for a Configurable DSP Core.	ISVLSI	2004	DBLP DOI BibTeX RDF
24	G. Surendra, Subhasis Banerjee, S. K. Nandy 0001	Power-performance trade-off using pipeline delays.	ASP-DAC	2004	DBLP DOI BibTeX RDF
24	Dongsoo Kang, Jean-Luc Gaudiot	Speculation Control for Simultaneous Multithreading.	IPDPS	2004	DBLP DOI BibTeX RDF
24	Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman	Scaling the issue window with look-ahead latency prediction.	ICS	2004	DBLP DOI BibTeX RDF	LHT, MNM, SILO, instruction sorting, CLP