Search results for "latches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
22	Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman	Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Dave Johnson 0003, Venkatesh Akella, Bret Stott	Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
22	Christer Svensson, Atila Alvandpour	Low power and low voltage CMOS digital circuit techniques.	ISLPED	1998	DBLP DOI BibTeX RDF	low power, CMOS, digital circuits, low voltage
22	Ellen Sentovich, Horia Toma, Gérard Berry	Efficient Latch Optimization Using Exclusive Sets.	DAC	1997	DBLP DOI BibTeX RDF
22	Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi	Automatic state space decomposition for approximate FSM traversal based on circuit analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
22	Vigyan Singhal, Sharad Malik, Robert K. Brayton	The case for retiming with explicit reset circuitry.	ICCAD	1996	DBLP DOI BibTeX RDF	reset state, synchronous reset, asynchronous reset, Retiming, initial state
22	Ellen Sentovich, Horia Toma, Gérard Berry	Latch optimization in circuits generated from high-level descriptions.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential optimisation, high-level synthesis, state assignment
22	Shaz Qadeer, Robert K. Brayton, Vigyan Singhal	Latch Redundancy Removal Without Global Reset.	ICCD	1996	DBLP DOI BibTeX RDF	global reset assumption, latch redundancy, safe replacement, delayed replacement, Finite state machine, core, strongly connected components
22	Brian Lockyear, Carl Ebeling	Optimal retiming of level-clocked circuits using symmetric clock schedules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Weiwei Mao, Michael D. Ciletti	Reducing correlation to improve coverage of delay faults in scan-path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann	Optimal latch mapping and retiming within a tree.	ICCAD	1994	DBLP DOI BibTeX RDF
21	Tamal Mandal, Debraj Kundu, Sudip Roy 0001	Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic Biochips with Latches.	VLSID	2024	DBLP DOI BibTeX RDF
21	Aibin Yan, Zhixing Li, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments.	IEEE Trans. Aerosp. Electron. Syst.	2023	DBLP DOI BibTeX RDF
21	Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno	Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops.	IEEE Access	2023	DBLP DOI BibTeX RDF
21	Samuel Ellicott, Michael Kines, Waleed Khalil	Design Space Exploration of TRNG Latches for Improved Entropy and Efficiency.	PRIME	2023	DBLP DOI BibTeX RDF
21	Jung-Jin Park, Young-Min Kang, Geon-Hak Kim, Ik-Joon Chang, Jinsang Kim	Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches.	ICEIC	2023	DBLP DOI BibTeX RDF
21	Serdar A. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Mridula Prathapan, Thomas Morf, Andrea Ruffino, Taekwang Jang	An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches.	ISSCC	2023	DBLP DOI BibTeX RDF
21	Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham	A Unified PUF and Crypto Core Exploiting the Metastability in Latches.	Future Internet	2022	DBLP DOI BibTeX RDF
21	Hyunho Park, Hanwool Jeong	Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
21	Antik Mallick, Zijian Zhao, Mohammad Khairul Bashar, Shamiul Alam, Md. Mazharul Islam 0006, Yi Xiao, Yixin Xu, Ahmedullah Aziz, Vijaykrishnan Narayanan, Kai Ni 0004, Nikhil Shukla	CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays.	CoRR	2022	DBLP DOI BibTeX RDF
21	Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu	Evaluation and Test of Production Defects in Hardened Latches.	IEICE Trans. Inf. Syst.	2022	DBLP DOI BibTeX RDF
21	Sam M.-H. Hsiao, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen	Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies.	ITC	2022	DBLP DOI BibTeX RDF
21	Zhengfeng Huang, Xiandong Li, Zhouyu Gong, Huaguo Liang, Yingchun Lu, Yiming Ouyang, Tianming Ni	Design of MNU-Resilient latches based on input-split C-elements.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
21	Aibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen	Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications.	IEEE Trans. Aerosp. Electron. Syst.	2020	DBLP DOI BibTeX RDF
21	Jan Böttcher, Viktor Leis, Jana Giceva, Thomas Neumann 0001, Alfons Kemper	Scalable and robust latches for database systems.	DaMoN	2020	DBLP DOI BibTeX RDF
21	Yukiya Miura, Yuya Kinoshita	Soft Error Tolerance of Power-Supply-Noise Hardened Latches.	IOLTS	2020	DBLP DOI BibTeX RDF
21	Chua-Chin Wang, Shao-Wei Lu	100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*.	APCCAS	2020	DBLP DOI BibTeX RDF
21	Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu	A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
21	Mojtaba Noorallahzadeh, Mohammad Mosleh	Efficient designs of reversible latches with low quantum cost.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
21	Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang	Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
21	Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De	Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.	ESSCIRC	2019	DBLP DOI BibTeX RDF
21	Martin Omaña 0001, TusharaSandeep Edara, Cecilia Metra	Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness.	IEEE Trans. Emerg. Top. Comput.	2018	DBLP DOI BibTeX RDF
21	Faisal Mustafa Sajjade, Neeraj Kumar Goyal, B. K. S. V. L. Varaprasad, Ravindra Moogina	Radiation Hardened by Design Latches - A Review and SEU Fault Simulations.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Chaudhry Indra Kumar, Anand Bulusu	Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability.	PRIME	2018	DBLP DOI BibTeX RDF
21	Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi	Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process.	IRPS	2018	DBLP DOI BibTeX RDF
21	Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata	Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology.	DSD	2018	DBLP DOI BibTeX RDF
21	Stefan Holst, Ruijun Ma, Xiaoqing Wen	The impact of production defects on the soft-error tolerance of hardened latches.	ETS	2018	DBLP DOI BibTeX RDF
21	Jeffrey T. Scruggs, Brenden S. Ritola	Hybrid Control of Vibratory Networks with Semiresonant Latches.	ACC	2018	DBLP DOI BibTeX RDF
21	Jacob Pike, Mahdi Parvizi, Naim Ben-Hamida, Sadok Aouini, Calvin Plett	New Charge-Steering Latches in 28nm CMOS for Use in High-Speed Wireline Transceivers.	ISCAS	2018	DBLP DOI BibTeX RDF
21	Christopher J. Lukas, Farah B. Yahya, Benton H. Calhoun	An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches.	ISCAS	2018	DBLP DOI BibTeX RDF
21	Ankur Shukla, Rahul M. Rao, James D. Warnock	Impact of Device Aging on Early Mode Failures in Pulsed Latches.	VLSID	2018	DBLP DOI BibTeX RDF
21	T. S. Manivannan, Meena Srinivasan	A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches.	VDAT	2018	DBLP DOI BibTeX RDF
21	Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo	Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
21	Jinn-Shyan Wang, Shih-Nung Wei	Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
21	Xueqing Li, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Meng-Fan Chang, Yongpan Liu, Suman Datta, Vijaykrishnan Narayanan	Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
21	Wael M. Elsharkasy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
21	Guo-Gin Fan, Mark Po-Hung Lin	State retention for power gated design with non-uniform multi-bit retention latches.	ICCAD	2017	DBLP DOI BibTeX RDF
21	Sha Tao, Elena Dubrova	TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches.	ISMVL	2017	DBLP DOI BibTeX RDF
21	Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera	Analytical Stability Modeling for CMOS Latches in Low Voltage Operation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
21	Naoki Tsuji, Naoki Takeuchi, Yuki Yamanashi, Thomas Ortlepp, Nobuyuki Yoshikawa	Majority Gate-Based Feedback Latches for Adiabatic Quantum Flux Parametron Logic.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
21	Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto	ASIC implementation of random number generators using SR latches and its evaluation.	EURASIP J. Inf. Secur.	2016	DBLP DOI BibTeX RDF
21	Xunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu	Design of latches and flip-flops using emerging tunneling devices.	DATE	2016	DBLP BibTeX RDF
21	Debajyoty Banik	Design of low cost latches based on reversible quantum dot cellular automata.	ISED	2016	DBLP DOI BibTeX RDF
21	R. J. E. Jansen, Scott Lindner	High-voltage tolerant bi-state self-biasing output driver using cascade complementary latches in twin-well CMOS technology.	ESSCIRC	2016	DBLP DOI BibTeX RDF
21	Jaspal Singh Shah, Manoj Sachdev	Radiation hardened pulsed-latches in 65-nm CMOS.	CCECE	2016	DBLP DOI BibTeX RDF
21	Byung-Do Yang	Low-Power and Area-Efficient Shift Register Using Pulsed Latches.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
21	Xu Hui, Zeng Yun	Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
21	Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans	TDTB error detecting latches: Timing violation sensitivity analysis and optimization.	ISQED	2015	DBLP DOI BibTeX RDF
21	Bo-Jyun Kuo, Bo-Wei Chen, Chia-Ming Tsai	A 0.6V, 1.3GHz dynamic comparator with cross-coupled latches.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
21	Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto	Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
21	Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto	Dynamic Behavior of RS latches using FIB processing and probe connection.	IACR Cryptol. ePrint Arch.	2014	DBLP BibTeX RDF
21	Taek-Joon Ahn, Kyung-Sub Son, Yong-Sung Ahn, Jin-Ku Kang	A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
21	Ignatius Bezzam, Shoba Krishnan	Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches.	VLSID	2014	DBLP DOI BibTeX RDF
21	Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto	Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
21	Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh	Variety enhancement of PUF responses using the locations of random outputting RS latches.	J. Cryptogr. Eng.	2013	DBLP DOI BibTeX RDF
21	Keisuke Inoue, Mineo Kaneko	Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF
21	Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii	Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches.	CARDIS	2013	DBLP DOI BibTeX RDF
21	Luiz Carlos Moreira, Jose Fontebasso Neto, Wilhelmus A. M. Van Noije, Emmanuel Torres-Rios	Inductorless very small 2nd derivative Gaussian IRUWB transmitter module using n/p-latches as PDs in CMOS technology.	LASCAS	2013	DBLP DOI BibTeX RDF
21	Isha Garg, Prakhar Sharma	Estimation of SNM in latches and subsequent formation of a 10T CNFET bitcell.	WISES	2013	DBLP BibTeX RDF
21	Vladimir M. Milovanovic, Horst Zimmermann	Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches.	DDECS	2012	DBLP DOI BibTeX RDF
21	Aadithya V. Karthik, Yingyan Lin, Chenjie Gu, Aolin Xu, Jaijeet S. Roychowdhury, Naresh R. Shanbhag	A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems.	ICASSP	2012	DBLP DOI BibTeX RDF
21	Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey	Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
21	Yang Lu, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi	On the design of two single event tolerant slave latches for scan delay testing.	DFT	2012	DBLP DOI BibTeX RDF
21	Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, Hiroaki Komatsu	Speed-path analysis for multi-path failed latches with random variation.	ISQED	2012	DBLP DOI BibTeX RDF
21	Ken Yano, Takanori Hayashida, Toshinori Sato	Analysis of SER Improvement by Radiation Hardened Latches.	PRDC	2012	DBLP DOI BibTeX RDF
21	S. Lin, Y.-B. Kim, Fabrizio Lombardi	Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
21	Andrey Nikolaev	Exploring Oracle RDBMS latches using Solaris DTrace	CoRR	2011	DBLP BibTeX RDF
21	Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov	Ring oscillators for functional and delay test of latches and flip-flops.	SBCCI	2011	DBLP DOI BibTeX RDF
21	Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov	Self-checking test circuits for latches and flip-flops.	IOLTS	2011	DBLP DOI BibTeX RDF
21	Chun Zhao, W. Pan, C. Z. Zhao, Ka Lok Man, J. Choi, J. Chang	Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology.	ISOCC	2011	DBLP DOI BibTeX RDF
21	Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Takao Ochiai, Masahiko Takenaka, Kouichi Itoh	Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches.	CHES	2011	DBLP DOI BibTeX RDF
21	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	High-Performance Robust Latches.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF
21	Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin	Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
21	Yngvar Berg	Static ultra-low-voltage high-speed CMOS logic and latches.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
21	A. Bhola, G. Kanitkar	Memristors and crossbar latches.	ICWET	2010	DBLP DOI BibTeX RDF
21	Himanshu Thapliyal, Nagarajan Ranganathan	Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs.	VLSI Design	2010	DBLP DOI BibTeX RDF	Quantum Cost, Delay, Sequential Circuits, Reversible Logic
21	Jaejun Lee, Sungho Lee, Yonghoon Song, Sangwook Nam	High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
21	Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni	All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates.	OSC	2009	DBLP DOI BibTeX RDF	optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA)
21	Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi	Soft-Error Hardening Designs of Nanoscale CMOS Latches.	VTS	2009	DBLP DOI BibTeX RDF
21	Serban E. Vlad	The equations of the ideal latches	CoRR	2008	DBLP BibTeX RDF
21	Jacqueline E. Rice	An Introduction to Reversible Latches.	Comput. J.	2008	DBLP DOI BibTeX RDF
21	Gaetano Palumbo, Melita Pennisi	Design guidelines for high-speed Transmission-gate latches: Analysis and comparison.	ICECS	2008	DBLP DOI BibTeX RDF
21	Xu Cheng, Russell Duane	Measurement and Analysis of PD-SOI Static Latches Based on Bistable-Gated-Bipolar Device.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Raul Fernández, Rosana Rodríguez, Montserrat Nafría, Xavier Aymerich	Effect of oxide breakdown on RS latches.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
21	Visvesh S. Sathe 0001, Jerry C. Kao, Marios C. Papaefthymiou	A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches.	CICC	2007	DBLP DOI BibTeX RDF
21	Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu	Design of ultra low power CML MUXs and latches with forward body bias.	SoCC	2007	DBLP DOI BibTeX RDF
21	Xiaoqiang Shou, Nader Kalantari, Michael M. Green	Design of CMOS Ternary Latches.	IEEE Trans. Circuits Syst. I Regul. Pap.	2006	DBLP DOI BibTeX RDF
21	Martin Hansson, Atila Alvandpour	A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOS.	SoCC	2006	DBLP DOI BibTeX RDF
21	Kazuteru Namba, Hideo Ito	Scan Design for Two-Pattern Test without Extra Latches.	IEICE Trans. Inf. Syst.	2005	DBLP DOI BibTeX RDF