Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Ayoob E. Dooply, Kenneth Y. Yun |
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 200-214, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault |
22 | Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman |
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 314-317, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Dave Johnson 0003, Venkatesh Akella, Bret Stott |
Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 731-740, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Christer Svensson, Atila Alvandpour |
Low power and low voltage CMOS digital circuit techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 7-10, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, CMOS, digital circuits, low voltage |
22 | Ellen Sentovich, Horia Toma, Gérard Berry |
Efficient Latch Optimization Using Exclusive Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 8-11, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi |
Automatic state space decomposition for approximate FSM traversal based on circuit analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12), pp. 1451-1464, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Vigyan Singhal, Sharad Malik, Robert K. Brayton |
The case for retiming with explicit reset circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 618-625, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reset state, synchronous reset, asynchronous reset, Retiming, initial state |
22 | Ellen Sentovich, Horia Toma, Gérard Berry |
Latch optimization in circuits generated from high-level descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 428-435, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
sequential optimisation, high-level synthesis, state assignment |
22 | Shaz Qadeer, Robert K. Brayton, Vigyan Singhal |
Latch Redundancy Removal Without Global Reset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 432-439, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
global reset assumption, latch redundancy, safe replacement, delayed replacement, Finite state machine, core, strongly connected components |
22 | Brian Lockyear, Carl Ebeling |
Optimal retiming of level-clocked circuits using symmetric clock schedules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1097-1109, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Weiwei Mao, Michael D. Ciletti |
Reducing correlation to improve coverage of delay faults in scan-path design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5), pp. 638-646, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann |
Optimal latch mapping and retiming within a tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 242-245, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Tamal Mandal, Debraj Kundu, Sudip Roy 0001 |
Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic Biochips with Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 419-424, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Aibin Yan, Zhixing Li, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen |
Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Aerosp. Electron. Syst. ![In: IEEE Trans. Aerosp. Electron. Syst. 59(3), pp. 2885-2897, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno |
Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 35830-35840, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Samuel Ellicott, Michael Kines, Waleed Khalil |
Design Space Exploration of TRNG Latches for Improved Entropy and Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 18th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023, Valencia, Spain, June 18-21, 2023, pp. 229-232, 2023, IEEE, 979-8-3503-0320-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Jung-Jin Park, Young-Min Kang, Geon-Hak Kim, Ik-Joon Chang, Jinsang Kim |
Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2023, Singapore, February 5-8, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2021-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Serdar A. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Mridula Prathapan, Thomas Morf, Andrea Ruffino, Taekwang Jang |
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 266-267, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham |
A Unified PUF and Crypto Core Exploiting the Metastability in Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Internet ![In: Future Internet 14(10), pp. 298, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Hyunho Park, Hanwool Jeong |
Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(11), pp. 1728-1738, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Antik Mallick, Zijian Zhao, Mohammad Khairul Bashar, Shamiul Alam, Md. Mazharul Islam 0006, Yi Xiao, Yixin Xu, Ahmedullah Aziz, Vijaykrishnan Narayanan, Kai Ni 0004, Nikhil Shukla |
CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.14729, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu |
Evaluation and Test of Production Defects in Hardened Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 105-D(5), pp. 996-1009, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Sam M.-H. Hsiao, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen |
Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2022, Anaheim, CA, USA, September 23-30, 2022, pp. 128-136, 2022, IEEE, 978-1-6654-6270-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Zhengfeng Huang, Xiandong Li, Zhouyu Gong, Huaguo Liang, Yingchun Lu, Yiming Ouyang, Tianming Ni |
Design of MNU-Resilient latches based on input-split C-elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 116, pp. 105243, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Aibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen |
Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Aerosp. Electron. Syst. ![In: IEEE Trans. Aerosp. Electron. Syst. 56(5), pp. 3931-3940, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Jan Böttcher, Viktor Leis, Jana Giceva, Thomas Neumann 0001, Alfons Kemper |
Scalable and robust latches for database systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DaMoN ![In: 16th International Workshop on Data Management on New Hardware, DaMoN 2020, Portland, Oregon, USA, June 15, 2020, pp. 2:1-2:8, 2020, ACM, 978-1-4503-8024-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Yukiya Miura, Yuya Kinoshita |
Soft Error Tolerance of Power-Supply-Noise Hardened Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 26th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2020, Napoli, Italy, July 13-15, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-8187-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Chua-Chin Wang, Shao-Wei Lu |
100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020, Ha Long, Vietnam, December 8-10, 2020, pp. 98-101, 2020, IEEE, 978-1-7281-9396-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu |
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(9), pp. 2170-2179, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Mojtaba Noorallahzadeh, Mohammad Mosleh |
Efficient designs of reversible latches with low quantum cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(6), pp. 806-815, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang |
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 66-II(8), pp. 1386-1390, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De |
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1550-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Martin Omaña 0001, TusharaSandeep Edara, Cecilia Metra |
Low-Cost Strategy to Mitigate the Impact of Aging on Latches' Robustness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 6(4), pp. 488-497, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Faisal Mustafa Sajjade, Neeraj Kumar Goyal, B. K. S. V. L. Varaprasad, Ravindra Moogina |
Radiation Hardened by Design Latches - A Review and SEU Fault Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 83, pp. 127-135, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Chaudhry Indra Kumar, Anand Bulusu |
Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018, Prague, Czech Republic, July 2-5, 2018, pp. 101-104, 2018, IEEE, 978-1-5386-5387-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi |
Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 3-1, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata |
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018, pp. 508-515, 2018, IEEE Computer Society, 978-1-5386-7377-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Stefan Holst, Ruijun Ma, Xiaoqing Wen |
The impact of production defects on the soft-error tolerance of hardened latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 23rd IEEE European Test Symposium, ETS 2018, Bremen, Germany, May 28 - June 1, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-3728-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Jeffrey T. Scruggs, Brenden S. Ritola |
Hybrid Control of Vibratory Networks with Semiresonant Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACC ![In: 2018 Annual American Control Conference, ACC 2018, Milwaukee, WI, USA, June 27-29, 2018, pp. 1452-1459, 2018, IEEE, 978-1-5386-5428-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Jacob Pike, Mahdi Parvizi, Naim Ben-Hamida, Sadok Aouini, Calvin Plett |
New Charge-Steering Latches in 28nm CMOS for Use in High-Speed Wireline Transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Christopher J. Lukas, Farah B. Yahya, Benton H. Calhoun |
An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-4, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Ankur Shukla, Rahul M. Rao, James D. Warnock |
Impact of Device Aging on Early Mode Failures in Pulsed Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018, pp. 256-260, 2018, IEEE Computer Society, 978-1-5386-3692-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | T. S. Manivannan, Meena Srinivasan |
A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers, pp. 521-537, 2018, Springer, 978-981-13-5949-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo |
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(12), pp. 3509-3520, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Jinn-Shyan Wang, Shih-Nung Wei |
Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(10), pp. 2893-2906, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Xueqing Li, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Meng-Fan Chang, Yongpan Liu, Suman Datta, Vijaykrishnan Narayanan |
Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(11), pp. 2907-2919, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Wael M. Elsharkasy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi |
Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7), pp. 1803-1814, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Guo-Gin Fan, Mark Po-Hung Lin |
State retention for power gated design with non-uniform multi-bit retention latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, pp. 607-614, 2017, IEEE, 978-1-5386-3093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Sha Tao, Elena Dubrova |
TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 47th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2017, Novi Sad, Serbia, May 22-24, 2017, pp. 130-135, 2017, IEEE Computer Society, 978-1-5090-5496-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12), pp. 2463-2472, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Naoki Tsuji, Naoki Takeuchi, Yuki Yamanashi, Thomas Ortlepp, Nobuyuki Yoshikawa |
Majority Gate-Based Feedback Latches for Adiabatic Quantum Flux Parametron Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(6), pp. 710-716, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto |
ASIC implementation of random number generators using SR latches and its evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Inf. Secur. ![In: EURASIP J. Inf. Secur. 2016, pp. 10, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Xunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu |
Design of latches and flip-flops using emerging tunneling devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 367-372, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
21 | Debajyoty Banik |
Design of low cost latches based on reversible quantum dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016, pp. 181-186, 2016, IEEE, 978-1-5090-2541-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | R. J. E. Jansen, Scott Lindner |
High-voltage tolerant bi-state self-biasing output driver using cascade complementary latches in twin-well CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 281-284, 2016, IEEE, 978-1-5090-2972-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Jaspal Singh Shah, Manoj Sachdev |
Radiation hardened pulsed-latches in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 2016 IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2016, Vancouver, BC, Canada, May 15-18, 2016, pp. 1-4, 2016, IEEE, 978-1-4673-8721-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Byung-Do Yang |
Low-Power and Area-Efficient Shift Register Using Pulsed Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6), pp. 1564-1571, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Xu Hui, Zeng Yun |
Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 12(9), pp. 20150286, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans |
TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 379-383, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Bo-Jyun Kuo, Bo-Wei Chen, Chia-Ming Tsai |
A 0.6V, 1.3GHz dynamic comparator with cross-coupled latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-6275-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto |
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(7), pp. 1593-1605, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto |
Dynamic Behavior of RS latches using FIB processing and probe connection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2014, pp. 870, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
21 | Taek-Joon Ahn, Kyung-Sub Son, Yong-Sung Ahn, Jin-Ku Kang |
A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 11(17), pp. 20140657, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Ignatius Bezzam, Shoba Krishnan |
Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 2014 27th International Conference on VLSI Design, VLSID 2014, and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, pp. 156-161, 2014, IEEE Computer Society, 978-1-4799-2513-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Andrea Ghilioni, Andrea Mazzanti, Francesco Svelto |
Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(8), pp. 1842-1850, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh |
Variety enhancement of PUF responses using the locations of random outputting RS latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptogr. Eng. ![In: J. Cryptogr. Eng. 3(4), pp. 197-211, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Keisuke Inoue, Mineo Kaneko |
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(8), pp. 1712-1722, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii |
Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CARDIS ![In: Smart Card Research and Advanced Applications - 12th International Conference, CARDIS 2013, Berlin, Germany, November 27-29, 2013. Revised Selected Papers, pp. 3-15, 2013, Springer, 978-3-319-08301-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Luiz Carlos Moreira, Jose Fontebasso Neto, Wilhelmus A. M. Van Noije, Emmanuel Torres-Rios |
Inductorless very small 2nd derivative Gaussian IRUWB transmitter module using n/p-latches as PDs in CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 4th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2013, Cusco, Peru, February 27 - March 1, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-4897-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Isha Garg, Prakhar Sharma |
Estimation of SNM in latches and subsequent formation of a 10T CNFET bitcell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISES ![In: Proceedings of the 11th Workshop on Intelligent Solutions in Embedded Systems, WISES 2013, Pilsen, Czech Republic, September 10-11, 2013, pp. 1-5, 2013, IEEE, 978-3-00-042899-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
21 | Vladimir M. Milovanovic, Horst Zimmermann |
Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012, pp. 360-365, 2012, IEEE, 978-1-4673-1187-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Aadithya V. Karthik, Yingyan Lin, Chenjie Gu, Aolin Xu, Jaijeet S. Roychowdhury, Naresh R. Shanbhag |
A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 2012 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2012, Kyoto, Japan, March 25-30, 2012, pp. 5289-5292, 2012, IEEE, 978-1-4673-0046-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey |
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, pp. 482-484, 2012, IEEE, 978-1-4673-0376-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Yang Lu, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi |
On the design of two single event tolerant slave latches for scan delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, pp. 67-72, 2012, IEEE Computer Society, 978-1-4673-3043-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, Hiroaki Komatsu |
Speed-path analysis for multi-path failed latches with random variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 545-552, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Ken Yano, Takanori Hayashida, Toshinori Sato |
Analysis of SER Improvement by Radiation Hardened Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: IEEE 18th Pacific Rim International Symposium on Dependable Computing, PRDC 2012, Niigata, Japan, November 18-19, 2012, pp. 89-95, 2012, IEEE Computer Society, 978-1-4673-4849-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | S. Lin, Y.-B. Kim, Fabrizio Lombardi |
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(7), pp. 1315-1319, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Andrey Nikolaev |
Exploring Oracle RDBMS latches using Solaris DTrace ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1111.0594, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
21 | Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov |
Ring oscillators for functional and delay test of latches and flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011, pp. 67-72, 2011, ACM, 978-1-4503-0828-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov |
Self-checking test circuits for latches and flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, pp. 210-213, 2011, IEEE Computer Society, 978-1-4577-1053-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Chun Zhao, W. Pan, C. Z. Zhao, Ka Lok Man, J. Choi, J. Chang |
Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011, pp. 313-316, 2011, IEEE, 978-1-4577-0709-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Takao Ochiai, Masahiko Takenaka, Kouichi Itoh |
Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28 - October 1, 2011. Proceedings, pp. 390-406, 2011, Springer, 978-3-642-23950-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra |
High-Performance Robust Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(11), pp. 1455-1465, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin |
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3), pp. 355-366, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Yngvar Berg |
Static ultra-low-voltage high-speed CMOS logic and latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010, pp. 115-118, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | A. Bhola, G. Kanitkar |
Memristors and crossbar latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26 - 27, 2010, pp. 915-918, 2010, ACM, 978-1-60558-812-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Himanshu Thapliyal, Nagarajan Ranganathan |
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 235-240, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Quantum Cost, Delay, Sequential Circuits, Reversible Logic |
21 | Jaejun Lee, Sungho Lee, Yonghoon Song, Sangwook Nam |
High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 92-C(12), pp. 1548-1550, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni |
All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OSC ![In: Optical SuperComputing, Second International Workshop, OSC 2009, Bertinoro, Italy, November 18-20, 2009. Proceedings, pp. 5-18, 2009, Springer, 978-3-642-10441-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA) |
21 | Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi |
Soft-Error Hardening Designs of Nanoscale CMOS Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 41-46, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Serban E. Vlad |
The equations of the ideal latches ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/0804.0879, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
21 | Jacqueline E. Rice |
An Introduction to Reversible Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 51(6), pp. 700-709, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Gaetano Palumbo, Melita Pennisi |
Design guidelines for high-speed Transmission-gate latches: Analysis and comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 145-148, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Xu Cheng, Russell Duane |
Measurement and Analysis of PD-SOI Static Latches Based on Bistable-Gated-Bipolar Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(11), pp. 2585-2593, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Raul Fernández, Rosana Rodríguez, Montserrat Nafría, Xavier Aymerich |
Effect of oxide breakdown on RS latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 47(4-5), pp. 581-584, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Visvesh S. Sathe 0001, Jerry C. Kao, Marios C. Papaefthymiou |
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 583-586, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu |
Design of ultra low power CML MUXs and latches with forward body bias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2007 IEEE International SOC Conference, Tampere, Finland, November 19-21, 2007, pp. 141-144, 2007, IEEE, 978-1-4244-1592-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Xiaoqiang Shou, Nader Kalantari, Michael M. Green |
Design of CMOS Ternary Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12), pp. 2588-2594, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Martin Hansson, Atila Alvandpour |
A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006, pp. 83-84, 2006, IEEE, 0-7803-9781-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Kazuteru Namba, Hideo Ito |
Scan Design for Two-Pattern Test without Extra Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 88-D(12), pp. 2777-2785, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|