Search results for "macromodels"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
24	Flavio G. Canavero, Stefano Grivet-Talocia, Ivan A. Maio, Igor S. Stievano	Linear and Nonlinear Macromodels for System-Level Signal Integrity and EMC Assessment.	IEICE Trans. Commun.	2005	DBLP DOI BibTeX RDF
24	Emad Gad, Changzhong Chen, Michel S. Nakhla, Ramachandra Achar	Passivity verification in delay-based macromodels of electrical interconnects.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
24	Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis	Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
24	Anuradha Agarwal, Ranga Vemuri	Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits.	ICCAD	2005	DBLP DOI BibTeX RDF
24	Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla	Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
24	Mamoru Ugajin, Akihiro Yamagishi, Junichi Kodate, Mitsuru Harada, Tsuneo Tsukahara	Macromodels in the frequency domain analysis of microwave resonators.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
24	Ning Dong 0002, Jaijeet Roychowdhury	Automated extraction of broadly applicable nonlinear analog macromodels from SPICE-level descriptions.	CICC	2004	DBLP DOI BibTeX RDF
24	Hui Zheng, Byron Krauter, Lawrence T. Pileggi	On-package decoupling optimization with package macromodels.	CICC	2003	DBLP DOI BibTeX RDF
24	Timo Palenius, Janne Roos, Sakari Aaltonen	Development and comparison of reduced-order interconnect macromodels for time-domain simulation.	ICECS	2002	DBLP DOI BibTeX RDF
24	Sakari Aaltonen, Janne Roos	Simple reduced-order macromodels with PRIMA.	ICECS	2002	DBLP DOI BibTeX RDF
24	Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla	Passive closed-form time-domain macromodels for on-chip distributed RC interconnects.	CICC	2002	DBLP DOI BibTeX RDF
24	Manuela Anton, Ionel Colonescu, Enrico Macii, Massimo Poncino	Fast characterization of RTL power macromodels.	ICECS	2001	DBLP DOI BibTeX RDF
24	Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla	A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations.	ICECS	2001	DBLP DOI BibTeX RDF
24	Eduardo A. C. da Costa, Fernando Paixão Cortes, Rodrigo Ferrugem Cardoso, Luigi Carro, Sergio Bampi	Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels.	SBCCI	2000	DBLP BibTeX RDF
24	Joel R. Phillips	Automated extraction of nonlinear circuit macromodels.	CICC	2000	DBLP DOI BibTeX RDF
24	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	The Use of Macromodels on Op-Amp Circuits Fault Modeling.	LATW	2000	DBLP BibTeX RDF
24	Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick	Efficient RLC Macromodels for Digital IC Interconnect.	VLSI	1999	DBLP BibTeX RDF
24	Alessandro Bogliolo, Luca Benini	Robust RTL power macromodels.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
24	Vjaceslav Georgiev, Elissaveta Gadjeva, K. Stanchev	Nonlinear macromodels for time-domain simulation of analog-discrete circuits.	ICECS	1998	DBLP DOI BibTeX RDF
24	Bruno Franzini, Cristiano Forzan, Davide Pandini, Y. Liu, Carlo Guardiani	Nonlinear macromodels of large coupled interconnect networks.	CICC	1998	DBLP DOI BibTeX RDF
24	E. Aykut Dengi, Ronald A. Rohrer	Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
24	Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi	RC-Interconnect Macromodels for Timing Simulation.	DAC	1996	DBLP DOI BibTeX RDF
24	Haifang Liao, Wayne Wei-Ming Dai	Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels.	ICCAD	1995	DBLP DOI BibTeX RDF	circuit reduction, scattering parameter, interconnect network, macromodel, Circuit partitioning, circuit synthesis
24	Jeong-Taek Kong, David Overhauser	Combining RC-Interconnect Effects with Nonlinear MOS Macromodels.	ISCAS	1995	DBLP DOI BibTeX RDF
24	Ivan L. Wemple, Andrew T. Yang	Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels.	DAC	1995	DBLP DOI BibTeX RDF
24	Ion Constatin Tesu, Florentin Dartu	Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits.	ISCAS	1993	DBLP BibTeX RDF
24	D. Golzio, S. Graffi, Zsolt Miklós Kovács-Vajna, G. Masetti	Circuit macromodels and large-signal behaviour of fet-input operational amplifiers.	Int. J. Circuit Theory Appl.	1992	DBLP DOI BibTeX RDF
24	Ayman I. Kayssi, Karem A. Sakallah	Delay macromodels for the timing analysis of GaAs DCFL.	EURO-DAC	1992	DBLP DOI BibTeX RDF
24	Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage	AWE macromodels of VLSI interconnect for circuit simulation.	ICCAD	1992	DBLP DOI BibTeX RDF
14	Hao Yu 0001, Joanna Ho, Lei He 0001	Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Thermal and power integrity, parametric 3D-IC design, macromodeling
14	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space.	VLSI Design	2009	DBLP DOI BibTeX RDF
14	Ying Wei 0002, Alex Doboli	Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
14	Yunsi Fei, Lin Zhong 0001, Niraj K. Jha	An energy-aware framework for dynamic software management in mobile computing systems.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	energy macromodel, runtime coordination, Software adaptation
14	Michael P. Reyes, Ronald S. Fearing	Macromodel for the mechanics of gecko hair adhesion.	ICRA	2008	DBLP DOI BibTeX RDF
14	Prateek Bhansali, Shweta Srivastava, Xiaolue Lai, Jaijeet S. Roychowdhury	Comprehensive procedure for fast and accurate coupled oscillator network simulation.	ICCAD	2008	DBLP DOI BibTeX RDF
14	Chenjie Gu, Jaijeet S. Roychowdhury	Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems.	ICCAD	2008	DBLP DOI BibTeX RDF
14	Likun Xia, Ian M. Bell, Antony J. Wilkinson	A novel approach for automated model generation.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Almitra Pradhan, Ranga Vemuri	On the Use of Hash Tables for Efficient Analog Circuit Synthesis.	VLSI Design	2008	DBLP DOI BibTeX RDF
14	Taha Amiralli, Anestis Dounavis	Macromodeling for Nonlinear Distributed Interconnect Networks.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Chun-Hsu Ko, Jin-Chern Chiou	Fuzzy macromodel for dynamic simulation of microelectromechanical systems.	IEEE Trans. Syst. Man Cybern. Part A	2006	DBLP DOI BibTeX RDF
14	Dmitry Vasilyev, Michal Rewienski, Jacob K. White 0001	Macromodel Generation for BioMEMS Components Using a Stabilized Balanced Truncation Plus Trajectory Piecewise-Linear Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	RTL-Aware Cycle-Accurate Functional Power Estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Jaskirat Singh, Sachin S. Sapatnekar	Partition-Based Algorithm for Power Grid Design Using Locality.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	B. Haddadin, Min Ma, T. S. Roseanu, Roni Khazaka	Efficient Macromodel for Interconnects Excited by Incident Fields.	CCECE	2006	DBLP DOI BibTeX RDF
14	Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin	Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.	VLSI Design	2006	DBLP DOI BibTeX RDF
14	Shweta Chary, Michael L. Bushnell	Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
14	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Peng Li 0001, Lawrence T. Pileggi	Compact reduced-order modeling of weakly nonlinear analog and RF circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Mengmeng Ding, Ranga Vemuri	A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling.	DATE	2005	DBLP DOI BibTeX RDF
14	Jaskirat Singh, Sachin S. Sapatnekar	A fast algorithm for power grid design.	ISPD	2005	DBLP DOI BibTeX RDF	power grid design, wire pitch, optimization, locality, macromodel, bipartitioning
14	Yuichi Tanji, Hidemasa Kubota	Passive approximation of tabulated frequency-data by Fourier expansion method.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
14	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
14	Saurabh K. Tiwary, Rob A. Rutenbar	Scalable trajectory methods for on-demand analog macromodel extraction.	DAC	2005	DBLP DOI BibTeX RDF	trajectory method, analog, SPICE, circuit, macromodel
14	Thomas Brandtner, Robert Weigel	SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level.	DATE	2004	DBLP DOI BibTeX RDF
14	Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury	Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction.	DATE	2004	DBLP DOI BibTeX RDF
14	Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang	Realizable parasitic reduction for distributed interconnects using matrix pencil technique.	ASP-DAC	2004	DBLP DOI BibTeX RDF
14	Igor Keller, Ken Tseng, Nishath K. Verghese	A robust cell-level crosstalk delay change analysis.	ICCAD	2004	DBLP DOI BibTeX RDF
14	Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang 0006, Gong Ouyang, Rob Sharpe, John W. Rockway	Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.	ISQED	2004	DBLP DOI BibTeX RDF
14	Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.	DAC	2004	DBLP DOI BibTeX RDF	modeling, synthesis, layout, sizing, parasitic, radio frequency
14	Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.	DAC	2004	DBLP DOI BibTeX RDF	modeling, model order reduction, substrate noise
14	Michal Rewienski, Jacob K. White 0001	A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
14	Fei Li 0003, Deming Chen, Lei He 0001, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
14	Takayuki Watanabe, Hideki Asai	Analysis of PCB interconnects using electromagnetic reduction technique.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
14	Dmitry Vasilyev, Michal Rewienski, Jacob White 0001	A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS.	DAC	2003	DBLP DOI BibTeX RDF	truncated balanced realization, nonlinear systems, model order reduction
14	Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen	Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
14	Tamal Mukherjee, Gary K. Fedder, Deepak Ramaswamy, Jacob K. White 0001	Emerging simulation approaches for micromachined devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
14	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli	Regression-based RTL power modeling.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	RTL power modeling, adaptive characterization, functional macros, regression models, RTL design
14	Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon	Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.	PATMOS	2000	DBLP DOI BibTeX RDF
14	Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino	Power Models for Semi-autonomous RTL Macros.	PATMOS	2000	DBLP DOI BibTeX RDF
14	Joel R. Phillips	Projection frameworks for model reduction of weakly nonlinear systems.	DAC	2000	DBLP DOI BibTeX RDF
14	Chandramouli V. Kashyap, Byron Krauter	A realizable driving point model for on-chip interconnect with inductance.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
14	Jaijeet S. Roychowdhury	Reduced-Order Modelling of Time-Varying Systems.	ASP-DAC	1999	DBLP DOI BibTeX RDF
14	Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag	Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.	VLSI Design	1999	DBLP DOI BibTeX RDF
14	S. Turgis, Daniel Auvergne	A novel macromodel for power estimation in CMOS structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
14	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	PRIMA: passive reduced-order interconnect macromodeling algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
14	Ralf Rosenberger, Sorin A. Huss	A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks.	DATE	1998	DBLP DOI BibTeX RDF	analog modeling, simulation methodologies
14	Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha P. Chandrakasan	Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT.	DAC	1997	DBLP DOI BibTeX RDF
14	Ivan L. Wemple, Andrew T. Yang	Integrated circuit substrate coupling models based on Voronoi tessellation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
14	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	A comprehensive fault macromodel for opamps.	ICCAD	1994	DBLP DOI BibTeX RDF
14	Jianfeng Shao, Ramesh Harjani	Macromodeling of analog circuits for hierarchical circuit design.	ICCAD	1994	DBLP DOI BibTeX RDF